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Nacho Navarro
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2020 – today
- 2024
- [i3]Ran Zmigrod, Dongsheng Wang, Mathieu Sibue, Yulong Pei, Petr Babkin, Ivan Brugere, Xiaomo Liu, Nacho Navarro, Antony Papadimitriou, William Watson, Zhiqiang Ma, Armineh Nourbakhsh, Sameena Shah:
BuDDIE: A Business Document Dataset for Multi-task Information Extraction. CoRR abs/2404.04003 (2024) - 2023
- [c57]Nacho Navarro, Salwa Alamir, Petr Babkin, Sameena Shah:
An Automated Code Update Tool For Python Packages. ICSME 2023: 536-540 - 2022
- [c56]Salwa Alamir, Petr Babkin, Nacho Navarro, Sameena Shah:
AI for Automated Code Updates. ICSE (SEIP) 2022: 25-26 - [i2]Petr Babkin, Nacho Navarro, Salwa Alamir, Sameena Shah:
Neural Transition-based Parsing of Library Deprecations. CoRR abs/2212.12584 (2022)
2010 – 2019
- 2017
- [j21]Victor Garcia, Alejandro Rico, Carlos Villavieja, Paul M. Carpenter
, Nacho Navarro, Alex Ramírez:
Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors. Int. J. Parallel Program. 45(3): 530-550 (2017) - [j20]Diego Marron, Jesse Read, Albert Bifet
Data stream classification using random feature functions and novel method combinations. J. Syst. Softw. 127: 195-204 (2017) - [c55]Lluís Vilanova
Direct Inter-Process Communication (dIPC): Repurposing the CODOMs Architecture to Accelerate IPC. EuroSys 2017: 16-31 - [c54]Matina Maria Trompouki
An open benchmark implementation for multi-CPU multi-GPU pedestrian detection in automotive systems. ICCAD 2017: 305-312 - [c53]Ivan Tanasic, Isaac Gelado, Marc Jordà, Eduard Ayguadé, Nacho Navarro:
Efficient exception handling support for GPUs. MICRO 2017: 109-122 - 2016
- [j19]Raúl de la Cruz
Optimization of atmospheric transport models on HPC platforms. Comput. Geosci. 97: 30-39 (2016) - [j18]Carlos Álvarez
The AXIOM software layers. Microprocess. Microsystems 47: 262-277 (2016) - 2015
- [j17]Lluc Alvarez
Hardware-Software Coherence Protocol for the Coexistence of Caches and Local Memories. IEEE Trans. Computers 64(1): 152-165 (2015) - [j16]Javier Cabezas, Isaac Gelado, John E. Stone
Runtime and Architecture Support for Efficient Data Exchange in Multi-Accelerator Applications. IEEE Trans. Parallel Distributed Syst. 26(5): 1405-1418 (2015) - [c52]Carlos Álvarez
The AXIOM Software Layers. DSD 2015: 117-124 - [c51]Javier Cabezas, Lluís Vilanova
Automatic Parallelization of Kernels in Shared-Memory Multi-GPU Nodes. ICS 2015: 3-13 - [c50]Lluis Gifre
iONE: An environment for experimentally assessing in-operation network planning algorithms. ICTON 2015: 1-4 - [c49]Lluc Alvarez
Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. ISCA 2015: 720-732 - [c48]Javier Cabezas, Marc Jordà
GPU-SM: shared memory multi-GPU programming. GPGPU@PPoPP 2015: 13-24 - [c47]Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos
The AXIOM project (Agile, eXtensible, fast I/O Module). SAMOS 2015: 262-269 - [i1]Diego Marron, Jesse Read, Albert Bifet, Nacho Navarro:
Data Stream Classification using Random Feature Functions and Novel Method Combinations. CoRR abs/1511.00971 (2015) - 2014
- [j15]Roberto Giorgi, Rosa M. Badia
TERAFLUX: Harnessing dataflow in next generation teradevices. Microprocess. Microsystems 38(8): 976-990 (2014) - [c46]Javier Cabezas, Lluís Vilanova
Automatic execution of single-GPU computations across multiple GPUs. PACT 2014: 467-468 - [c45]Branimir Dickov, Miquel Pericàs, Paul M. Carpenter
Software-Managed Power Reduction in Infiniband Links. ICPP 2014: 311-320 - [c44]Lluis Gifre
An in-operation planning tool architecture for flexgrid network re-optimization. ICTON 2014: 1-4 - [c43]Ivan Tanasic, Isaac Gelado, Javier Cabezas, Alex Ramírez, Nacho Navarro, Mateo Valero
Enabling preemptive multiprogramming on GPUs. ISCA 2014: 193-204 - [c42]Lluís Vilanova
CODOMs: Protecting software with Code-centric memory Domains. ISCA 2014: 469-480 - [c41]Lluis Gifre
Experimental assessment of a high performance backend PCE for flexgrid optical network re-optimization. OFC 2014: 1-3 - [c40]Branimir Dickov, Miquel Pericàs, Paul M. Carpenter
Analyzing Performance Improvements and Energy Savings in Infiniband Architecture using Network Compression. SBAC-PAD 2014: 73-80 - 2013
- [j14]Ramon Bertran
Counter-Based Power Modeling Methods: Top-Down vs. Bottom-Up. Comput. J. 56(2): 198-213 (2013) - [j13]Muhammad Shafiq
A template system for the efficient compilation of domain abstractions onto reconfigurable computers. J. Syst. Archit. 59(2): 91-102 (2013) - [j12]Ramon Bertran
A Systematic Methodology to Generate Decomposable and Responsive Power Models for CMPs. IEEE Trans. Computers 62(7): 1289-1302 (2013) - [c39]Ivan Tanasic, Lluís Vilanova
Comparison based sorting for systems with multiple GPUs. GPGPU@ASPLOS 2013: 1-11 - [c38]Marco Solinas, Rosa M. Badia
The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices. DSD 2013: 272-279 - 2012
- [j11]Ramon Bertran
Energy accounting for shared virtualized environments under DVFS using PMC-based power models. Future Gener. Comput. Syst. 28(2): 457-468 (2012) - [c37]Tassadaq Hussain, Muhammad Shafiq
PPMC: A Programmable Pattern Based Memory Controller. ARC 2012: 89-101 - [c36]Muhammad Shafiq
BSArc: blacksmith streaming architecture for HPC accelerators. Conf. Computing Frontiers 2012: 23-32 - [c35]Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé
PPMC: Hardware scheduling and memory management support for multi accelerators. FPL 2012: 571-574 - [c34]Branimir Dickov, Miquel Pericàs, Guillaume Houzeaux
Assessing the Impact of Network Compression on Molecular Dynamics and Finite Element Methods. HPCC-ICESS 2012: 588-597 - [c33]Lluc Alvarez
Hardware-software coherence protocol for the coexistence of caches and local memories. SC 2012: 89 - [c32]Ramon Bertran
POTRA: a framework for building power models for next generation multicore architectures. SIGMETRICS 2012: 427-428 - 2011
- [j10]Ramon Bertran
Local Memory Design Space Exploration for High-Performance Computing. Comput. J. 54(5): 786-799 (2011) - [j9]Mauricio Araya-Polo, Javier Cabezas, Mauricio Hanzich
Assessing Accelerator-Based HPC Reverse Time Migration. IEEE Trans. Parallel Distributed Syst. 22(1): 147-162 (2011) - [c31]Carlos Villavieja, Vasileios Karakostas, Lluís Vilanova
DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory. PACT 2011: 340-349 - [c30]Carlos Villavieja, Yoav Etsion, Alex Ramírez, Nacho Navarro:
FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores. Euro-Par (1) 2011: 282-294 - [c29]Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Eduard Ayguadé
Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool. FPT 2011: 1-8 - [c28]Lluc Alvarez
Design space exploration for aggressive core replication schemes in CMPs. HPDC 2011: 269-270 - [c27]Muhammad Shafiq
TARCAD: A template architecture for reconfigurable accelerator designs. SASP 2011: 8-15 - 2010
- [j8]Mateo Valero
Multicore: The View from Europe. IEEE Micro 30(5): 2-4 (2010) - [c26]Isaac Gelado, Javier Cabezas, Nacho Navarro, John E. Stone
An asymmetric distributed shared memory model for heterogeneous parallel systems. ASPLOS 2010: 347-358 - [c25]Muhammad Shafiq
FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators. FPL 2010: 568-573 - [c24]Ramon Bertran
Decomposable and responsive power models for multicore processors using performance counters. ICS 2010: 147-158
2000 – 2009
- 2009
- [j7]Steven S. Lumetta, Nacho Navarro:
CASES 2007 guest editors' introduction. Des. Autom. Embed. Syst. 13(1-2): 89 (2009) - [j6]Jordi Llosa, Ignasi Vilajosana, Xavier Vilajosana
REMOTE, a Wireless Sensor Network Based System to Monitor Rowing Performance. Sensors 9(9): 7069-7082 (2009) - [j5]Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere:
Linux Kernel Compaction through Cold Code Swapping. Trans. High Perform. Embed. Archit. Compil. 2: 173-200 (2009) - [c23]Muhammad Shafiq
Exploiting memory customization in FPGA for 3D stencil computations. FPT 2009: 38-45 - [c22]Víctor J. Jiménez, Lluís Vilanova
Predictive Runtime Code Scheduling for Heterogeneous Architectures. HiPEAC 2009: 19-33 - [c21]Julio Merino, Lluc Alvarez
Cetra: A trace and analysis framework for the evaluation of Cell BE systems. ISPASS 2009: 43-52 - [c20]Javier Cabezas, Mauricio Araya-Polo, Isaac Gelado, Nacho Navarro, Enric Morancho, José María Cela
High-Performance Reverse Time Migration on GPU. SCCC 2009: 77-86 - 2008
- [c19]Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu:
CUBA: an architecture for efficient CPU/co-processor data communication. ICS 2008: 299-308 - 2007
- [j4]Koen De Bosschere, Wayne Luk, Xavier Martorell
High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. 1: 5-29 (2007) - [c18]John H. Kelm, Isaac Gelado, Mark J. Murphy, Nacho Navarro, Steven S. Lumetta, Wen-mei W. Hwu:
CIGAR: Application Partitioning for a CPU/Coprocessor Architecture. PACT 2007: 317-326 - [c17]Wen-mei W. Hwu, Shane Ryoo, Sain-Zee Ueng, John H. Kelm, Isaac Gelado, Sam S. Stone, Robert E. Kidd, Sara S. Baghsorkhi, Aqeel Mahesri, Stephanie C. Tsao, Nacho Navarro, Steven S. Lumetta, Matthew I. Frank, Sanjay J. Patel:
Implicitly Parallel Programming Models for Thousand-Core Microprocessors. DAC 2007: 754-759 - [e2]Taewhan Kim, Pascal Sainrat, Steven S. Lumetta, Nacho Navarro:
Proceedings of the 2007 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2007, Salzburg, Austria, September 30 - October 3, 2007. ACM 2007 [contents] - 2006
- [j3]Ronald D. Barnes, John W. Sias, Erik M. Nystrom, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu:
Beating In-Order Stalls with "Flea-Flicker" Two-Pass Pipelining. IEEE Trans. Computers 55(1): 18-33 (2006) - [c16]Yolanda Becerra, Jordi Garcia, Toni Cortes, Nacho Navarro:
Java Virtual Machine: the key for accurated memory prefetching. Software Engineering Research and Practice 2006: 933-939 - 2005
- [e1]Thomas M. Conte
High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings. Lecture Notes in Computer Science 3793, Springer 2005, ISBN 3-540-30317-0 [contents] - 2003
- [c15]Yolanda Becerra
Evaluating the importance of virtual memory for Java. ISPASS 2003: 101-110 - [c14]Ronald D. Barnes, Erik M. Nystrom, John W. Sias, Sanjay J. Patel, Nacho Navarro, Wen-mei W. Hwu:
Beating in-order stalls with "flea-flicker" two-pass pipelining. MICRO 2003: 387-398 - 2001
- [j2]José Oliver, Jordi Guitart
Strategies for the efficient exploitation of loop-level parallelism in Java. Concurr. Comput. Pract. Exp. 13(8-9): 663-680 (2001) - 2000
- [j1]Marc González, Eduard Ayguadé, Xavier Martorell, Jesús Labarta
NanosCompiler: supporting flexible multilevel parallelism exploitation in OpenMP. Concurr. Pract. Exp. 12(12): 1205-1218 (2000) - [c13]Marc González, Albert Serra, Xavier Martorell, José Oliver, Eduard Ayguadé, Jesús Labarta, Nacho Navarro:
Applying Interposition Techniques for Performance Analysis of OpenMP Parallel Applications. IPDPS 2000: 235-240 - [c12]José Oliver, Eduard Ayguadé, Nacho Navarro:
Towards an efficient exploitation of loop-level parallelism in Java. Java Grande 2000: 9-15 - [c11]Xavier Martorell, Julita Corbalán, Dimitrios S. Nikolopoulos, Nacho Navarro, Eleftherios D. Polychronopoulos, Theodore S. Papatheodorou, Jesús Labarta:
A Tool to Schedule Parallel Applications on Multiprocessors: The NANOS CPU MANAGER. JSSPP 2000: 87-112 - [c10]Marc González, José Oliver, Xavier Martorell, Eduard Ayguadé, Jesús Labarta
OpenMP Extensions for Thread Groups and Their Run-Time Support. LCPC 2000: 324-338 - [c9]Albert Serra, Nacho Navarro, Toni Cortes:
DITools: Application-level Support for Dynamic Extension and Flexible Composition. USENIX ATC, General Track 2000: 225-238
1990 – 1999
- 1999
- [c8]Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc González, Nacho Navarro:
Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. ICPP 1999: 172-180 - [c7]Xavier Martorell, Eduard Ayguadé, Nacho Navarro, Julita Corbalán, Marc González, Jesús Labarta:
Thread fork/join techniques for multi-level parallelism exploitation in NUMA multiprocessors. International Conference on Supercomputing 1999: 294-301 - 1998
- [c6]Eleftherios D. Polychronopoulos, Xavier Martorell, Dimitrios S. Nikolopoulos, Jesús Labarta, Theodore S. Papatheodorou, Nacho Navarro:
Kernel-level Scheduling for the Nano-threads Programming Model. International Conference on Supercomputing 1998: 337-344 - [c5]Ernest Artiaga, Xavier Martorell, Yolanda Becerra, Nacho Navarro:
Experiences on implementing PARMACS macros to run the SPLASH-2 suite on multiprocessors. PDP 1998: 64-69 - 1997
- [c4]Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé:
Analysis of Several Scheduling Algorithms under the Nano-Thread Programming Model. IPPS 1997: 281-287 - [c3]Eduard Ayguadé, Xavier Martorell, Jesús Labarta
Exploiting Parallelism Through Directives on the Nano-Threads Programming Model. LCPC 1997: 307-321 - 1996
- [c2]Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé:
A Library Implementation of the Nano-Threads Programming Model. Euro-Par, Vol. II 1996: 644-649 - 1995
- [c1]Marisa Gil, Xavier Martorell, Nacho Navarro:
The eXc Model: Scheduler-Activations on Mach 3.0. Parallel and Distributed Computing and Systems 1995: 5-10
Coauthor Index
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