default search action
Christopher Batten
Person information
- affiliation: Cornell University, Ithaca, NY, USA
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j12]Courtney Golden
, Dan Ilan
Supporting a Virtual Vector Instruction Set on a Commercial Compute-in-SRAM Accelerator. IEEE Comput. Archit. Lett. 23(1): 29-32 (2024) - [c43]Dai Cheol Jung, Max Ruttenberg, Paul Gao, Scott Davidson, Daniel Petrisko, Kangli Li, Aditya K. Kamath, Lin Cheng, Shaolin Xie, Peitian Pan, Zhongyuan Zhao, Zichao Yue, Bandhav Veluri, Sripathi Muralitharan, Adrian Sampson, Andrew Lumsdaine, Zhiru Zhang, Christopher Batten, Mark Oskin, Dustin Richmond, Michael Bedford Taylor:
Scalable, Programmable and Dense: The HammerBlade Open-Source RISC-V Manycore. ISCA 2024: 770-784 - [c42]Christopher Batten
PyHDL-Eval: An LLM Evaluation Framework for Hardware Design Using Python-Embedded DSLs. MLCAD 2024: 10:1-10:17 - [i3]Courtney Golden, Dan Ilan, Nicholas Cebry, Christopher Batten:
Accelerating Seed Location Filtering in DNA Read Mapping Using a Commercial Compute-in-SRAM Architecture. CoRR abs/2401.11685 (2024) - [i2]Nathaniel Ross Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany:
Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks. CoRR abs/2408.11053 (2024) - 2023
- [j11]Christopher Batten
Special Issue on Top Picks From the 2022 Computer Architecture Conferences. IEEE Micro 43(4): 6-10 (2023) - [c41]Lin Cheng, Max Ruttenberg, Dai Cheol Jung, Dustin Richmond
Beyond Static Parallel Loops: Supporting Dynamic Task Parallelism on Manycore Architectures with Software-Managed Scratchpad Memories. ASPLOS (3) 2023: 46-58 - [c40]Ting-Jung Chang, Ang Li
CIFER: A 12nm, 16mm2, 22-Core SoC with a 1541 LUT6/mm2 1.92 MOPS/LUT, Fully Synthesizable, CacheCoherent, Embedded FPGA. CICC 2023: 1-2 - [c39]Khalid Al-Hawaj, Tuan Ta, Nick Cebry, Shady Agwa, Olalekan Afuye, Eric Hall, Courtney Golden, Alyssa B. Apsel, Christopher Batten
EVE: Ephemeral Vector Engines. HPCA 2023: 691-704 - [c38]Peitian Pan, Shunning Jiang, Yanghui Ou, Christopher Batten:
Symbolic Elaboration: Checking Generator Properties in Dynamic Hardware Description Languages. MEMOCODE 2023: 126-136 - [c37]Peitian Pan, Christopher Batten:
Formal Verification of the Stall Invariant Property for Latency-Insensitive RTL Modules. MEMOCODE 2023: 148-158 - [c36]Max Doblas
GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment. MICRO 2023: 1466-1480 - [i1]Matthew Guthaus, Christopher Batten, Erik Brunvand, Pierre-Emmanuel Gaillardon, David M. Harris, Rajit Manohar, Pinaki Mazumder, Larry T. Pileggi, James E. Stine:
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. CoRR abs/2311.02055 (2023) - 2022
- [j10]Lin Cheng
A Tensor Processing Framework for CPU-Manycore Heterogeneous Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(6): 1620-1635 (2022) - [c35]Tuan Ta, Khalid Al-Hawaj, Nick Cebry, Yanghui Ou, Eric Hall, Courtney Golden, Christopher Batten
big.VLITTLE: On-Demand Data-Parallel Acceleration for Mobile Systems on Chip. MICRO 2022: 181-198 - 2021
- [j9]Shunning Jiang
PyH2: Using PyMTL3 to Create Productive and Open-Source Hardware Testing Methodologies. IEEE Des. Test 38(2): 53-61 (2021) - [c34]Shunning Jiang, Yanghui Ou, Peitian Pan, Christopher Batten:
UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling. DAC 2021: 883-888 - [c33]Olalekan Afuye, Shady Agwa, Christopher Batten, Alyssa B. Apsel:
Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM. ESSDERC 2021: 283-286 - [c32]Christopher Torng, Peitian Pan, Yanghui Ou, Cheng Tan
Ultra-Elastic CGRAs for Irregular Loop Specialization. HPCA 2021: 412-425 - [c31]Helena Caminal
CAPE: A Content-Addressable Processing Engine. HPCA 2021: 557-569 - 2020
- [j8]Shunning Jiang, Peitian Pan, Yanghui Ou, Christopher Batten:
PyMTL3: A Python Framework for Open-Source Hardware Modeling, Generation, Simulation, and Verification. IEEE Micro 40(4): 58-66 (2020) - [c30]Lin Cheng, Berkin Ilbeyi, Carl Friedrich Bolz-Tereick, Christopher Batten:
Type freezing: exploiting attribute type monomorphism in tracing JIT compilers. CGO 2020: 16-29 - [c29]Moyang Wang, Tuan Ta, Lin Cheng, Christopher Batten:
Efficiently Supporting Dynamic Task Parallelism on Heterogeneous Cache-Coherent Systems. ISCA 2020: 173-186 - [c28]Khalid Al-Hawaj, Olalekan Afuye, Shady Agwa, Alyssa B. Apsel, Christopher Batten:
Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator using In-Situ Processing-In-SRAM. ISCAS 2020: 1-5 - [c27]Yanghui Ou, Shady Agwa, Christopher Batten:
Implementing Low-Diameter On-Chip Networks for Manycore Processors Using a Tiled Physical Design Methodology. NOCS 2020: 1-8
2010 – 2019
- 2019
- [c26]Cheng Tan
PyOCN: A Unified Framework for Modeling, Testing, and Evaluating On-Chip Networks. ICCD 2019: 437-445 - [c25]Austin Rovinski, Chun Zhao
A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS. VLSI Circuits 2019: 30- - 2018
- [j7]Scott Davidson, Shaolin Xie, Christopher Torng, Khalid Al-Hawaj, Austin Rovinski, Tutu Ajayi, Luis Vega, Chun Zhao
The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips. IEEE Micro 38(2): 30-41 (2018) - [j6]Ivan Bukreyev, Christopher Torng, Waclaw Godycki, Christopher Batten, Alyssa B. Apsel:
Four Monolithically Integrated Switched-Capacitor DC-DC Converters With Dynamic Capacitance Sharing in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(6): 2035-2047 (2018) - [c24]Shunning Jiang, Berkin Ilbeyi, Christopher Batten:
Mamba: closing the performance gap in productive hardware development frameworks. DAC 2018: 60:1-60:6 - [c23]Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. MICRO 2018: 55-67 - 2017
- [c22]Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA 2017: 189-194 - [c21]Berkin Ilbeyi, Carl Friedrich Bolz-Tereick, Christopher Batten:
Cross-layer workload characterization of meta-tracing JIT VMs. IISWC 2017: 97-107 - [c20]Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten:
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. MICRO 2017: 759-773 - 2016
- [c19]Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang
Improving high-level synthesis with decoupled data structure optimization. DAC 2016: 137:1-137:6 - [c18]Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten:
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. Hot Chips Symposium 2016: 1 - [c17]Christopher Torng, Moyang Wang, Christopher Batten:
Asymmetry-Aware Work-Stealing Runtimes. ISCA 2016: 40-52 - [c16]Berkin Ilbeyi, Christopher Batten:
JIT-assisted fast-forward embedding and instrumentation to enable fast, accurate, and agile simulation. ISPASS 2016: 284-295 - 2015
- [c15]Derek Lockhart, Berkin Ilbeyi, Christopher Batten:
Pydgin: generating fast instruction set simulators from simple architecture descriptions with meta-tracing JIT compilers. ISPASS 2015: 256-267 - 2014
- [c14]Ji Yun Kim, Christopher Batten:
Accelerating Irregular Algorithms on GPGPUs Using Fine-Grain Hardware Worklists. MICRO 2014: 75-87 - [c13]Derek Lockhart, Gary Zibrat, Christopher Batten:
PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research. MICRO 2014: 280-292 - [c12]Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B. Apsel, Christopher Batten:
Enabling Realistic Fine-Grain Voltage Scaling with Reconfigurable Power Distribution Networks. MICRO 2014: 381-393 - [c11]Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang
Architectural Specialization for Inter-Iteration Loop Dependence Patterns. MICRO 2014: 583-595 - 2013
- [j5]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators. ACM Trans. Comput. Syst. 31(3): 6 (2013) - [c10]Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten:
Microarchitectural mechanisms to exploit value structure in SIMT architectures. ISCA 2013: 130-141 - 2012
- [j4]Christopher Batten
Designing Chip-Level Nanophotonic Interconnection Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(2): 137-153 (2012) - 2011
- [c9]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
The Maven vector-thread architecture. Hot Chips Symposium 2011: 1 - [c8]Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, Krste Asanovic:
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators. ISCA 2011: 129-140 - [c7]Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh
Analysis of application-aware on-chip routing under traffic uncertainty. NOCS 2011: 9-16 - 2010
- [b1]Christopher Batten:
Simplified vector-thread architectures for flexible and efficient data-parallel accelerators. Massachusetts Institute of Technology, Cambridge, MA, USA, 2010 - [c6]Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi, Christopher Batten
Re-architecting DRAM memory systems with monolithically integrated silicon photonics. ISCA 2010: 129-140
2000 – 2009
- 2009
- [j3]Christopher Batten
Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics. IEEE Micro 29(4): 8-21 (2009) - [c5]Scott Beamer, Krste Asanovic, Christopher Batten, Ajay Joshi, Vladimir Stojanovic:
Designing multi-socket systems using silicon photonics. ICS 2009: 521-522 - [c4]Ajay Joshi, Christopher Batten
Silicon-photonic clos networks for global on-chip communication. NOCS 2009: 124-133 - 2008
- [j2]Ronny Krashinsky, Christopher Batten, Krste Asanovic:
Implementing the scale vector-thread processor. ACM Trans. Design Autom. Electr. Syst. 13(3): 41:1-41:24 (2008) - [c3]Christopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos A. Popovic
Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. Hot Interconnects 2008: 21-30 - 2004
- [j1]Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
The Vector-Thread Architecture. IEEE Micro 24(6): 84-90 (2004) - [c2]Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
The Vector-Thread Architecture. ISCA 2004: 52-63 - [c1]Christopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic:
Cache Refill/Access Decoupling for Vector Machines. MICRO 2004: 331-342
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-23 20:34 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: