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Shreesha Srinath
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2020 – today
- 2021
- [c12]Nursultan Kabylkas
, Tommy Thorn, Shreesha Srinath, Polychronis Xekalakis, Jose Renau
Effective Processor Verification with Logic Fuzzer Enhanced Co-simulation. MICRO 2021: 667-678
2010 – 2019
- 2018
- [c11]Brucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons
A modular digital VLSI flow for high-productivity SoC design. DAC 2018: 72:1-72:6 - [c10]Tao Chen, Shreesha Srinath, Christopher Batten, G. Edward Suh
An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware. MICRO 2018: 55-67 - 2017
- [c9]Steve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang:
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis. FPGA 2017: 189-194 - [c8]Ji Kim, Shunning Jiang, Christopher Torng, Moyang Wang, Shreesha Srinath, Berkin Ilbeyi, Khalid Al-Hawaj, Christopher Batten:
Using intra-core loop-task accelerators to improve the productivity and performance of task-based parallel programs. MICRO 2017: 759-773 - 2016
- [c7]Ritchie Zhao, Gai Liu, Shreesha Srinath, Christopher Batten, Zhiru Zhang
Improving high-level synthesis with decoupled data structure optimization. DAC 2016: 137:1-137:6 - [c6]Christopher Torng, Moyang Wang, Bharath Sudheendra, Nagaraj Murali, Suren Jayasuriya, Shreesha Srinath, Taylor Pritchard, Robin Ying, Christopher Batten:
Experiences using a novel Python-based hardware modeling framework for computer architecture test chips. Hot Chips Symposium 2016: 1 - 2014
- [c5]Shreesha Srinath, Berkin Ilbeyi, Mingxing Tan, Gai Liu, Zhiru Zhang
Architectural Specialization for Inter-Iteration Loop Dependence Patterns. MICRO 2014: 583-595 - 2013
- [j1]Sayandeep Sen, Tan Zhang, Syed Gilani, Shreesha Srinath, Suman Banerjee, Sateesh Addepalli:
Design and Implementation of an "Approximate" Communication System for Wireless Media Applications. IEEE/ACM Trans. Netw. 21(4): 1035-1048 (2013) - [c4]Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten:
Microarchitectural mechanisms to exploit value structure in SIMT architectures. ISCA 2013: 130-141 - 2010
- [c3]Shreesha Srinath, Katherine Compton:
Automatic generation of high-performance multipliers for FPGAs with asymmetric multiplier blocks. FPGA 2010: 51-58 - [c2]Sayandeep Sen, Syed Gilani, Shreesha Srinath, Stephen Schmitt, Suman Banerjee:
Design and implementation of an "approximate" communication system for wireless media applications. SIGCOMM 2010: 15-26
2000 – 2009
- 2008
- [c1]Ashwin Kothari
Rough Neuron Based Neural Classifier. ICETET 2008: 624-628
Coauthor Index
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