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James Tuck 0001
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- affiliation: North Carolina State University, Raleigh, NC, USA
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2020 – today
- 2023
- [j16]Kevin Volkel
, Kevin N. Lin, Paul W. Hook, Winston Timp
FrameD: framework for DNA-based data storage design, verification, and validation. Bioinform. 39(10) (2023) - [c37]Hussein Elnawawy, James Tuck
PreFlush: Lightweight Hardware Prediction Mechanism for Cache Line Flush and Writeback. PACT 2023: 74-85 - [c36]Xijing Han, James Tuck
Thoth: Bridging the Gap Between Persistently Secure Memories and Memory Interfaces of Emerging NVMs. HPCA 2023: 94-107 - [c35]Ramil Agliamzanov, James M. Tuck:
Reducing Read Amplification and Re-synthesis in DNA-based Archival Storage. ICRC 2023: 1-5 - 2022
- [j15]Kevin Volkel
DINOS: Data INspired Oligo Synthesis for DNA Data Storage. ACM J. Emerg. Technol. Comput. Syst. 18(3): 53:1-53:35 (2022) - [c34]Xijing Han, James Tuck
Horus: Persistent Security for Extended Persistence-Domain Memory Systems. MICRO 2022: 1255-1269 - 2021
- [c33]Mohammad A. Alshboul
BBB: Simplifying Persistent Programming using Battery-Backed Buffers. HPCA 2021: 111-124 - [c32]Xijing Han, James Tuck
Dolos: Improving the Performance of Persistent Applications in ADR-Supported Secure Memory. MICRO 2021: 1241-1253 - 2020
- [j14]Ahmed Samara
The Case for Domain-Specialized Branch Predictors for Graph-Processing. IEEE Comput. Archit. Lett. 19(2): 101-104 (2020) - [c31]Mohammad A. Alshboul
WET: Write Efficient Loop Tiling for Non-Volatile Main Memory. DAC 2020: 1-6 - [i1]Tiancong Wang, James Tuck:
Persistent Data Retention Models. CoRR abs/2009.14705 (2020)
2010 – 2019
- 2019
- [j13]Mohammad A. Alshboul
Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory. ACM Trans. Archit. Code Optim. 16(2): 18:1-18:27 (2019) - 2018
- [c30]Mohammad A. Alshboul
Lazy Persistency: A High-Performing and Write-Efficient Software Persistency Technique. ISCA 2018: 439-451 - [c29]Tiancong Wang, Sakthikumaran Sambasivam, James Tuck:
Hardware Supported Permission Checks on Persistent Objects for Performance and Programmability. ISCA 2018: 466-478 - [e2]Xipeng Shen, James Tuck, Ricardo Bianchini, Vivek Sarkar:
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2018, Williamsburg, VA, USA, March 24-28, 2018. ACM 2018, ISBN 978-1-4503-4911-6 [contents] - 2017
- [j12]George Patsilaras, James Tuck:
ReDirect: Reconfigurable Directories for Multicore Architectures. ACM Trans. Archit. Code Optim. 14(4): 50:1-50:23 (2017) - [c28]Hussein Elnawawy, Mohammad A. Alshboul
Efficient Checkpointing of Loop-Based Codes for Non-volatile Main Memory. PACT 2017: 318-329 - [c27]Bagus Wibowo, Abhinav Agrawal, James Tuck:
Characterizing the impact of soft errors across microarchitectural structures and implications for predictability. IISWC 2017: 250-260 - [c26]Seunghee Shin, James Tuck, Yan Solihin:
Hiding the Long Latency of Persist Barriers Using Speculative Execution. ISCA 2017: 175-186 - [c25]Seunghee Shin, Satish Kumar Tirukkovalluri, James Tuck, Yan Solihin:
Proteus: a flexible and fast software supported hardware logging approach for NVM. MICRO 2017: 178-190 - [c24]Joonmoo Huh, James Tuck:
Improving the effectiveness of searching for isomorphic chains in superword level parallelism. MICRO 2017: 718-729 - [c23]Tiancong Wang, Sakthikumaran Sambasivam, Yan Solihin, James Tuck:
Hardware supported persistent object address translation. MICRO 2017: 800-812 - [c22]Abhinav Agrawal, Gabriel H. Loh, James Tuck:
Leveraging near data processing for high-performance checkpoint/restart. SC 2017: 60 - 2016
- [j11]Reed Milewicz, Rajeshwar Vanka, James Tuck
Lightweight runtime checking of C programs with RTC. Comput. Lang. Syst. Struct. 45: 191-203 (2016) - [j10]Bagus Wibowo, Abhinav Agrawal, Thomas Stanton, James Tuck:
An Accurate Cross-Layer Approach for Online Architectural Vulnerability Estimation. ACM Trans. Archit. Code Optim. 13(3): 30:1-30:27 (2016) - [e1]Xipeng Shen
Languages and Compilers for Parallel Computing - 28th International Workshop, LCPC 2015, Raleigh, NC, USA, September 9-11, 2015, Revised Selected Papers. Lecture Notes in Computer Science 9519, Springer 2016, ISBN 978-3-319-29777-4 [contents] - 2015
- [j9]Rami Sheikh, James Tuck, Eric Rotenberg:
Control-Flow Decoupling: An Approach for Timely, Non-Speculative Branching. IEEE Trans. Computers 64(8): 2182-2203 (2015) - [c21]Paul D. Franzon
Computing in 3D. 3DIC 2015: TS6.1.1-TS6.1.2 - [c20]Paul D. Franzon
Computing in 3D. CICC 2015: 1-6 - [c19]Abhinav Agrawal, Bagus Wibowo, James Tuck:
Source Mark: A Source-Level Approach for Identifying Architecture and Optimization Agnostic Regions for Performance Analysis. IISWC 2015: 160-171 - [c18]Reed Milewicz, Rajeshwar Vanka, James Tuck, Daniel J. Quinlan, Peter Pirkelbauer:
Runtime checking C programs. SAC 2015: 2107-2114 - 2014
- [c17]Paul D. Franzon
3D-enabled customizable embedded computer (3DECC). 3DIC 2014: 1-3 - 2013
- [j8]Sanghoon Lee, James Tuck:
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor. ACM Trans. Archit. Code Optim. 10(4): 30:1-30:26 (2013) - 2012
- [j7]George Patsilaras, Niket K. Choudhary, James Tuck:
Efficiently exploiting memory level parallelism on asymmetric coupled cores in the dark silicon era. ACM Trans. Archit. Code Optim. 8(4): 28:1-28:21 (2012) - [c16]Rajeshwar Vanka, James Tuck:
Efficient and accurate data dependence profiling using software signatures. CGO 2012: 186-195 - [c15]Liang Han, Xiaowei Jiang, Wei Liu, Youfeng Wu, James Tuck:
HiRe: using hint & release to improve synchronization of speculative threads. ICS 2012: 143-152 - [c14]Rami Sheikh, James Tuck, Eric Rotenberg:
Control-Flow Decoupling. MICRO 2012: 329-340 - 2011
- [c13]Sanghoon Lee, James Tuck
Automatic parallelization of fine-grained meta-functions on a chip multiprocessor. CGO 2011: 130-140 - [c12]Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck:
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor. HPCA 2011: 99-110 - 2010
- [c11]Liang Han, Wei Liu, James Tuck:
Speculative parallelization of partial reduction variables. CGO 2010: 141-150 - [c10]Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solihin:
MMT: Exploiting fine-grained parallelism in dynamic memory management. IPDPS 2010: 1-12
2000 – 2009
- 2009
- [j6]Josep Torrellas, Luis Ceze, James Tuck
The Bulk Multicore architecture for improved programmability. Commun. ACM 52(12): 58-65 (2009) - [j5]James Tuck, Wonsun Ahn, Josep Torrellas, Luis Ceze:
SoftSig: Software-Exposed Hardware Signatures for Code Analysis and Optimization. IEEE Micro 29(1): 84-95 (2009) - [c9]Devesh Tiwari, Sanghoon Lee, James Tuck, Yan Solihin:
Memory management thread for heap allocation intensive sequential applications. MEDEA@PACT 2009: 35-42 - 2008
- [c8]James Tuck, Wonsun Ahn, Luis Ceze, Josep Torrellas:
SoftSig: software-exposed hardware signatures for code analysis and optimization. ASPLOS 2008: 145-156 - 2007
- [b1]James Tuck:
Efficient Support for Speculative Tasking. University of Illinois Urbana-Champaign, USA, 2007 - [c7]James Tuck, Wei Liu, Josep Torrellas:
CAP: Criticality analysis for power-efficient speculative multithreading. ICCD 2007: 409-416 - [c6]Luis Ceze, James Tuck, Pablo Montesinos, Josep Torrellas:
BulkSC: bulk enforcement of sequential consistency. ISCA 2007: 278-289 - 2006
- [j4]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Energy-Efficient Thread-Level Speculation. IEEE Micro 26(1): 80-91 (2006) - [j3]Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau:
CAVA: Using checkpoint-assisted value prediction to hide L2 misses. ACM Trans. Archit. Code Optim. 3(2): 182-208 (2006) - [c5]Luis Ceze, James Tuck, Josep Torrellas, Calin Cascaval
Bulk Disambiguation of Speculative Threads in Multiprocessors. ISCA 2006: 227-238 - [c4]James Tuck, Luis Ceze, Josep Torrellas:
Scalable Cache Miss Handling for High Memory-Level Parallelism. MICRO 2006: 409-422 - [c3]Wei Liu, James Tuck, Luis Ceze, Wonsun Ahn, Karin Strauss, Jose Renau, Josep Torrellas:
POSH: a TLS compiler that exploits program structure. PPoPP 2006: 158-167 - 2005
- [c2]Jose Renau, James Tuck, Wei Liu, Luis Ceze, Karin Strauss, Josep Torrellas:
Tasking with out-of-order spawn in TLS chip multiprocessors: microarchitecture and compilation. ICS 2005: 179-188 - [c1]Jose Renau, Karin Strauss, Luis Ceze, Wei Liu, Smruti R. Sarangi, James Tuck, Josep Torrellas:
Thread-Level Speculation on a CMP can be energy efficient. ICS 2005: 219-228 - 2004
- [j2]Luis Ceze, Karin Strauss, James Tuck, Jose Renau, Josep Torrellas:
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction. IEEE Comput. Archit. Lett. 3 (2004) - 2001
- [j1]Jeff Gray
Handling crosscutting constraints in domain-specific modeling. Commun. ACM 44(10): 87-93 (2001)
Coauthor Index
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