Nothing Special   »   [go: up one dir, main page]

WO2020061886A1 - 一种像素电路和显示面板 - Google Patents

一种像素电路和显示面板 Download PDF

Info

Publication number
WO2020061886A1
WO2020061886A1 PCT/CN2018/107890 CN2018107890W WO2020061886A1 WO 2020061886 A1 WO2020061886 A1 WO 2020061886A1 CN 2018107890 W CN2018107890 W CN 2018107890W WO 2020061886 A1 WO2020061886 A1 WO 2020061886A1
Authority
WO
WIPO (PCT)
Prior art keywords
transistor
electrode
signal
pixel circuit
driving
Prior art date
Application number
PCT/CN2018/107890
Other languages
English (en)
French (fr)
Inventor
郑武
Original Assignee
深圳市柔宇科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to CN201880094142.5A priority Critical patent/CN112639949A/zh
Priority to PCT/CN2018/107890 priority patent/WO2020061886A1/zh
Publication of WO2020061886A1 publication Critical patent/WO2020061886A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]

Definitions

  • the present invention relates to the field of display, and more particularly, to a pixel circuit and a display panel.
  • AMOLED display devices With the development of the times and technology, large-sized and high-resolution AMOLED display devices have gradually developed. Large-sized AMOLED display devices also require larger-sized panels and a larger number of pixels. The greater the resistance, the power supply voltage will inevitably cause a voltage drop (IR Drop), and the voltage drop of each pixel circuit is different, which results in different power supply voltages for each pixel circuit. Therefore, under the same data signal voltage input, different pixel circuits will have different brightness outputs, which will lead to the entire The display brightness of the panel is uneven, and the picture is different, the IR of the pixel Drop will also be different, so that the entire display screen appears brighter near the Driver IC (driving chip), darker away from the Driver IC, and uneven brightness.
  • Driver IC driving chip
  • the technical problem to be solved by the present invention is to provide a pixel circuit and a display panel in response to the defects of the above-mentioned influence of the power supply voltage on the brightness in the prior art.
  • a pixel circuit including:
  • a data signal input unit configured to input a data signal according to the scanning signal of the current stage
  • a drive control unit configured to control the drive unit to be turned on according to a light emission control signal; or to control the drive unit to be turned on according to a scan signal and a light emission control signal of a previous stage; a data signal input terminal of the drive control unit and A capacitor is disposed between the signal output terminals of the drive control unit;
  • the switch circuit is configured to be turned on according to the light-emitting control signal when the driving unit is turned on, and transmit a driving signal output by the driving unit to the light-emitting unit to drive the light-emitting unit to emit light.
  • the data signal input unit includes: a first transistor
  • a first electrode of the first transistor is connected to a current group scan signal, a second electrode of the first transistor is connected to a data signal, a third electrode of the first transistor is connected to a data signal input terminal of the drive control unit. connection.
  • the drive control unit includes: a second transistor and a capacitor;
  • a first terminal of the capacitor and a second electrode of the second transistor are connected to a third electrode of the first transistor together, and a second terminal of the capacitor is connected to a control terminal of the driving unit;
  • the second A first electrode of the transistor is connected to a light emission control signal, and a third electrode of the second transistor is connected to a reference signal;
  • a first terminal of the capacitor is a data signal input terminal of the drive control unit, and a second terminal of the capacitor is a signal output terminal of the drive control unit.
  • the driving unit includes: a third transistor and a fifth transistor;
  • a third electrode of the third transistor is connected to a second terminal of the capacitor, a second electrode of the third transistor is connected to a third electrode of the fifth transistor, and a first electrode of the third transistor is connected to the Scanning signal of current stage;
  • a second electrode of the fifth transistor is connected to a power signal, a first electrode of the fifth transistor is connected to a second terminal of the capacitor, and a third electrode of the fifth transistor is connected to the switching circuit;
  • the first electrode of the fifth transistor is a control terminal of the driving unit.
  • the switching circuit includes: a fourth transistor
  • a second electrode of the fourth transistor is connected to a third electrode of the fifth transistor, a first electrode of the fourth transistor is connected to the light emission control signal, and a third electrode of the fourth transistor is connected to the light emitting unit. Positive electrode.
  • the driving control unit further includes: a sixth transistor;
  • a third electrode of the sixth transistor is connected to a discharge signal, a second electrode of the sixth transistor is connected to a second terminal of the capacitor, and a first electrode of the sixth transistor is connected to the scan signal of the previous stage.
  • the driving unit further includes: a seventh transistor connected between the fourth transistor and the light emitting unit;
  • the first electrode of the seventh transistor is connected to the light emission control signal
  • the second electrode of the seventh transistor is connected to the third electrode of the fourth transistor
  • the third electrode of the seventh transistor is connected to the The positive terminal of the light-emitting unit.
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all PMOS transistors;
  • the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are all NMOS transistors.
  • the light-emission control signal is at a low level and the current stage is scanned.
  • the fourth transistor and the fifth transistor are turned on, and the third transistor is turned off.
  • the light emission control signal is at a high level and the current level is scanned.
  • the fourth transistor and the fifth transistor are turned on, and the third transistor is turned off.
  • the present invention also provides a display panel including the pixel circuit described above.
  • the present invention also provides a pixel circuit including a first node, a second node, a capacitor connected between the first node and the second node, and a driving transistor, and a gate of the driving transistor is connected to the second node.
  • the source of the driving transistor is connected to the input voltage VDD, and the drain is used to output current to the light-emitting unit.
  • V1 the voltage of the first node during the first period
  • V3 the first The voltage of the node in the second period
  • V1 is not equal to V3 and is independent of the input voltage.
  • the voltage of the second node during the first period is V2, and the voltage during the second period is V2 + V3-V1.
  • the voltage of the second node during the first period is VDD-Vth, where Vth is a threshold voltage of the driving transistor.
  • the driving cycle further includes an initialization period earlier than the first period, and the voltage of the second node is initialized during the initialization period.
  • a transistor T3 is connected between the gate and the drain of the driving transistor, and the transistor T3 is turned on in the first period and turned off in the second period.
  • the current flowing through the light-emitting unit can be affected only by the data signal, and is no longer affected by the power supply voltage, thereby eliminating the influence of the change in the power supply voltage on the current flowing through the light-emitting unit, eliminating the power supply.
  • the influence of voltage on brightness ensures the brightness consistency of the display screen.
  • FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit provided by the present invention.
  • 2 to 4 are timing diagrams of various signals of the pixel circuit according to the first embodiment of the present invention.
  • FIG. 5 is a circuit diagram of a second embodiment of a pixel circuit provided by the present invention.
  • FIG. 6 to FIG. 7 are timing diagrams of respective signals of the second embodiment of the pixel circuit provided by the present invention.
  • FIG. 1 is a circuit diagram of a first embodiment of a pixel circuit provided by the present invention.
  • the pixel circuit can be applied to a display panel.
  • the display panel includes, but is not limited to, an OLED display panel, an AMLOED display panel, an LCD panel, an LED panel, and the like.
  • the pixel circuit is disposed in a light-emitting area of the display panel.
  • the pixel circuit includes a data signal input unit 10, a driving unit 30, a driving control unit 20, and a switching circuit 40.
  • the data signal input unit 10 is configured to input a data signal according to the scanning signal (Gn) of the current stage.
  • the driving unit 30 is configured to output a driving signal when being turned on.
  • the driving control unit 20 is configured to control the driving unit 30 to be turned on according to the light emission control signal (EM); or to control the driving unit 30 to be turned on according to the scanning signal (Gn-1) and the light emitting control signal of the previous stage;
  • a capacitor C is disposed between the data signal input terminal and the signal output terminal of the drive control unit.
  • the drive control unit 20 controls the drive unit 30 to be turned on by the light emission control signal
  • the drive unit 30 is turned on during the valid period of the light emission control signal; when the drive control unit 20 controls the drive unit 30 by the light emission control signal and the previous stage scanning signal When it is turned on, the driving unit 30 is turned on during the active level period of the light emission control signal and the scan signal of the previous stage is in the invalid level period.
  • the data signal input unit 10 includes: a first transistor T1, wherein a first electrode of the first transistor T1 is connected to a current-stage scan signal (Gn), and a second electrode of the first transistor T1 is connected to data (Vdata ), The third electrode of the first transistor T1 is connected to a data signal input terminal of the driving control unit 20.
  • the first transistor T1 is a PMOS transistor.
  • the first electrode of the first transistor T1 is the gate of the PMOS tube
  • the second electrode of the first transistor T1 is the source of the PMOS tube
  • the third electrode of the first transistor T1 is the drain of the PMOS tube.
  • the drive control unit 20 includes a second transistor T2 and a sixth transistor T6.
  • the first terminal of the capacitor C and the second electrode of the second transistor T2 are connected to the third electrode of the first transistor T1, the second terminal of the capacitor C is connected to the control terminal of the driving unit 30, and the first terminal of the second transistor T2
  • the electrode is connected to the light emission control signal (EM)
  • the third electrode of the second transistor T2 is connected to the reference (Vref)
  • the first electrode of the sixth transistor T6 is connected to the scan signal (Gn-1) of the previous stage
  • the sixth transistor T6 is
  • the two electrodes are connected to the second terminal of the capacitor C, and the third electrode of the sixth transistor T6 is connected to a discharge signal (Vinit).
  • the first terminal of the capacitor C is a data signal input terminal of the driving control unit 20, and the second terminal of the capacitor C is a signal output terminal of the driving control unit 20.
  • the discharge signal (Vinit) is a low-level signal.
  • the second transistor T2 and the sixth transistor T6 are both PMOS transistors, wherein a first electrode of the second transistor T2 is a gate of the PMOS tube, and a second electrode of the second transistor T2 is a source of the PMOS tube,
  • the third electrode of the second transistor T2 is the drain of the PMOS tube;
  • the first electrode of the sixth transistor T6 is the gate of the PMOS tube;
  • the second electrode of the sixth transistor T6 is the source of the PMOS tube;
  • the third electrode is the drain of the PMOS tube.
  • the driving unit 30 includes a third transistor T3 and a fifth transistor T5.
  • the third electrode of the third transistor T3 is connected to the second terminal of the capacitor C, the second electrode of the third transistor T3 is connected to the third electrode of the fifth transistor T5, and the first electrode of the third transistor T3 Connected to the current stage scanning signal (Gn); the second electrode of the fifth transistor T5 is connected to the power signal (ELVDD); the first electrode of the fifth transistor T5 is connected to the second terminal of the capacitor C;
  • the third electrode of the fifth transistor T5 is connected to the switching circuit 40; wherein the first electrode of the fifth transistor T5 is a control terminal of the driving unit 30.
  • the fifth transistor T5 is a driving transistor of the pixel circuit of the present invention.
  • the third transistor T3 is turned on, and when the emission control signal (EM) is at a low level, the fourth transistor T4 is turned on.
  • the switching circuit 40 includes a fourth transistor T4.
  • the second electrode of the fourth transistor T4 is connected to the third electrode of the fifth transistor T5, the first electrode of the fourth transistor T4 is connected to the light emission control signal (EM), and the third electrode of the fourth transistor T4 is connected to the positive electrode of the light emitting unit (OLED). .
  • a transistor may be added between the fourth transistor T4 and the light-emitting unit, that is, a seventh transistor T7 may be added between the fourth transistor T4 and the light-emitting unit (not shown in the figure).
  • (Out) wherein the first electrode of the seventh transistor T7 is connected to the light emission control signal, the second electrode of the seventh transistor T7 is connected to the third electrode of the fourth transistor T4, and the first electrode of the seventh transistor T7
  • the three electrodes are connected to a positive electrode of the light emitting unit.
  • the type of the seventh transistor T7 is the same as that of the fifth transistor T5.
  • the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all PMOS transistors, wherein the first electrode of the third transistor T3 is the gate of the PMOS transistor and the third transistor T3
  • the second electrode is the source of the PMOS tube, the third electrode of the third transistor T3 is the drain of the PMOS tube; the first electrode of the fourth transistor T4 is the gate of the PMOS tube, and the second electrode of the fourth transistor T4 is The source of the PMOS transistor, the third electrode of the fourth transistor T4 is the drain of the PMOS transistor; the first electrode of the fifth transistor T5 is the gate of the PMOS transistor, and the second electrode of the fifth transistor T5 is the source of the PMOS transistor.
  • the third electrode of the fifth transistor T5 is the drain of the PMOS transistor.
  • the scanning signal (Gn) of the current stage the scanning signal (Gn-1) of the previous stage, the emission control signal (EM), the data signal (Vdata), and the reference signal (Vref) are all provided by the Driver.
  • the data signal (Vdata) is the data voltage output by the Driver IC for image display
  • the reference signal (Vref) is the reference voltage output by the Driver IC.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 in this embodiment may be a PMOS transistor or an NMOS transistor.
  • the types of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are the same, that is, when a PMOS tube is used, the A transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6 are all PMOS transistors; when an NMOS transistor is used, the first transistor T1, the second transistor T2, the first transistor The three transistors T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all NMOS transistors.
  • the effective level of the scanning signal (Gn) of the current stage is high level
  • the effective level of the emission control signal (EM) is high level
  • the scanning signal (Gn-1 of the previous stage) ) The inactive level is low.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all PMOS transistors.
  • the scanning signal (Gn) of the current stage is high level, the first transistor T1 is turned off, and the data signal unit will The data signal is input, so the data signal cannot be input.
  • the effective level of the scanning signal (Gn) of the current stage is a low level
  • the effective level of the emission control signal (EM) is a low level
  • the scanning signal (Gn-1 of the previous stage) The inactive level is high.
  • the scanning signal (Gn) of the current stage is at a high level, and the first transistor T1 is turned off; the light emission control signal (EM) is at a high level, and the second transistor T2, the third transistor T3, and the fourth transistor T4 is in the off state; the scan signal (Gn-1) of the previous stage is low, so the sixth transistor T6 is turned on and the fifth transistor T5 is also turned on.
  • the second terminal of the capacitor C point N2
  • the voltage is Vinit. Because Vinit is low (negative voltage) and the first transistor T1 is in the off state, the data signal (Vdata) cannot be input, so the capacitor C is in the discharging state.
  • the scanning signal (Gn-1) of the previous stage is high, the scanning signal (Gn) of the current stage is low, and the light emission control signal (EM) is high Level.
  • the first transistor T1, the third transistor T3 are turned on, the second transistor T2, the fourth transistor T4, and the sixth transistor are all turned off. Since the voltage of N2 in the previous frame is Vinit, the fifth transistor T5 is also turned on at this time. through.
  • the data signal can be input to charge the capacitor C.
  • the voltage at the first terminal (point N1) of the capacitor C is Vdata, and the voltage at the second terminal (point N2) of the capacitor C is ELVDD-Vth, where Vth is the fifth transistor T5. Threshold voltage.
  • the scanning signal (Gn-1) of the previous stage is high
  • the scanning signal (Gn) of the current stage is high
  • the light emission control signal (EM) Is low.
  • the first transistor T1, the third transistor T3, and the sixth transistor T6 are all turned off, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned on.
  • the voltage at point N1 is Vref.
  • the voltage change at point N1 is: Vref-Vdata; it can be obtained from the coupling principle of the capacitor.
  • the voltage at point N2 is: ELVDD-Vth + Vref-Vdata.
  • the current flowing through the light-emitting unit (OLED) can be obtained as:
  • u is a constant
  • Cox is a parasitic capacitance between a gate and a source and a drain of the fifth transistor T5
  • W / L is a width-to-length ratio of the fifth transistor T5.
  • the current flowing through the light-emitting unit is only affected by the data voltage and reference voltage input by the data signal, and has nothing to do with the power supply voltage (ELVDD).
  • the influence of the unit's current eliminates the influence of the power supply voltage on the brightness and ensures the consistency of the brightness of the display screen.
  • FIG. 5 is a circuit diagram of a second embodiment of a pixel circuit provided by the present invention.
  • the pixel circuit of this embodiment also includes a data signal input unit 10, a driving unit 30, and a driving control unit 20.
  • the data signal input unit 10 and the driving unit 30 are the same as those in the first embodiment, and the sixth transistor T6 is omitted from the driving control unit 20.
  • the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are all PMOS transistors.
  • the effective level of the scanning signal (Gn) of the current stage is a low level, and the effective level of the light emission control signal (EM) is a low level.
  • the scanning signal (Gn) of the current stage is at a low level and the light emission control signal (EM) is at a high level.
  • the first transistor T1 and the third transistor T3 are both turned on.
  • the second transistor T2 and the fourth transistor T4 are both turned off, and the fifth transistor T5 is turned on due to the light emission condition of the previous frame.
  • the voltage at the first terminal (point N1) of the capacitor C is Vdata
  • the voltage at the second terminal (point N2) of the capacitor C is: ELVDD-Vth.
  • the scanning signal (Gn) of the current stage is high level and the light emission control signal (EM) is low level.
  • the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are all turned on.
  • the first transistor T1 and the third transistor T3 are both turned off.
  • the voltage at the point N1 is Vref. Therefore, the voltage variation at the point N1 is: Vref-Vdata; it can be obtained according to the capacitive coupling principle.
  • the voltage at the point N2 is: ELVDD-Vth + Vref-Vdata.
  • the current flowing through the light-emitting unit (OLED) can be obtained as: .
  • u is a constant
  • Cox is a parasitic capacitance between a gate and a source and a drain of the fifth transistor T5
  • W / L is a width-to-length ratio of the fifth transistor T5.
  • the current flowing through the light-emitting unit is only affected by the data voltage and reference voltage input by the data signal, and has nothing to do with the power supply voltage (ELVDD).
  • the influence of the unit current eliminates the influence of the power supply voltage on the brightness and ensures the consistency of the brightness of the display screen.
  • the resolution of the display panel can be further improved by removing the sixth transistor T6.
  • the present invention eliminates the effect of ELVDD on the magnitude of the current flowing through the driving transistor (the fifth transistor T5) in the pixel circuit, thereby eliminating the effect of the ELVDD voltage on the brightness, thereby ensuring the brightness consistency of the entire display screen.
  • the present invention also provides a display panel.
  • the display panel includes a pixel circuit, and the pixel circuit is the pixel circuit described above.
  • the display panel includes, but is not limited to, an OLED display panel, an AMLOED display panel, and the like.
  • the present invention also provides a pixel circuit including a first node N1, a second node N2, a capacitor C connected between the first node N1 and the second node N2, and a driving transistor T5 (that is, the aforementioned first Five transistors T5).
  • the gate of the driving transistor T5 is connected to the second node N2.
  • the source of the driving transistor T5 is connected to the input voltage VDD (ie, the aforementioned ELVDD).
  • the drain is used to output current to the light-emitting unit.
  • the voltage of the first node N1 during the first period is V1
  • the voltage of the first node N1 during the second period is V3, where V1 is not equal to V3 and is independent of the input voltage.
  • the voltage of the second node N2 during the first period is V2, and the voltage during the second period is V2 + V3-V1.
  • the voltage of the second node N2 during the first period is VDD-Vth, where Vth is the threshold voltage of the driving transistor T5.
  • the first node N1 receives the data voltage Vdata in the first period, and the first node N1 receives the reference voltage Vref in the second period.
  • the driving cycle further includes an initialization period earlier than the first period, and the voltage of the second node N2 is initialized during the initialization period.
  • a transistor T3 is connected between the gate and the drain of the driving transistor T5. The transistor T3 is turned on in the first period and turned off in the second period.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种像素电路和显示面板，该像素电路包括：数据信号输入单元(10)，用于根据当前级的扫描信号输入数据信号；驱动单元(30)，用于在导通时输出驱动信号；驱动控制单元(20)，用于根据发光控制信号控制驱动单元(30)导通；或者，根据前一级的扫描信号和发光控制信号控制驱动单元(30)导通；驱动控制单元(20)的数据信号输入端与驱动控制单元(20)的信号输出端之间设置一电容；开关电路(40)，用于在驱动单元(30)导通时根据发光控制信号导通，将驱动单元(30)输出的驱动信号传输至发光单元，驱动发光单元发光。实施该像素电路可以消除电源电压对亮度的影响，保证显示画面的亮度一致性。

Description

一种像素电路和显示面板 技术领域
本发明涉及显示领域，更具体地说，涉及一种像素电路和显示面板。
 背景技术
随着时代及技术的进步，大尺寸、高分辨率的AMOLED显示器件逐渐发展起来，大尺寸AMOLED显示器件也需要较大尺寸的面板及较多数量的像素，面板导线长度越来越长，导线电阻也越大，因此，电源电压不可避免地会在导线上产生电压降（IR Drop），并且，每个像素电路的电压降不同，因而造成每个像素电路获得的电源电压不同，从而在相同的数据信号电压输入下，不同的像素电路会有不同的亮度输出，进而导致整个面板的显示亮度不均匀，并且画面不同，像素的IR Drop也会跟着不同，从而使整个显示画面出现靠近Driver IC（驱动芯片）处偏亮，远离Driver IC处偏暗，亮度不均。
 技术问题
本发明要解决的技术问题在于，针对现有技术的上述电源电压对亮度的影响的缺陷，提供一种像素电路和显示面板。
 技术解决方案
本发明解决其技术问题所采用的技术方案是：一种像素电路，包括：
数据信号输入单元，用于根据当前级的扫描信号输入数据信号；
驱动单元，用于在导通时输出驱动信号；
驱动控制单元，用于根据发光控制信号控制所述驱动单元导通；或者，根据前一级的扫描信号和发光控制信号控制所述驱动单元导通；所述驱动控制单元的数据信号输入端与所述驱动控制单元的信号输出端之间设置一电容；
开关电路，用于在所述驱动单元导通时根据所述发光控制信号导通，将所述驱动单元输出的驱动信号传输至发光单元，以驱动所述发光单元发光。
优选地，所述数据信号输入单元包括：第一晶体管；
所述第一晶体管的第一电极连接当前级的组扫描信号，所述第一晶体管的第二电极连接数据信号，所述第一晶体管的第三电极与所述驱动控制单元的数据信号输入端连接。
优选地，所述驱动控制单元包括：第二晶体管和电容；
所述电容的第一端和所述第二晶体管的第二电极一并连接所述第一晶体管的第三电极，所述电容的第二端连接所述驱动单元的控制端；所述第二晶体管的第一电极连接发光控制信号，所述第二晶体管的第三电极连接参考信号；
所述电容的第一端为所述驱动控制单元的数据信号输入端，所述电容的第二端为所述驱动控制单元的信号输出端。
优选地，所述驱动单元包括：第三晶体管和第五晶体管；
所述第三晶体管的第三电极连接所述电容的第二端，所述第三晶体管的第二电极连接所述第五晶体管的第三电极，所述第三晶体管的第一电极连接所述当前级的扫描信号；
所述第五晶体管的第二电极连接电源信号，所述第五晶体管的第一电极连接所述电容的第二端，所述第五晶体管的第三电极连接所述开关电路；
所述第五晶体管的第一电极为所述驱动单元的控制端。
优选地，所述开关电路包括：第四晶体管；
所述第四晶体管的第二电极连接所述第五晶体管的第三电极，所述第四晶体管的第一电极连接所述发光控制信号，所述第四晶体管的第三电极连接所述发光单元的正极。
优选地，所述驱动控制单元还包括：第六晶体管；
所述第六晶体管的第三电极连接放电信号，所述第六晶体管的第二电极连接所述电容的第二端，所述第六晶体管的第一电极连接所述前一级的扫描信号。
优选地，所述驱动单元还包括：连接在所述第四晶体管与所述发光单元之间的第七晶体管；
其中，所述第七晶体管的第一电极连接所述发光控制信号，所述第七晶体管的第二电极连接所述第四晶体管的第三电极，所述第七晶体管的第三电极连接所述发光单元的正极。
优选地，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为PMOS管；
或者，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为NMOS管。
优选地，若所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管为PMOS管，则所述发光控制信号为低电平、所述当前级的扫描信号为高电平时，所述第四晶体管和第五晶体管导通，所述第三晶体管截止。
优选地，若所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管为NMOS管，则所述发光控制信号为高电平、所述当前级的扫描信号为低电平时，所述第四晶体管和第五晶体管导通，所述第三晶体管截止。
本发明还提供一种显示面板，包括以上所述的像素电路。
本发明还提供一种像素电路，包括第一节点、第二节点、连接于第一节点与第二节点之间的电容、以及驱动晶体管，所述驱动晶体管的栅极与所述第二节点连接，所述驱动晶体管的源极与输入电压VDD连接，漏极用于输出电流至发光单元，在像素电路的驱动周期内，所述第一节点在第一时段的电压为V1，所述第一节点在第二时段的电压为V3，其中V1不等于V3且均与输入电压无关，漏极输出的电流经由所述第二节点的电容耦合效应而满足公式I=K(V1-V3) 2，其中K为与输入电压无关的参数。
优选地，所述第二节点在第一时段的电压为V2，在第二时段的电压为V2+V3-V1。
优选地，所述第二节点在第一时段的电压为VDD-Vth，其中Vth为所述驱动晶体管的阈值电压。
优选地，在第一时段所述第一节点接收数据电压Vdata，在第二时段所述第一节点接收参考电压Vref，所述驱动晶体管的漏极输出的电流满足I=K(Vdata-Vref) 2。
优选地，驱动周期还包括早于第一时段的初始化时段，初始化时段内第二节点的电压被初始化。
优选地，所述驱动晶体管的栅极和漏极之间连接有晶体管T3，晶体管T3在第一时段导通，在第二时段截止。
 有益效果
通过采用本发明的像素电路可以使流过发光单元的电流只受数据信号的影响，而不再受电源电压的影响，从而消除的电源电压的变化对流过发光单元的电流的影响，消除了电源电压对亮度的影响，保证了显示画面的亮度一致性。
 附图说明
下面将结合附图及实施例对本发明作进一步说明，附图中：
图1是本发明提供的像素电路实施例一的电路图；
图2至图4是本发明提供的像素电路实施例一的各个信号的时序图；
图5是本发明提供的像素电路实施例二的电路图；
图6至图7是本发明提供的像素电路实施例二的各个信号的时序图。
 本发明的最佳实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图1是本发明提供的一种像素电路实施例一的电路图。该像素电路可应用于显示面板，其中，显示面板包括但不限于OLED显示面板、AMLOED显示面板、LCD面板、LED面板等。
进一步地，该像素电路设置在显示面板的发光区域。
如图1所示，本实施例中，该像素电路包括数据信号输入单元10、驱动单元30、驱动控制单元20以及开关电路40。其中，数据信号输入单元10用于根据当前级的扫描信号（Gn）输入数据信号。驱动单元30，用于在导通时输出驱动信号。驱动控制单元20，用于根据发光控制信号（EM）控制驱动单元30导通；或者，根据前一级的扫描信号（Gn-1）和发光控制信号控制驱动单元30导通；驱动控制单元的数据信号输入端与驱动控制单元的信号输出端之间设置一电容C。当驱动控制单元20通过发光控制信号控制驱动单元30导通时，驱动单元30在发光控制信号的有效期间导通；当驱动控制单元20通过发光控制信号和前一级的扫描信号控制驱动单元30导通时，驱动单元30在发光控制信号的有效电平期间且前一级的扫描信号处于无效电平期间导通。
进一步地，该数据信号输入单元10包括：第一晶体管T1，其中，第一晶体管T1的第一电极连接当前级的扫描信号（Gn），所述第一晶体管T1的第二电极连接数据（Vdata），所述第一晶体管T1的第三电极与所述驱动控制单元20的数据信号输入端连接。可选的，在该实施例中，第一晶体管T1为PMOS管。其中，第一晶体管T1的第一电极为PMOS管的栅极，第一晶体管T1的第二电极为PMOS管的源极，第一晶体管T1的第三电极为PMOS管的漏极。本实施例中，当前级的扫描信号（Gn）为低电平时，第一晶体管T1导通。
本实施例中，驱动控制单元20包括：第二晶体管T2和第六晶体管T6。其中，电容C的第一端和第二晶体管T2的第二电极一并连接第一晶体管T1的第三电极，电容C的第二端连接驱动单元30的控制端，第二晶体管T2的第一电极连接发光控制信号（EM），第二晶体管T2的第三电极连接参考（Vref）；第六晶体管T6的第一电极连接前一级的扫描信号（Gn-1），第六晶体管T6的第二电极连接电容C的第二端，第六晶体管T6的第三电极连接放电信号（Vinit）。其中，电容C的第一端为所述驱动控制单元20的数据信号输入端，电容C的第二端为驱动控制单元20的信号输出端。该实施例中，放电信号（Vinit）为低电平信号。
可选的，第二晶体管T2和第六晶体管T6均为PMOS管，其中，第二晶体管T2的第一电极为PMOS管的栅极，第二晶体管T2的第二电极为PMOS管的源极，第二晶体管T2的第三电极为PMOS管的漏极；第六晶体管T6的第一电极为PMOS管的栅极，第六晶体管T6的第二电极为PMOS管的源极，第六晶体管T6的第三电极为PMOS管的漏极。本实施例中前一级的扫描信号（Gn-1）为低电平时，第六晶体管T6导通，发光控制信号为低电平时，第二晶体管T2导通。
本实施例中，驱动单元30包括：第三晶体管T3、和第五晶体管T5。第三晶体管T3的第三电极连接所述电容C的第二端，所述第三晶体管T3的第二电极连接所述第五晶体管T5的第三电极，所述第三晶体管T3的第一电极连接所述当前级的扫描信号（Gn）；所述第五晶体管T5的第二电极连接电源信号（ELVDD），所述第五晶体管T5的第一电极连接所述电容C的第二端，所述第五晶体管T5的第三电极连接所述开关电路40；其中，第五晶体管T5的第一电极为所述驱动单元30的控制端。
在该实施例中，第五晶体管T5为本发明的像素电路的驱动晶体管。且当前级的扫描信号（Gn）为低电平时，第三晶体管T3导通，发光控制信号（EM）为低电平时，第四晶体管T4导通。
本实施例中，开关电路40包括：第四晶体管T4。第四晶体管T4的第二电极连接第五晶体管T5的第三电极，第四晶体管T4的第一电极连接发光控制信号（EM），第四晶体管T4的第三电极连接发光单元（OLED）的正极。
当然，可以理解地，在其他实施例中，还可以在第四晶体管T4与发光单元之间增加一个晶体管，即可在第四晶体管T4与发光单元之间增设第七晶体管T7（图中未示出），其中，第七晶体管T7的第一电极连接所述发光控制信号，所述第七晶体管T7的第二电极连接所述第四晶体管T4的第三电极，所述第七晶体管T7的第三电极连接所述发光单元的正极。其中，第七晶体管T7的类型与第五晶体管T5的类型相同。通过在第四晶体管T4与发光单元之间增设第七晶体管T7可以有效延长发光单元的使用寿命。
可选的，在该实施例中、第三晶体管T3、第四晶体管T4和第五晶体管T5均为PMOS管，其中，第三晶体管T3的第一电极为PMOS管的栅极，第三晶体管T3的第二电极为PMOS管的源极，第三晶体管T3的第三电极为PMOS管的漏极；第四晶体管T4的第一电极为PMOS管的栅极，第四晶体管T4的第二电极为PMOS管的源极，第四晶体管T4的第三电极为PMOS管的漏极；第五晶体管T5的第一电极为PMOS管的栅极，第五晶体管T5的第二电极为PMOS管的源极，第五晶体管T5的第三电极为PMOS管的漏极。
在此需要说明的是，当前级的扫描信号（Gn）、前一级的扫描信号（Gn-1）、发光控制信号（EM）、数据信号（Vdata）、以及参考信号（Vref）均由Driver IC提供，且数据信号（Vdata）为由Driver IC输出的用于图像显示的数据电压，参考信号（Vref）为Driver IC输出参考电压。
在此需要说明的是，本实施例的第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6可以采用PMOS管或者NMOS管。且在本发明的实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6的类型相同，即当采用PMOS管时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为PMOS管；当采用NMOS管时，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为NMOS管。
而且，当采用NMOS管时，当前级的扫描信号（Gn）的有效电平为高电平，发光控制信号（EM）的有效电平为高电平，前一级的扫描信号（Gn-1）的无效电平为低电平。
下面结合图2至图4的时序图对本实施例的像素电路的工作原理进行说明。在该实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6均为PMOS管。
如图2所示，首先，在t1时段，当前级的扫描信号（Gn）为高电平，第一晶体管T1截止，而数据信号单元在当前级的扫描信号（Gn）的有效电平期间将数据信号输入，所以数据信号不能输入。其中，在该实施例中，当前级的扫描信号（Gn）的有效电平为低电平，发光控制信号（EM）的有效电平为低电平，前一级的扫描信号（Gn-1）的无效电平为高电平。具体的，在t1时段，当前级的扫描信号（Gn）为高电平，第一晶体管T1截止；发光控制信号（EM）为高电平，第二晶体管T2、第三晶体管T3、第四晶体管T4均处于截止状态；而前一级的扫描信号（Gn-1）为低电平，所以第六晶体管T6导通，第五晶体管T5也开启，此时，电容C的第二端（N2点）电压为Vinit，由于Vinit低电平（负电压），而第一晶体管T1处于截止状态，数据信号（Vdata）不能输入，所以电容C处于放电状态。
接着，在t2时段（如图3所示），前一级的扫描信号（Gn-1）为高电平，当前级的扫描信号（Gn）为低电平，发光控制信号（EM）为高电平。此时，第一晶体管T1、第三晶体管T3导通，第二晶体管T2、第四晶体管T4、第六晶体管均截止，而由于上一帧N2电压为Vinit，所以此时第五晶体管T5也导通。此时，数据信号可以输入给电容C充电，电容C的第一端（N1点）电压为Vdata，电容C的第二端（N2点）电压为ELVDD-Vth，其中，Vth为第五晶体管T5的阈值电压。
然后，在第3时段（如图4所示），前一级的扫描信号（Gn-1）为高电平、当前级的扫描信号（Gn）为高电平，而发光控制信号（EM）为低电平。此时，第一晶体管T1、第三晶体管T3以及第六晶体管T6均截止，第二晶体管T2、第四晶体管T4和第五晶体管T5均导通。N1点电压为Vref，此时N1点的电压变化量为：Vref-Vdata；由电容的耦合原理可以得到，此时N2点的电压为：ELVDD-Vth+Vref-Vdata。
而由第五晶体管T5的导通特性可以得到：第五晶体管T5的导通电压为：Vgs-Vth，而Vgs=ELVDD-N2点的电压，所以可以得到第五晶体管T5的导通电压为：ELVDD-（ELVDD-Vth+Vref-Vdata）＝Vdata-Vref。根据电流公式可以得到流经发光单元（OLED）的电流为：
Figure dest_path_image001
。
其中，u为常数，C ox为第五晶体管T5的栅极和源漏极之间的寄生电容，W/L为第五晶体管T5的宽长比。
由上述电流公式可以看出，流经发光单元（OLED）的电流只受数据信号输入的数据电压及参考电压的影响，而与电源电压（ELVDD）没有关系，因此，可以消除电源电压对流过发光单元的电流的影响，消除了电源电压对亮度的影响，保证了显示画面亮度的一致性。
图5是本发明提供的一种像素电路实施例二的电路图。在该实施例中，该实施例的像素电路也包括数据信号输入单元10、驱动单元30以及驱动控制单元20。其中，数据信号输入单元10和驱动单元30均与实施例一的相同，而驱动控制单元20中则省去了第六晶体管T6。
下面结合图6和图7的时序图对本实施例的像素电路的工作原理进行说明。在该实施例中，第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5均为PMOS管。当前级的扫描信号（Gn）的有效电平为低电平，发光控制信号（EM）的有效电平为低电平。
如图6所示，在t1时段，当前级的扫描信号（Gn）为低电平，发光控制信号（EM）为高电平，此时，第一晶体管T1和第三晶体管T3均导通，第二晶体管T2和第四晶体管T4均截止，而由于上一帧发光情况，所以第五晶体管T5导通。此时，电容C的第一端（N1点）电压为Vdata，电容C的第二端（N2点）的电压为：ELVDD-Vth。
接着，在t2时段，当前级的扫描信号（Gn）为高电平，发光控制信号（EM）为低电平，此时，第二晶体管T2、第四晶体管T4和第五晶体管T5均导通，而第一晶体管T1和第三晶体管T3均截止。N1点的电压为Vref，所以，N1点的电压变化量为：Vref-Vdata；根据电容耦合原理可以得到，此时N2点的电压为：ELVDD-Vth+Vref-Vdata。
由第五晶体管T5的导通特性可以得到：第五晶体管T5的导通电压为：Vgs-Vth，而Vgs=ELVDD-N2点的电压，所以可以得到第五晶体管T5的导通电压为：ELVDD-（ELVDD-Vth+Vref-Vdata）。根据电流公式可以得到流经发光单元（OLED）的电流为：
Figure 789695dest_path_image001
。
其中，u为常数，C ox为第五晶体管T5的栅极和源漏极之间的寄生电容，W/L为第五晶体管T5的宽长比。
由上述电流公式可以看出，流经发光单元（OLED）的电流只受数据信号输入的数据电压及参考电压的影响，而与电源电压（ELVDD）没有关系，因此，可以消除电源电压对流过发光单元的电流的影响，消除了电源电压对亮度的影响，保证了显示画面亮度的一致性；另外，在该实施例中，通过将第六晶体管T6去掉，可以进一步提高显示面板的分辨率。
综上，本发明通过在像素电路中消除ELVDD对流过驱动晶体管（第五晶体管T5）电流大小的影响，从而达到消除ELVDD电压对亮度的影响，以保证整个显示画面的亮度一致性。
本发明还提供了一种显示面板，该显示面板包括一种像素电路，该像素电路为前文所述的像素电路。其中，该显示面板包括但不限于OLED显示面板、AMLOED显示面板等。
本发明还提供了一种像素电路，该像素电路包括第一节点N1、第二节点N2、连接于第一节点N1与第二节点N2之间的电容C、以及驱动晶体管T5（即前述的第五晶体管T5），该驱动晶体管T5的栅极与第二节点N2连接，该驱动晶体管T5的源极与输入电压VDD（即前述的ELVDD）连接，漏极用于输出电流至发光单元，在像素电路的驱动周期内，所述第一节点N1在第一时段的电压为V1，所述第一节点N1在第二时段的电压为V3，其中V1不等于V3且均与输入电压无关，漏极输出的电流经由第二节点N2的电容C耦合效应而满足公式I=K(V1-V3) 2，其中K为与输入电压无关的参数。
第二节点N2在第一时段的电压为V2，在第二时段的电压为V2+V3-V1。
或者，第二节点N2在第一时段的电压为VDD-Vth，其中Vth为驱动晶体管T5的阈值电压。
在第一时段第一节点N1接收数据电压Vdata，在第二时段第一节点N1接收参考电压Vref，该驱动晶体管T5的漏极输出的电流满足I=K(Vdata-Vref) 2。
进一步地，驱动周期还包括早于第一时段的初始化时段，初始化时段内第二节点N2的电压被初始化。
该驱动晶体管T5的栅极和漏极之间连接有晶体管T3，晶体管T3在第一时段导通，在第二时段截止。
由前述驱动晶体管T5的漏极输出的电流满足I=K(Vdata-Vref) 2可以看出，流入发光单元的电流与电源电压没有关系，只受数据电压和参考电压的影响，所以，可以消除电源电压对发光单元的影响，进而消除电源电压对亮度的影响，保证了显示画面亮度的一致性。
以上实施例只为说明本发明的技术构思及特点，其目的在于让熟悉此项技术的人士能够了解本发明的内容并据此实施，并不能限制本发明的保护范围。凡跟本发明权利要求范围所做的均等变化与修饰，均应属于本发明权利要求的涵盖范围。
应当理解的是，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，而所有这些改进和变换都应属于本发明所附权利要求的保护范围。

Claims (17)

  1. 一种像素电路，其特征在于，包括：
    数据信号输入单元，用于根据当前级的扫描信号输入数据信号；
    驱动单元，用于在导通时输出驱动信号；
    驱动控制单元，用于根据发光控制信号控制所述驱动单元导通；或者，根据前一级的扫描信号和发光控制信号控制所述驱动单元导通；所述驱动控制单元的数据信号输入端与所述驱动控制单元的信号输出端之间设置一电容；
    开关电路，用于将所述驱动单元输出的驱动信号传输至发光单元，以驱动所述发光单元发光。
  2. 根据权利要求1所述的像素电路，其特征在于，所述数据信号输入单元包括：第一晶体管；
    所述第一晶体管的第一电极连接当前级的组扫描信号，所述第一晶体管的第二电极连接数据信号，所述第一晶体管的第三电极与所述驱动控制单元的数据信号输入端连接。
  3. 根据权利要求2所述的像素电路，其特征在于，所述驱动控制单元包括：第二晶体管；
    所述电容的第一端和所述第二晶体管的第二电极一并连接所述第一晶体管的第三电极，所述电容的第二端连接所述驱动单元的控制端；所述第二晶体管的第一电极连接发光控制信号，所述第二晶体管的第三电极连接参考信号；
    所述电容的第一端为所述驱动控制单元的数据信号输入端，所述电容的第二端为所述驱动控制单元的信号输出端。
  4. 根据权利要求3所述的像素电路，其特征在于，所述驱动单元包括：第三晶体管和第五晶体管；
    所述第三晶体管的第三电极连接所述电容的第二端，所述第三晶体管的第二电极连接所述第五晶体管的第三电极，所述第三晶体管的第一电极连接所述当前级的扫描信号；
    所述第五晶体管的第二电极连接电源信号，所述第五晶体管的第一电极连接所述电容的第二端，所述第五晶体管的第三电极连接所述开关电路；
    所述第五晶体管的第一电极为所述驱动单元的控制端。
  5. 根据权利要求4所述的像素电路，其特征在于，所述开关电路包括：第四晶体管；
    所述第四晶体管的第二电极连接所述第五晶体管的第三电极，所述第四晶体管的第一电极连接所述发光控制信号，所述第四晶体管的第三电极连接所述发光单元的正极。
  6. 根据权利要求5所述的像素电路，其特征在于，所述驱动控制单元还包括：第六晶体管；
    所述第六晶体管的第三电极连接放电信号，所述第六晶体管的第二电极连接所述电容的第二端，所述第六晶体管的第一电极连接所述前一级的扫描信号。
  7. 根据权利要求5或6所述的像素电路，其特征在于，所述驱动单元还包括：连接在所述第四晶体管与所述发光单元之间的第七晶体管；
    其中，所述第七晶体管的第一电极连接所述发光控制信号，所述第七晶体管的第二电极连接所述第四晶体管的第三电极，所述第七晶体管的第三电极连接所述发光单元的正极。
  8. 根据权利要求6所述的像素电路，其特征在于，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为PMOS管；
    或者，所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管均为NMOS管。
  9. 根据权利要求8所述的像素电路，其特征在于，若所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管为PMOS管，则所述发光控制信号为低电平、所述当前级的扫描信号为高电平时，所述第四晶体管和第五晶体管导通，所述第三晶体管截止。
  10. 根据权利要求8所述的像素电路，其特征在于，若所述第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管和第六晶体管为NMOS管，则所述发光控制信号为高电平、所述当前级的扫描信号为低电平时，所述第四晶体管和第五晶体管导通，所述第三晶体管截止。
  11. 一种显示面板，其特征在于，包括权利要求1-10任一项所述的像素电路。
  12. 一种像素电路，其特征在于，包括第一节点、第二节点、连接于第一节点与第二节点之间的电容、以及驱动晶体管，所述驱动晶体管的栅极与所述第二节点连接，所述驱动晶体管的源极与输入电压VDD连接，漏极用于输出电流至发光单元，在像素电路的驱动周期内，所述第一节点在第一时段的电压为V1，所述第一节点在第二时段的电压为V3，其中V1不等于V3且均与输入电压无关，漏极输出的电流经由所述第二节点的电容耦合效应而满足公式I=K(V1-V3) 2，其中K为与输入电压无关的参数。
  13. 根据权利要求12所述的像素电路，其特征在于，所述第二节点在第一时段的电压为V2，在第二时段的电压为V2+V3-V1。
  14. 根据权利要求12所述的像素电路，其特征在于，所述第二节点在第一时段的电压为VDD-Vth，其中Vth为所述驱动晶体管的阈值电压。
  15. 根据权利要求12所述的像素电路，其特征在于，在第一时段所述第一节点接收数据电压Vdata，在第二时段所述第一节点接收参考电压Vref，所述驱动晶体管的漏极输出的电流满足I=K(Vdata-Vref) 2。
  16. 根据权利要求12所述的像素电路，其特征在于，驱动周期还包括早于第一时段的初始化时段，初始化时段内第二节点的电压被初始化。
  17. 根据权利要求12所述的像素电路，其特征在于，所述驱动晶体管的栅极和漏极之间连接有晶体管T3，晶体管T3在第一时段导通，在第二时段截止。
     
     
PCT/CN2018/107890 2018-09-27 2018-09-27 一种像素电路和显示面板 WO2020061886A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201880094142.5A CN112639949A (zh) 2018-09-27 2018-09-27 一种像素电路和显示面板
PCT/CN2018/107890 WO2020061886A1 (zh) 2018-09-27 2018-09-27 一种像素电路和显示面板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2018/107890 WO2020061886A1 (zh) 2018-09-27 2018-09-27 一种像素电路和显示面板

Publications (1)

Publication Number Publication Date
WO2020061886A1 true WO2020061886A1 (zh) 2020-04-02

Family

ID=69950144

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2018/107890 WO2020061886A1 (zh) 2018-09-27 2018-09-27 一种像素电路和显示面板

Country Status (2)

Country Link
CN (1) CN112639949A (zh)
WO (1) WO2020061886A1 (zh)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064573B2 (en) * 2003-05-26 2006-06-20 Seiko Epson Corporation Driving circuit, method of testing driving circuit, electro-optical apparatus, and electro-optical device
CN104575392A (zh) * 2015-02-02 2015-04-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法
CN105206246A (zh) * 2015-10-31 2015-12-30 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105679249A (zh) * 2016-03-31 2016-06-15 上海天马有机发光显示技术有限公司 驱动电路、有机电致发光二极管显示器及驱动方法
CN107610640A (zh) * 2017-09-28 2018-01-19 京东方科技集团股份有限公司 一种阵列基板及驱动方法、显示面板和显示设备
CN108288456A (zh) * 2018-04-28 2018-07-17 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105206221B (zh) * 2014-06-13 2018-06-22 京东方科技集团股份有限公司 像素驱动电路、驱动方法、阵列基板及显示装置
CN106875894B (zh) * 2017-03-13 2019-01-18 京东方科技集团股份有限公司 一种像素电路及其驱动方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064573B2 (en) * 2003-05-26 2006-06-20 Seiko Epson Corporation Driving circuit, method of testing driving circuit, electro-optical apparatus, and electro-optical device
CN104575392A (zh) * 2015-02-02 2015-04-29 京东方科技集团股份有限公司 像素驱动电路及其驱动方法
CN105206246A (zh) * 2015-10-31 2015-12-30 武汉华星光电技术有限公司 扫描驱动电路及具有该电路的液晶显示装置
CN105679249A (zh) * 2016-03-31 2016-06-15 上海天马有机发光显示技术有限公司 驱动电路、有机电致发光二极管显示器及驱动方法
CN107610640A (zh) * 2017-09-28 2018-01-19 京东方科技集团股份有限公司 一种阵列基板及驱动方法、显示面板和显示设备
CN108288456A (zh) * 2018-04-28 2018-07-17 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示装置

Also Published As

Publication number Publication date
CN112639949A (zh) 2021-04-09

Similar Documents

Publication Publication Date Title
WO2020001635A1 (zh) 驱动电路及其驱动方法、显示装置
CN110223636B (zh) 像素驱动电路及其驱动方法、显示装置
WO2021238470A1 (zh) 像素电路及其驱动方法、显示面板
TWI498873B (zh) 有機發光二極體電路及其驅動方法
WO2020062802A1 (zh) 显示面板及像素电路的驱动方法
WO2018188390A1 (zh) 像素电路及其驱动方法、显示装置
WO2020155895A1 (zh) 栅极驱动电路及其驱动方法、显示装置及其控制方法
WO2020001554A1 (zh) 像素电路及其驱动方法、显示面板
CN107863069B (zh) 像素电路及其驱动方法、显示基板及显示装置
WO2016150232A1 (zh) 像素电路及其驱动方法、显示装置
WO2020181515A1 (zh) 像素电路及其驱动方法、显示装置
WO2018214533A1 (zh) 显示装置以及像素电路及其控制方法
JP2006309149A (ja) 有機電界発光表示装置
WO2020192278A1 (zh) 像素电路及其驱动方法、显示基板、显示装置
TWI470604B (zh) 反向器電路及顯示器
KR100966502B1 (ko) 발광 표시장치의 구동회로 및 구동방법
KR101678333B1 (ko) 화소회로, 디스플레이 장치 및 그 구동방법
KR20120043301A (ko) 유기발광다이오드 표시장치 및 그 구동방법
US11094252B2 (en) Display-driving method and a display apparatus
WO2019237756A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
TW201619944A (zh) 畫素單元及其驅動方法
WO2020187158A1 (zh) 像素驱动电路和显示面板及其驱动方法、显示装置
WO2017045376A1 (zh) 像素电路及其驱动方法、显示面板和显示装置
KR20160052940A (ko) 스캔 구동 장치 및 이를 이용한 표시 장치
WO2020062811A1 (zh) 像素电路及其驱动方法、显示面板、显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 18934950

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 18934950

Country of ref document: EP

Kind code of ref document: A1