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WO2020181515A1 - 像素电路及其驱动方法、显示装置 - Google Patents

像素电路及其驱动方法、显示装置 Download PDF

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Publication number
WO2020181515A1
WO2020181515A1 PCT/CN2019/077927 CN2019077927W WO2020181515A1 WO 2020181515 A1 WO2020181515 A1 WO 2020181515A1 CN 2019077927 W CN2019077927 W CN 2019077927W WO 2020181515 A1 WO2020181515 A1 WO 2020181515A1
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WIPO (PCT)
Prior art keywords
transistor
terminal
voltage
electrically connected
potential
Prior art date
Application number
PCT/CN2019/077927
Other languages
English (en)
French (fr)
Inventor
殷新社
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/642,807 priority Critical patent/US11107408B2/en
Priority to CN201980000294.9A priority patent/CN110062944B/zh
Priority to PCT/CN2019/077927 priority patent/WO2020181515A1/zh
Publication of WO2020181515A1 publication Critical patent/WO2020181515A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0262—The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0278—Details of driving circuits arranged to drive both scan and data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0285—Improving the quality of display appearance using tables for spatial correction of display data
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, and a display device.
  • the threshold voltage of the driving transistor in different pixels of an OLED (Organic Light Emitting Diode) display panel may be different at the same time.
  • the threshold voltage of the driving transistor in the same pixel may be different at different times, that is, the threshold voltage of the driving transistor has a drift phenomenon.
  • the driving current for driving the OLED in different pixels will also be different. This results in different display brightness of different pixels, resulting in uneven display brightness of the display panel.
  • a pixel circuit including: a light emitting element including an anode and a cathode; a first switch circuit configured to respond to a first scan signal from a first scan line, In the case of transmitting the voltage from the data line; a driving circuit configured to drive the light emitting element to emit light under the control of the voltage transmitted by the first switch circuit, the driving circuit including: a first transistor, the first transistor The control terminal is configured to be electrically connected to the first switch circuit, the first terminal of the first transistor is electrically connected to the first voltage terminal, and the second terminal of the first transistor is electrically connected to the anode of the light emitting element.
  • a capacitor the first end of the capacitor is electrically connected to the first voltage terminal, and the second end of the capacitor is electrically connected to the first switch circuit; and a second switch circuit is connected to the data line ,
  • the second end of the first transistor is electrically connected to the anode of the light-emitting element, and is configured to respond to the second scan signal from the second scan line to turn on the potential on the data line They are respectively stabilized at a first fixed potential and a second fixed potential, the first fixed potential makes the light emitting element emit light, and the second fixed potential makes the first transistor cut off.
  • the second switch circuit includes a second transistor, the control terminal of the second transistor is configured to receive the second scan signal, and the first terminal of the second transistor is connected to the data line The second end of the second transistor is electrically connected to the anode of the light-emitting element.
  • the data line is electrically connected to a reset circuit, the potential of the data line is reset by the reset circuit to a first initial potential and a second initial potential, respectively, and the first initial potential causes the light emission The element does not emit light, and the second initial potential turns on the first transistor.
  • the cathode of the light emitting element is electrically connected to a control circuit, and under the control of the control circuit, the cathode of the light emitting element is electrically connected to the second voltage terminal or the fourth voltage terminal; wherein, the The potential of the second voltage terminal makes the light-emitting element in a forward bias, and the potential of the fourth voltage terminal makes the light-emitting element in a reverse bias.
  • the first switch circuit includes a third transistor, the control terminal of the third transistor is configured to receive the first scan signal, and the first terminal of the third transistor is connected to the data line The second end of the third transistor is electrically connected to the second end of the capacitor and the control end of the first transistor.
  • a display device including a plurality of pixel units, and each pixel unit includes the pixel circuit described in any one of the above embodiments.
  • the display device further includes: a plurality of first scan lines, each of the first scan lines is electrically connected to a pixel circuit in the same row of pixel units; a plurality of second scan lines, each of the second scan lines The line is electrically connected with pixel circuits in the same row of pixel units; and a plurality of data lines, each data line is electrically connected with the pixel circuits in the same column of pixel units.
  • the display device further includes: a plurality of reset circuits arranged in the non-display area or the source driver of the display device, each reset circuit is electrically connected to a corresponding data line, and each reset circuit The circuit is configured to reset the potential of the corresponding data line to a first initial potential and a second initial potential, respectively, in response to the reset signal.
  • the first initial potential makes the pixel unit electrically connected to the data line a
  • the light-emitting element does not emit light
  • the second initial potential turns on the first transistor in each pixel unit electrically connected to the data line.
  • each reset circuit includes a fourth transistor, the control terminal of the fourth transistor is configured to receive the reset signal, the first terminal of the fourth transistor is electrically connected to a corresponding data line, and The second terminal of the fourth transistor is electrically connected to the third voltage terminal.
  • the display device further includes a control circuit, which is provided in a non-display area of the display device or a power source of the display device, and the control circuit is connected to the cathode of the light-emitting element in each pixel unit. Electrically connected; the control circuit is configured to respond to at least one control signal so that the cathode of the light-emitting element in each pixel unit is electrically connected to the second voltage terminal or the fourth voltage terminal, wherein the potential of the second voltage terminal The light-emitting element is made to be in a forward bias, and the potential of the fourth voltage terminal makes the light-emitting element to be in a reverse bias.
  • a control circuit which is provided in a non-display area of the display device or a power source of the display device, and the control circuit is connected to the cathode of the light-emitting element in each pixel unit. Electrically connected; the control circuit is configured to respond to at least one control signal so that the cathode of the light-emitting element in each
  • the at least one control signal includes a first control signal and a second control signal;
  • the control circuit includes a fifth transistor, and the control terminal of the fifth transistor is configured to receive the first control signal.
  • the first terminal of the fifth transistor is electrically connected to the cathode of the light-emitting element in each pixel unit, the second terminal of the fifth transistor is electrically connected to the fourth voltage terminal; and the sixth transistor, so The control terminal of the sixth transistor is configured to receive the second control signal, the first terminal of the sixth transistor is electrically connected to the cathode of the light-emitting element in each pixel unit, and the second terminal of the sixth transistor It is electrically connected to the second voltage terminal.
  • a method for driving a pixel circuit as described in any one of the above embodiments including: in a first stage, stabilizing the potential on the data line at the first stage where the light emitting element emits light. A fixed potential; in the second stage, the potential on the data line is stabilized at a second fixed potential that makes the first transistor cut off; in the display stage, a compensated data voltage is provided to the data line to drive the light emission The element emits light, wherein the compensated data voltage is determined according to the first fixed potential and the second fixed potential.
  • the first stage includes a first non-display stage and a second non-display stage after the first non-display stage; in the first non-display stage, the first switch circuit responds to The first scan signal of the first scan line is turned on to transmit the sensing voltage from the data line to the second terminal of the capacitor and the control terminal of the first transistor, and the first transistor is at the sensing voltage Is turned on to generate a sensing current under the control of, and the second switch circuit is non-conductive in response to the second scan signal from the second scan line; in the second non-display phase, the first switch circuit is responsive to the The first scan signal is not turned on, and the second switch circuit is turned on in response to the second scan signal so that the sensing current charges the data line, so that the potential on the data line is stabilized at The first fixed potential at which the light-emitting element emits light.
  • the second stage includes a third non-display stage; in the third non-display stage, the second switch circuit is turned on in response to the second scan signal to charge the data line In response to the first scan signal, the first switch circuit is turned on so that the data line charges the capacitor, so that the potential on the data line is stabilized at a second fixed potential that turns off the first transistor.
  • the first stage further includes a fourth non-display stage located between the first non-display stage and the second non-display stage; in the fourth non-display stage, the The potential of the data line is reset to the first initial potential at which the light-emitting element does not emit light, the first switch circuit is non-conductive in response to the first scan signal, and the second switch circuit is in response to the second scan.
  • the signal is on.
  • the second stage further includes a fifth non-display stage before the third non-display stage; in the fifth non-display stage, the potential of the data line is reset to make the A second initial potential at which the first transistor is turned on, the first switch circuit is turned on in response to the first scan signal, and the second switch circuit is turned on in response to the second scan signal.
  • the first stage further includes a sixth non-display stage after the second non-display stage; in the sixth non-display stage, the source driver reads the data line from the data line.
  • the first fixed potential in the sixth non-display stage, the source driver reads the data line from the data line.
  • the second stage further includes a seventh non-display stage after the third non-display stage; in the seventh non-display stage, the source driver reads the data line The second fixed potential.
  • the first stage is at the power-on of the display panel.
  • the second phase is located between the end time of the display phase and the shutdown time of the display panel.
  • the first switch circuit in response to the first scan signal to transmit the compensated data voltage from the data line to the second terminal of the capacitor And the control terminal of the first transistor, the first transistor is turned on under the control of the compensated data voltage to generate a driving current for driving the light-emitting element to emit light, and the second switch circuit is responsive to the The second scan signal is not turned on; wherein the compensated data voltage is the sum of the data voltage before compensation, the first compensation voltage, and the second compensation voltage, and the first compensation voltage is determined according to the threshold voltage of the first transistor It is determined that the second compensation voltage is determined according to the operating voltage of the light emitting element, the threshold voltage of the first transistor is determined according to the second fixed potential of the previous display period of the current display period, and the operation of the light emitting element The voltage is determined according to the first fixed potential of the current display period.
  • Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure
  • Fig. 3 is a schematic diagram of a display period according to an embodiment of the present disclosure.
  • FIG. 4 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure.
  • Fig. 5 is a timing control signal diagram of a pixel circuit according to an embodiment of the present disclosure.
  • FIG. 6 is a timing control signal diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 7 is a timing control signal diagram of a pixel circuit according to another embodiment of the present disclosure.
  • FIG. 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • a specific component when it is described that a specific component is located between the first component and the second component, there may or may not be an intermediate component between the specific component and the first component or the second component.
  • the specific component When it is described that a specific component is connected to another component, the specific component may be directly connected to the other component without an intermediate component, or may not be directly connected to the other component but with an intermediate component.
  • Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes a light-emitting element 10, a first switching circuit 20, a driving circuit 30 and a second switching circuit 40.
  • the light emitting element 10 includes an anode and a cathode.
  • the light-emitting element 10 may be an OLED or the like, for example.
  • the anode of the light-emitting element 10 is electrically connected to the driving circuit 30 and the second switch circuit 40, and the cathode of the light-emitting element 10 may be electrically connected to the second voltage terminal ELV SS or the fourth voltage terminal ELV DD′ under the control of the control circuit 60, for example.
  • the potential of the second voltage terminal ELV SS makes the light-emitting element 10 in a forward bias
  • the potential of the fourth voltage terminal ELV DD' makes the light-emitting element 10 in a reverse bias.
  • the first switch circuit 20 is electrically connected between the data line DL and the driving circuit 30.
  • the first switch circuit 20 is configured to transmit the voltage from the data line DL to the driving circuit 30 in response to the first scan signal G from the first scan line, in the case of conduction.
  • a first driving circuit 30 includes a transistor T1 (i.e., a driving transistor) and a capacitor C st.
  • the control terminal of the first transistor T1 is electrically connected to the first switch circuit 20, the first terminal of the first transistor T1 is electrically connected to the first voltage terminal ELV DD , and the second terminal of the first transistor T1 is electrically connected to the anode of the light emitting element 10 .
  • the first terminal of the capacitor C st is electrically connected to the first voltage terminal ELV DD , and the second terminal of the capacitor C st is electrically connected to the first switch circuit 20 and the control terminal of the first transistor T1.
  • the second switch circuit 40 is electrically connected to the data line DL, the second end of the first transistor T1 and the anode of the light emitting element 10.
  • the second switch circuit 40 is configured to, in response to the second scan signal S from the second scan line, stabilize the potential on the data line DL at the first fixed potential and the second fixed potential when turned on.
  • the first fixed potential causes the light emitting element 10 to emit light
  • the second fixed potential causes the first transistor T1 to turn off.
  • the potential on the data line DL can be stabilized at the first fixed potential and the second fixed potential at different stages, respectively, which will be described later in conjunction with the driving method.
  • the first fixed potential is the sum of the potential of the cathode of the light-emitting element 10 and the working voltage V OLED of the light-emitting element 10. Therefore, after the potential on the data line DL is stabilized at the first fixed potential, the first fixed potential on the data line DL can be read, and the working voltage V OLED of the light-emitting element 10 can be obtained.
  • a source driver that provides a data voltage can read the first fixed potential on the data line DL and store the operating voltage V OLED of the light-emitting element 10.
  • the data voltage V data provided by the source driver to the data line DL may be the sum of the original data voltage V pixel and the second compensation voltage f2 (V OLED ) to compensate for the luminous efficiency of the light-emitting element 10.
  • the second compensation voltage f2 (V OLED ) is determined according to the operating voltage V OLED of the light-emitting element 10. It should be understood that the luminous efficiency corresponding to the working voltage V OLED of the light-emitting element 10 can be determined by the compensation model between the working voltage of the light-emitting element and the luminous efficiency, and then the compensation voltage required to compensate for the decrease in the luminous efficiency of the light-emitting element 10 can be determined. , That is, the second compensation voltage f2 (V OLED ).
  • the second fixed potential is the sum of the potential of the first voltage terminal ELV DD and the threshold voltage V TH of the first transistor T1. Therefore, after the potential on the data line DL is stabilized at the second fixed potential, the second fixed potential on the data line DL can be read, so that the threshold voltage V TH of the first transistor T1 can be obtained.
  • a source driver that provides a data voltage can read the second fixed potential on the data line DL and store the threshold voltage V TH of the first transistor T1.
  • the data voltage V data provided by the source driver to the data line DL may be the sum of the original data voltage V pixel and the first compensation voltage f1 (V TH ) to compensate the threshold voltage V TH of the first transistor T1 , Thereby alleviating the problem of uneven display brightness caused by the difference in the threshold voltage V TH of the first transistor T1.
  • the first compensation voltage f1 (V TH ) is determined according to the threshold voltage V TH of the first transistor T1.
  • the first compensation voltage f1 (V TH ) may be equal to the threshold voltage V TH .
  • the first compensation voltage f1 (V TH ) may be the sum or difference between the threshold voltage V TH and other values.
  • the other value may be, for example, the average value of the threshold voltage V TH of the first transistor T1 in different pixels.
  • the potential on the data line can be stabilized at the first fixed potential and the second fixed potential respectively.
  • the operating voltage of the light-emitting element can be obtained from the first fixed potential
  • the threshold voltage of the first transistor can be obtained from the second fixed potential.
  • the luminous efficiency of the light-emitting element and the threshold voltage of the first transistor can be compensated externally, so as to reduce the uneven display brightness caused by the decrease in the luminous efficiency of the light-emitting element and the difference in the threshold voltage of the first transistor. problem.
  • the data line DL is electrically connected to the reset circuit 50.
  • the potential of the data line DL is reset to the first initial potential Vini1 and the second initial potential Vini2 by the reset circuit 50, respectively.
  • the first initial potential V ini1 makes the light emitting element 10 not emit light
  • the second initial potential V ini2 makes the first transistor T1 conductive.
  • the difference between the first initial potential V ini1 and the potential of the cathode of the light-emitting element 10 is less than the operating voltage V OLED of the light-emitting element 10, so the light-emitting element 10 does not emit light.
  • the first initial potential V ini1 and the second initial potential V ini2 may be the same. In other embodiments, the first initial potential V ini1 and the second initial potential V ini2 may also be different.
  • the potential on the data line may be reset to the first initial potential that makes the light-emitting element not emit light before being stabilized at the first fixed potential that makes the light-emitting element emit light.
  • it before being stabilized at the second fixed potential for turning off the first transistor, it may be reset to the second initial potential for turning on the first transistor.
  • This method can reduce the impact of the potential fluctuation of the data line before the first fixed potential on the first fixed potential, so that the first fixed potential is more accurate, so that the final operating voltage V OLED of the light-emitting element is obtained. More accurate.
  • the influence of the potential fluctuation of the data line before the second fixed potential on the second fixed potential can be reduced, so that the second fixed potential is more accurate, so that the threshold voltage V of the first transistor is finally obtained. TH is more accurate.
  • the cathode of the light-emitting element 10 may be electrically connected to the control circuit 60. Under the control of the control circuit 60, the cathode of the light emitting element 10 is electrically connected to the second voltage terminal ELV SS or the fourth voltage terminal ELV DD' .
  • the potential of the second voltage terminal ELV SS makes the light-emitting element 10 in a forward bias
  • the potential of the fourth voltage terminal ELV DD′ makes the light-emitting element 10 in a reverse bias.
  • the potential of the fourth voltage terminal ELV DD′ and the potential of the first voltage terminal ELV DD may be the same to reduce the number of power terminals.
  • the cathode of the light emitting element 10 when the cathode of the light emitting element 10 is connected to the second voltage terminal ELV SS , the light emitting element 10 is in a forward biased state, so it can emit light when the conditions are met; and the cathode of the light emitting element 10 is connected to In the case of the fourth voltage terminal ELV DD' , the light-emitting element 10 is in a reverse bias state, and therefore does not emit light.
  • FIG. 2 is a schematic flowchart of a driving method of a pixel circuit according to an embodiment of the present disclosure.
  • Fig. 3 is a schematic diagram of a display period according to an embodiment of the present disclosure. In FIG. 3, a display period is between the power-on time of the display panel where the pixel circuit is located and the power-off time of the display panel.
  • step 202 in the first stage M1, the potential on the data line DL is stabilized at a first fixed potential that causes the light-emitting element 10 to emit light.
  • the first stage M1 may be located between the power-on time of the display panel and the start time of the display phase (ie, the time when the display panel starts to display images). Before the display stage, the light-emitting element 10 does not emit light, and the operating voltage of the light-emitting element 10 is less affected by the junction temperature of the light-emitting element 10. The first fixed potential obtained at this time is more accurate, so that the final light-emitting element 10 can work. The voltage V OLED is more accurate.
  • step 204 in the second phase M2, the potential on the data line DL is stabilized at a second fixed potential that turns off the first transistor T1.
  • the second phase M2 may be located between the end time of the display phase (that is, the time when the display panel ends displaying images) and the shutdown time of the display panel. Since the display phase has passed, the junction temperature of the first transistor T1 is in a stable state, and the threshold voltage V TH is reduced by the junction temperature of the first transistor T1. In this case, the second fixed potential obtained is more accurate, so that the obtained threshold voltage V TH is closer to the voltage when the first transistor T1 is operating, and is more accurate.
  • the display period shown in FIG. 3 is only an example.
  • the first stage M1 and the second stage M2 may both be located between the power-on time of the display panel and the start time of the display stage, or may both be located between the end time and the end time of the display stage. Between the moments when the display panel is turned off.
  • step 206 in the display phase, the compensated data voltage is provided to the data line DL to drive the light-emitting element 10 to emit light.
  • the compensated data voltage is determined according to the first fixed potential and the second fixed potential.
  • the display phase a first switching circuit 20 in response to the first scan signal G is turned on to transfer the compensated data voltage from the data line DL to the second end of the capacitor C st and the first transistor Control terminal of T1.
  • the first transistor T1 is turned on under the control of the compensated data voltage to generate a driving current for driving the light-emitting element 10 to emit light.
  • the second switch circuit 40 is non-conductive in response to the second scan signal S.
  • the data voltage after compensation is the sum of the data voltage before compensation (also referred to as the original data voltage V pixel ), the first compensation voltage f1 (V TH ), and the second compensation voltage f2 (V OLED ).
  • the first compensation voltage f1 (V TH ) is determined according to the threshold voltage V TH of the first transistor T1.
  • the second compensation voltage f2 (V OLED ) is determined according to the operating voltage V OLED of the light-emitting element 10.
  • the operating voltage of the light-emitting element 10 may be determined according to the first fixed potential V1 of the current display period
  • the threshold voltage V TH of the first transistor T1 may be determined according to the second fixed potential of the previous display period of the current display period. V2 to determine.
  • the compensated data voltage can compensate the luminous efficiency of the light-emitting element 10 and the threshold voltage V TH of the first transistor T1, so as to alleviate the decrease in the luminous efficiency of the light-emitting element 10 and the threshold voltage of the first transistor T1.
  • the problem of uneven display brightness caused by the difference in voltage V TH is a problem of uneven display brightness caused by the difference in voltage V TH .
  • the first stage M1 may include a first non-display stage t1 and a second non-display stage t2 located after the first non-display stage t1.
  • the second switch circuit 40 does not conduct in response to the second scan signal S from the second scan line; while the first switch circuit 20 conducts in response to the first scan signal G from the first scan line. pass, to sense the voltage of the data line DL transmission from the second terminal to the control terminal of the first transistor T1 and a capacitor C st is.
  • the first transistor T1 is turned on under the control of the sensing voltage to generate a sensing current.
  • the sensing voltage is the sum of the initial voltage and the first compensation voltage f1 (V TH ).
  • the first compensation voltage f1 (V TH ) is determined according to the threshold voltage V TH of the first transistor T1.
  • the sensing voltage received by the driving circuit 30 in the first non-display period t1 is a voltage obtained by compensating the threshold voltage of the first transistor T1, so that the sensing current generated by the first transistor T1 is a constant sensing current.
  • the initial voltage is configured to cause the first transistor T1 to generate a sensing current.
  • the initial voltage can be set according to the actual situation. For example, the value of the initial voltage can be set according to the desired sensing current.
  • the first switch circuit 20 is non-conductive in response to the first scan signal G from the first scan line; and the second switch circuit 40 is conductive in response to the second scan signal S from the second scan line. It is turned on, so that the sensing current generated by the first transistor T1 charges the data line DL, so that the potential on the data line DL is stabilized at the first fixed potential that makes the light-emitting element 10 emit light.
  • the first stage M1 may further include a fourth non-display stage t4 located between the first non-display stage t1 and the second non-display stage t2.
  • the potential of the data line DL is reset to the first initial potential at which the light-emitting element 10 does not emit light.
  • the first switch circuit 20 is not turned on in response to the first scan signal G, and the second switch circuit 40 is turned on in response to the second scan signal S.
  • the potential on the data line DL is stabilized at the first fixed potential that causes the light-emitting element 10 to emit light in the second non-display period t2, and is reset to make the light-emitting element 10 not emit light in the fourth non-display period t4.
  • the first initial potential can reduce the impact of the potential fluctuation of the data line DL before the first fixed potential on the first fixed potential, so that the first fixed potential is more accurate, so that the final operating voltage V of the light-emitting element is obtained. OLED is more accurate.
  • the first stage M1 further includes a sixth non-display stage t6 after the second non-display stage t2.
  • the source driver reads the first fixed potential from the data line DL.
  • the second stage M2 according to different embodiments of the present disclosure will be described below in conjunction with FIG. 3.
  • the second stage M2 may include a third non-display stage t3.
  • the second switch circuit 40 is turned on in response to the second scan signal S to charge the data line DL.
  • the first switch circuit 20 is turned on in response to the first scan signal G to make the data line DL charge the capacitor, so that the potential on the data line DL is stabilized at a second fixed potential that turns off the first transistor T1.
  • the second stage M2 may further include a fifth non-display stage t5 before the third non-display stage t3.
  • the potential of the data line DL is reset to a second initial potential that turns on the first transistor T1 in the driving circuit.
  • the first switch circuit 20 is turned on in response to the first scan signal G
  • the second switch circuit 40 is turned on in response to the second scan signal S.
  • the potential on the data line DL is reset to the second initial potential that turns on the first transistor T1 before being stabilized at the second fixed potential that turns off the first transistor T1.
  • This method can reduce the influence of the potential fluctuation of the data line DL before it stabilizes at the second fixed potential on the second fixed potential, so that the second fixed potential is more accurate, and the threshold value of the first transistor T1 finally obtained The voltage V TH is more accurate.
  • the second stage M2 may further include a seventh non-display stage t7 after the third non-display stage t3.
  • the source driver reads the second fixed potential from the data line DL.
  • FIG. 4 is a schematic structural diagram of a pixel circuit according to another embodiment of the present disclosure. The following describes specific implementations of each circuit in the pixel circuit, as well as the reset circuit and the control circuit in conjunction with FIG. 4. It should be understood that although the pixel circuit in FIG. 4 shows a specific implementation of each circuit, in some embodiments, one or more circuits are not limited to the implementation shown in FIG. 4.
  • the second switch circuit 40 includes a second transistor T2.
  • the control terminal of the second transistor T2 is configured to receive the second scan signal S, the first terminal of the second transistor T2 is electrically connected to the data line DL, and the second terminal of the second transistor T2 is electrically connected to the anode of the light-emitting element 10.
  • the first switch circuit 20 includes a third transistor T3.
  • the control terminal of the third transistor T3 is configured to receive a first scanning signal G, the first terminal of the third transistor T3 is electrically connected to the data line DL, a second terminal of the third transistor T3 and a second terminal of the capacitor C st and The control terminal of a transistor T1 is electrically connected.
  • the reset circuit 50 includes a fourth transistor T4.
  • the control terminal of the fourth transistor T4 is configured to receive the reset signal R, the first terminal of the fourth transistor T4 is electrically connected to the data line DL, and the second terminal of the fourth transistor T4 is electrically connected to the third voltage terminal V ini .
  • the control circuit 60 includes a fifth transistor T5 and a sixth transistor T6.
  • the control terminal of the fifth transistor T5 is configured to receive the first control signal SEN, the first terminal of the fifth transistor T5 is electrically connected to the cathode of the light-emitting element 10, and the second terminal of the fifth transistor T5 is connected to the fourth voltage terminal ELV DD' Electric connection.
  • the control terminal of the sixth transistor T6 is configured to receive the second control signal EM, the first terminal of the sixth transistor T6 is electrically connected to the cathode of the light emitting element 10, and the second terminal of the sixth transistor T6 is electrically connected to the second voltage terminal ELV SS . connection.
  • the pixel circuit only includes three transistors and one capacitor (ie, 3T1C).
  • Such a pixel circuit has a simple structure, which not only can realize the sensing of the working voltage of the light-emitting element and the threshold voltage of the first transistor (that is, the driving transistor), but also helps to improve the aperture ratio of the pixel and the resolution of the display panel.
  • each transistor in the pixel circuit of FIG. 4 may be a P-type thin film transistor (TFT).
  • the first transistor T1 in the pixel circuit shown in FIG. 4 may be a P-type transistor, some of the other transistors may be an N-type TFT, and the remaining transistors may be a P-type TFT.
  • the active layer of each transistor may include but is not limited to Low Temperature Poly-silicon (LTPS).
  • each transistor in the pixel circuit shown in FIG. 4 is a P-type TFT.
  • FIG. 5 is a timing control signal diagram of a pixel circuit according to an embodiment of the present disclosure. The process of obtaining the operating voltage of the light-emitting element 10 will be described below in conjunction with the pixel circuit shown in FIG. 4 and the timing control signal shown in FIG. 5.
  • the first scan signal G and the second control signal EM are at low level VGL, and the second scan signal S, reset signal R and the first control signal SEN are at high level. Ping VGH. Therefore, the third transistor T3 and the sixth transistor T6 are turned on, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off.
  • sense voltage V sense through the third transistor to the data line DL is applied to the first transfer transistor T3 of the control terminal and a second terminal of the capacitor C st T1.
  • the first transistor T1 is turned on under the control of the sense voltage V sense, thereby generating a sense current I s.
  • the sensing current I s can be expressed as the following formula:
  • ⁇ is the carrier mobility of the first transistor T1
  • C OX is the capacitance of the gate dielectric layer of the first transistor T1
  • W/L is the aspect ratio of the channel of the first transistor T1
  • V TH is the threshold voltage of the first transistor T1.
  • the sensing voltage V sense may be the sum of the initial voltage V s and the first compensation voltage f1 (V TH ).
  • the first compensation voltage f1 (V TH ) is equal to the threshold voltage V TH of the first transistor T1.
  • the sensing current I s can be expressed as the following formula:
  • the sensing current I s of the first transistor T1 in different pixel circuits may be the same.
  • the initial voltage V s can be set according to actual conditions.
  • the value of the initial voltage V s can be set according to the desired sensing current I s .
  • the threshold voltage V TH of the first transistor T1 can be obtained by, but not limited to, the method described later.
  • the first scan signal G becomes a high level VGH
  • the reset signal R and the second scan signal S become a low level VGL
  • the levels of other signals are the same as in the S1 stage. Therefore, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned on, and the third transistor T3 and the fifth transistor T5 are turned off. Further, since the sense voltage V sense is in the capacitor C st, the first transistor T1 therefore remains in the conducting state voltage V sense of the control data stored to continuously output sense current I s.
  • the potential of the data line DL is reset to the first initial potential V ini1 so that the light-emitting element 10 does not emit light.
  • the first initial value may be provided by the potential V ini1 such that potential difference between the first and the second initial potential V ini1 ELV SS terminal voltage is less than the operating voltage of the light emitting element 10 such that the light emitting element 10 does not emit light. Further, since the light emitting element 10 does not emit light, so that the first transistor T1 is generated by a sense current I s flows to the data line DL.
  • the reset signal R becomes the high level VGH, and the levels of other signals are the same as the T12 stage. Therefore, the second transistor T2 and the sixth transistor T6 are turned on, and the third transistor T3, the fourth transistor T4 and the fifth transistor T5 are turned off. T12 identical stages, the first transistor T1 is kept turned-on state under the control of the sense voltage V sense to continuously output sense current I s.
  • the sensing current I s output by the first transistor T1 will flow to the data line DL, thereby charging the data line DL. It should be understood that there is a distributed capacitance C data between the data line DL and other lines (such as data lines, scan lines, etc.).
  • the potential on the data line DL starts to rise from the first initial potential V ini1 and rises to the first fixed potential V1 after a period of time, at which time the light emitting element 10 starts to emit light.
  • the potential on the data line DL stabilizes at the first fixed potential V1.
  • the source driver reads the potential on the data line DL in response to the sampling signal SMPL from the low level VGL to the high level VGH, thereby obtaining the first fixed potential V1. It should be understood that, in some embodiments, the source driver can also read the potential on the data line DL in response to the sampling signal SMPL changing from the high level VGH to the low level VGL.
  • the potential difference between the first fixed potential V1 and the second voltage terminal ELV SS can be calculated to obtain the operating voltage V OLED of the light-emitting element 10.
  • FIG. 6 is a timing control signal diagram of a pixel circuit according to another embodiment of the present disclosure. The process of obtaining the threshold voltage of the first transistor T1 will be described below in conjunction with the pixel circuit shown in FIG. 4 and the timing control signal shown in FIG. 6.
  • the first scan signal G, the second scan signal S, the reset signal R, and the first control signal SEN are at low level VGL, and the second control signal EM is at high level. Ping VGH. Therefore, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, and the sixth transistor T6 is turned off.
  • the potential of the data line DL is reset to the second initial potential V ini2 at which the first transistor T1 is turned on.
  • the second initial potential V ini2 third transistor T3 is written to a second terminal of the first transistor and the control terminal of the capacitor C st via T1. It should be understood, the value provided by the second initial potential V ini2 such that the potential difference between the second initial potential V ini2 ELV DD and the first voltage terminal is less than the threshold voltage V TH of the first transistor T1, so that the first transistor T1 Conduction.
  • the reset signal R becomes the high level VGH, and the levels of other signals are the same as the T21 stage. Therefore, the second transistor T2, the third transistor T3, and the fifth transistor T5 are turned on, and the fourth transistor T4 and the sixth transistor T6 are turned off.
  • the current output by the first transistor T1 will flow to the data line DL, thereby charging the data line DL. Charging the data line DL to the capacitor C st through the third transistor T3, the potential of the control terminal of the first transistor T1 begins to rise from the second initial potential V ini2, after a period of time to rise to a second fixed potential V2, the first transistor T1 at this time Deadline.
  • the potential on the data line DL stabilizes at the second fixed potential V2.
  • the absolute value of the difference between the second fixed potential V2 and the potential of the first voltage terminal ELV DD is equal to the absolute value of the threshold voltage V TH of the first transistor T1
  • the source driver reads the potential on the data line DL in response to the sampling signal SMPL from the low level VGL to the high level VGH, thereby obtaining the second fixed potential V2.
  • the source driver can also read the potential on the data line DL in response to the sampling signal SMPL from the high level VGH to the low level VGL, thereby obtaining the second fixed potential V2.
  • the difference between the second fixed potential V2 and the potential of the first voltage terminal ELV DD can be calculated to obtain the threshold voltage V TH of the first transistor T1.
  • FIG. 7 is a timing control signal diagram of a pixel circuit according to another embodiment of the present disclosure. The process of driving the pixel circuit for display will be described below in combination with the pixel circuit shown in FIG. 4 and the timing control signal shown in FIG. 7.
  • the first scan signal G and the second control signal EM are at a low level VGL
  • the second scan signal S, the reset signal R and the first control signal SEN are at a high level VGH. Therefore, the third transistor T3 and the sixth transistor T6 are turned on, and the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are turned off.
  • a data voltage V data on the data line DL is written to the control terminal of the first transistor and a second terminal of the capacitor C st through the third transistor T1 is T3.
  • the first transistor T1 is turned on under the control of the data voltage V data , thereby driving the light emitting element 10 to emit light.
  • the value of the data voltage V data can be adjusted according to the operating voltage V OLED of the light-emitting element and the threshold voltage V TH of the first transistor T1 obtained previously.
  • the data voltage V data is the compensated data voltage
  • the compensated data voltage is the sum of the original data voltage V pixel, the first compensation voltage f1 (V TH ) and the second compensation voltage f2 (V OLED ) to reduce the There is a problem of uneven display brightness caused by the decrease in the luminous efficiency of the light-emitting element 10 and the difference in the threshold voltage V TH of the first transistor T1.
  • the first compensation voltage f1 (V TH ) is a compensation voltage related to the threshold voltage V TH of the first transistor T1
  • the second compensation voltage f2 (V OLED ) is a compensation voltage related to the operating voltage V OLED of the light-emitting element 10 .
  • FIG. 8 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.
  • the display device includes a plurality of pixel units 801 (for example, FIG. 8 shows n (row) ⁇ m (column) pixel units 801).
  • Each pixel unit 801 includes the pixel circuit of any one of the above embodiments, such as the pixel circuit shown in FIG. 1, FIG. 3, or FIG.
  • the display device may be, for example, any product or component with a display function, such as a display panel, a mobile terminal, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and electronic paper.
  • the display device further includes a plurality of first scan lines, such as first scan line G1, first scan line G2... first scan line Gn.
  • Each first scan line is electrically connected to the pixel circuits in the pixel unit 801 in the same row.
  • the first scan line G1 is electrically connected to the pixel circuits in the first row of pixel units 801
  • the first scan line G2 is electrically connected to the pixel circuits in the second row of pixel units 801, and so on.
  • the display device further includes a plurality of second scan lines, such as a second scan line S1, a second scan line S2...the second scan line Sn.
  • Each second scan line is electrically connected to the pixel circuits in the pixel unit 801 in the same row.
  • the second scan line S1 is electrically connected to the pixel circuits in the first row of pixel units 801
  • the second scan line S2 is electrically connected to the pixel circuits in the second row of pixel units 801, and so on.
  • the display device further includes a plurality of data lines electrically connected to the source driver 802, for example, data lines DL1, data lines DL2...data lines DLm.
  • Each data line DL is electrically connected to the pixel circuit in the pixel unit 801 in the same column.
  • the data line DL1 is electrically connected to the pixel circuits in the first column of pixel units 801
  • the data line DL2 is electrically connected to the pixel circuits in the second column of pixel units 801, and so on.
  • a plurality of pixel units 801, a plurality of first scan lines, a plurality of second scan lines, and a plurality of data lines are arranged in the display area of the display device.
  • the plurality of first scan lines and the plurality of second scan lines may be electrically connected to the gate driver.
  • the display device further includes a plurality of reset circuits 50 arranged in the non-display area or source driver 802 of the display device.
  • a plurality of reset circuits 50 may be electrically connected to the same reset line Rn.
  • Each reset circuit 50 is electrically connected to a corresponding data line, that is, multiple reset circuits 50 correspond to multiple data lines one-to-one.
  • Each reset circuit 50 is configured to, in response to the reset signal R, reset the potential of the corresponding data line to a first initial potential V ini1 (for example, in the fourth non-display period t4) and a second initial potential V ini2 (for example, in the The fifth non-display stage t5).
  • the first initial potential Vini1 makes the light emitting element 10 in each pixel unit 801 electrically connected to the data line not emit light.
  • the reset circuit 50 electrically connected to the data line DL1 resets the potential of the data line DL1 to a first initial potential V ini1 at which the light-emitting elements in the first column of pixel units 801 electrically connected to the data line DL1 do not emit light
  • the data The reset circuit 50 electrically connected to the line DL2 resets the potential of the data line DL2 to the first initial potential V ini1 at which the light-emitting elements in the second column of pixel units 801 electrically connected to the data line DL2 do not emit light, and so on.
  • the second initial potential V ini2 turns on the first transistor T1 in each pixel unit 801 electrically connected to the data line.
  • the reset circuit 50 electrically connected to the data line DL1 resets the potential of the data line DL1 to a second initial potential V ini2 that turns on the first transistor T1 in the first column of pixel cells 801 electrically connected to the data line DL1
  • the reset circuit 50 electrically connected to the data line DL2 resets the potential of the data line DL2 to the second initial potential V ini2 that turns on the first transistor T1 in the second column of pixel units 801 electrically connected to the data line DL2, thereby analogy.
  • the structure of the reset circuit 50 may refer to the structure of the reset circuit 50 shown in FIG. 4, for example.
  • Each reset circuit 50 may include a fourth transistor T4.
  • the control terminal of the fourth transistor T4 is configured to receive the reset signal R, the first terminal of the fourth transistor T4 is electrically connected to the corresponding data line, and the second terminal of the fourth transistor T4 is electrically connected to the third voltage terminal V ini .
  • the display device further includes a control circuit 60 provided in the non-display area of the display device or the power supply of the display device.
  • the control circuit 60 is electrically connected to the cathode of the light-emitting element 10 in each pixel unit 801.
  • the control circuit 60 is configured to respond to at least one control signal so that the cathode of the light-emitting element 10 in each pixel unit 801 is electrically connected to the second voltage terminal ELV SS or the fourth voltage terminal ELV DD′ .
  • control circuit 60 causes the cathode of the light emitting element 10 in each pixel unit 801 to be electrically connected to the second voltage terminal ELV SS in the first stage M1, and electrically connected to the fourth voltage terminal ELV DD' in the second stage M2.
  • the structure of the control circuit 60 may refer to the structure of the control circuit 60 shown in FIG. 4, for example.
  • the at least one control signal may include a first control signal SEN and a second control signal EM.
  • the control circuit includes a fifth transistor T5 and a sixth transistor T6.
  • the control terminal of the fifth transistor T5 is configured to receive the first control signal SEN, the first terminal of the fifth transistor T5 is electrically connected to the cathode of the light emitting element 10 in each pixel unit 801, and the second terminal of the fifth transistor T5 is connected to The fourth voltage terminal ELV DD' is electrically connected.
  • the control terminal of the sixth transistor T6 is configured to receive the second control signal EM, the first terminal of the sixth transistor T6 is electrically connected to the cathode of the light emitting element 10 in each pixel unit 801, and the second terminal of the sixth transistor T6 is connected to The second voltage terminal ELV SS is electrically connected.
  • the sensing of the operating voltage of the light-emitting element in each pixel unit can be realized row by row before the display stage of each display period, and each pixel can be driven row by row during the display stage of each display period.
  • the light-emitting elements in the cells emit light, and after the display stage of each display period, the threshold voltage of the first transistor in each pixel unit can be sensed line by line.

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Abstract

一种像素电路及其驱动方法、显示装置，像素电路包括：发光元件（10），包括阳极和阴极；第一开关电路（20）响应于来自第一扫描线的第一扫描信号（G），在导通的情况下传输来自数据线（DL）的电压；驱动电路（30），包括：第一晶体管（T1），第一晶体管（T1）的控制端与第一开关电路（20）电连接、第一端与第一电压端（ELVDD）电连接、第二端与发光元件（10）的阳极电连接；和电容器（Cst），电容器（Cst）的第一端与第一电压端（ELVDD）电连接、第二端与第一开关电路（20）电连接；和第二开关电路（40），被配置为响应于来自第二扫描线的第二扫描信号（S），在导通的情况下使数据线（DL）上的电位分别稳定在第一固定电位（V1）、第二固定电位（V2），第一固定电位（V1）使得发光元件（10）发光，第二固定电位（V2）使得第一晶体管（T1）截止。

Description

像素电路及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及像素电路及其驱动方法、显示装置。
背景技术
由于制造工艺或晶体管自身特性等原因，OLED(Organic Light Emitting Diode，有机发光二极管)显示面板不同像素中驱动晶体管的阈值电压在同一时刻下可能不同。另外，同一像素中驱动晶体管的阈值电压在不同时刻下也可能不同，即驱动晶体管的阈值电压存在漂移现象。
因此，即使在同一灰阶下，由于驱动晶体管的阈值电压存在差异，不同像素中驱动OLED的驱动电流也会存在差异。这导致不同像素的显示亮度不同，从而导致显示面板的显示亮度不均匀。
发明内容
根据本公开实施例的一方面，提供一种像素电路，包括：发光元件，包括阳极和阴极；第一开关电路，被配置为响应于来自第一扫描线的第一扫描信号，在导通的情况下传输来自数据线的电压；驱动电路，被配置为在所述第一开关电路传输的电压的控制下驱动所述发光元件发光，所述驱动电路包括：第一晶体管，所述第一晶体管的控制端被配置为与所述第一开关电路电连接，所述第一晶体管的第一端与第一电压端电连接，所述第一晶体管的第二端与所述发光元件的阳极电连接；和电容器，所述电容器的第一端与所述第一电压端电连接，所述电容器的第二端与所述第一开关电路电连接；和第二开关电路，与所述数据线、所述第一晶体管的第二端和所述发光元件的阳极电连接，被配置为响应于来自第二扫描线的第二扫描信号，在导通的情况下使所述数据线上的电位分别稳定在第一固定电位和第二固定电位，所述第一固定电位使得所述发光元件发光，所述第二固定电位使得所述第一晶体管截止。
在一些实施例中，所述第二开关电路包括第二晶体管，所述第二晶体管的控制端被配置为接收所述第二扫描信号，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第二端与所述发光元件的阳极电连接。
在一些实施例中，所述数据线与复位电路电连接，所述数据线的电位被所述复位 电路分别复位到第一初始电位和第二初始电位，所述第一初始电位使得所述发光元件不发光，所述第二初始电位使得所述第一晶体管导通。
在一些实施例中，所述发光元件的阴极与控制电路电连接，在所述控制电路的控制下，所述发光元件的阴极与第二电压端或第四电压端电连接；其中，所述第二电压端的电位使得所述发光元件处于正向偏置，所述第四电压端的电位使得所述发光元件处于反向偏置。
在一些实施例中，所述第一开关电路包括第三晶体管，所述第三晶体管的控制端被配置为接收所述第一扫描信号，所述第三晶体管的第一端与所述数据线电连接，所述第三晶体管的第二端与所述电容器的第二端和所述第一晶体管的控制端电连接。
根据本公开实施例的另一方面，提供一种显示装置，包括多个像素单元，每个像素单元包括上述任意一个实施例所述的像素电路。
在一些实施例中，所述显示装置还包括：多条第一扫描线，每条第一扫描线与同一行像素单元中的像素电路电连接；多条第二扫描线，每条第二扫描线与同一行像素单元中的像素电路电连接；和多条数据线，每条数据线与同一列像素单元中的像素电路电连接。
在一些实施例中，所述显示装置还包括：多个复位电路，设置在所述显示装置的非显示区或源极驱动器中，每个复位电路与一条对应的数据线电连接，每个复位电路被配置为响应于复位信号，将对应的数据线的电位分别复位到第一初始电位和第二初始电位，所述第一初始电位使得与该条数据线电连接的每个像素单元中的发光元件不发光，所述第二初始电位使得与该条数据线电连接的每个像素单元中的第一晶体管导通。
在一些实施例中，每个复位电路包括第四晶体管，所述第四晶体管的控制端被配置为接收所述复位信号，所述第四晶体管的第一端与对应的数据线电连接，所述第四晶体管的第二端与第三电压端电连接。
在一些实施例中，所述显示装置还包括：控制电路，设置在所述显示装置的非显示区或所述显示装置的电源中，所述控制电路与每个像素单元中的发光元件的阴极电连接；所述控制电路被配置为响应于至少一个控制信号，使得每个像素单元中的发光元件的阴极与第二电压端或第四电压端电连接，其中，所述第二电压端的电位使得所述发光元件处于正向偏置，所述第四电压端的电位使得所述发光元件处于反向偏置。
在一些实施例中，所述至少一个控制信号包括第一控制信号和第二控制信号；所 述控制电路包括：第五晶体管，所述第五晶体管的控制端被配置为接收所述第一控制信号，所述第五晶体管的第一端与每个像素单元中的发光元件的阴极电连接，所述第五晶体管的第二端与所述第四电压端电连接；和第六晶体管，所述第六晶体管的控制端被配置为接收所述第二控制信号，所述第六晶体管的第一端与每个像素单元中的发光元件的阴极电连接，所述第六晶体管的第二端与所述第二电压端电连接。
根据本公开实施例的又一方面，提供一种如上述任意一个实施例所述的像素电路的驱动方法，包括：在第一阶段，使数据线上的电位稳定在使得发光元件发光的第一固定电位；在第二阶段，使所述数据线上的电位稳定在使得第一晶体管截止的第二固定电位；在显示阶段，向所述数据线提供补偿后的数据电压，以驱动所述发光元件发光，其中，补偿后的数据电压根据所述第一固定电位和所述第二固定电位来确定。
在一些实施例中，所述第一阶段包括第一非显示阶段和在所述第一非显示阶段之后的第二非显示阶段；在所述第一非显示阶段，第一开关电路响应于来自第一扫描线的第一扫描信号导通以将来自数据线的感测电压传输至所述电容器的第二端和所述第一晶体管的控制端，所述第一晶体管在所述感测电压的控制下导通以产生感测电流，第二开关电路响应于来自第二扫描线的第二扫描信号不导通；在所述第二非显示阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通以使得所述感测电流对所述数据线充电，从而使得所述数据线上的电位稳定在使得发光元件发光的第一固定电位。
在一些实施例中，所述第二阶段包括第三非显示阶段；在所述第三非显示阶段，所述第二开关电路响应于所述第二扫描信号导通以向所述数据线充电，所述第一开关电路响应于所述第一扫描信号导通以使得所述数据线对电容器进行充电，从而使得所述数据线上的电位稳定在使得第一晶体管截止的第二固定电位。
在一些实施例中，所述第一阶段还包括位于所述第一非显示阶段和所述第二非显示阶段之间的第四非显示阶段；在所述第四非显示阶段，将所述数据线的电位复位到使得所述发光元件不发光的第一初始电位，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通。
在一些实施例中，所述第二阶段还包括在所述第三非显示阶段之前的第五非显示阶段；在所述第五非显示阶段，将所述数据线的电位复位到使得所述第一晶体管导通的第二初始电位，所述第一开关电路响应于所述第一扫描信号导通，所述第二开关电路响应于所述第二扫描信号导通。
在一些实施例中，所述第一阶段还包括在所述第二非显示阶段之后的第六非显示阶段；在所述第六非显示阶段，源极驱动器从所述数据线读取所述第一固定电位。
在一些实施例中，所述第二阶段还包括在所述第三非显示阶段之后的第七非显示阶段；在所述第七非显示阶段，源极驱动器从所述数据线读取所述第二固定电位。
在一些实施例中，所述像素电路所在的显示面板的开机时刻与所述显示面板的关机时刻之间为一个显示周期；在同一显示周期内，所述第一阶段位于所述显示面板的开机时刻与所述显示阶段的开始时刻之间，所述第二阶段位于所述显示阶段的结束时刻与所述显示面板的关机时刻之间。
在一些实施例中，在所述显示阶段，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的补偿后的数据电压传输至所述电容器的第二端和所述第一晶体管的控制端，所述第一晶体管在补偿后的数据电压的控制下导通以产生用于驱动所述发光元件发光的驱动电流，所述第二开关电路响应于所述第二扫描信号不导通；其中，补偿后的数据电压为补偿前的数据电压、第一补偿电压和第二补偿电压之和，所述第一补偿电压根据所述第一晶体管的阈值电压来确定，所述第二补偿电压根据所述发光元件的工作电压来确定，所述第一晶体管的阈值电压根据当前显示周期的上一个显示周期的第二固定电位来确定，所述发光元件的工作电压根据当前显示周期的第一固定电位来确定。
附图说明
构成说明书的一部分的附图描述了本公开的实施例，并且连同说明书一起用于解释本公开的原理。
参照附图，根据下面的详细描述，可以更加清楚地理解本公开，其中：
图1是根据本公开一个实施例的像素电路的结构示意图；
图2是根据本公开一个实施例的像素电路的驱动方法的流程示意图；
图3是根据本公开一个实施例的一个显示周期的示意图；
图4是根据本公开另一个实施例的像素电路的结构示意图；
图5是根据本公开一个实施例的像素电路的时序控制信号图；
图6是根据本公开另一个实施例的像素电路时序控制信号图；
图7是根据本公开又一个实施例的像素电路时序控制信号图；
图8是根据本公开一个实施例的显示装置的结构示意图。
应当明白，附图中所示出的各个部分的尺寸并不必然是按照实际的比例关系绘制的。此外，相同或类似的参考标号表示相同或类似的构件。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。对示例性实施例的描述仅仅是说明性的，决不作为对本公开及其应用或使用的任何限制。本公开可以以许多不同的形式实现，不限于这里所述的实施例。提供这些实施例是为了使本公开透彻且完整，并且向本领域技术人员充分表达本公开的范围。应注意到：除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、材料的组分、数字表达式和数值应被解释为仅仅是示例性的，而不是作为限制。
本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的部分。“包括”或者“包含”等类似的词语意指在该词前的要素涵盖在该词后列举的要素，并不排除也涵盖其他要素的可能。“上”、“下”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在本公开中，当描述到特定部件位于第一部件和第二部件之间时，在该特定部件与第一部件或第二部件之间可以存在居间部件，也可以不存在居间部件。当描述到特定部件连接其它部件时，该特定部件可以与所述其它部件直接连接而不具有居间部件，也可以不与所述其它部件直接连接而具有居间部件。
本公开使用的所有术语(包括技术术语或者科学术语)与本公开所属领域的普通技术人员理解的含义相同，除非另外特别定义。还应当理解，在诸如通用字典中定义的术语应当被解释为具有与它们在相关技术的上下文中的含义相一致的含义，而不应用理想化或极度形式化的意义来解释，除非这里明确地这样定义。
对于相关领域普通技术人员已知的技术、方法和设备可能不作详细讨论，但在适当情况下，所述技术、方法和设备应当被视为说明书的一部分。
发明人注意到，像素中发光元件的发光效率随着工作时间的增加会下降，导致像素的显示亮度会下降。例如，如果某个区域的像素比其他区域的像素发光时间更长或亮度更高，容易使得这个区域的像素的发光效率下降，从而使得这个区域的像素的显示亮度偏低，导致显示亮度不均匀，出现残留影像的现象。
图1是根据本公开一个实施例的像素电路的结构示意图。
如图1所示，像素电路包括发光元件10、第一开关电路20、驱动电路30和第二开关电路40。
发光元件10包括阳极和阴极。在一些实施例中，发光元件10例如可以是OLED等。发光元件10的阳极与驱动电路30和第二开关电路40电连接，发光元件10的阴极例如可以在控制电路60的控制下与第二电压端ELV SS或第四电压端ELV DD’电连接。第二电压端ELV SS的电位使得发光元件10处于正向偏置，第四电压端ELV DD’的电位使得发光元件10处于反向偏置。
第一开关电路20电连接在数据线DL与驱动电路30之间。第一开关电路20被配置为响应于来自第一扫描线的第一扫描信号G，在导通的情况下传输来自数据线DL的电压至驱动电路30。
驱动电路30被配置为在第一开关电路20传输的电压的控制下驱动发光元件10发光。参见图1，驱动电路30包括第一晶体管T1(即驱动晶体管)和电容器C st。第一晶体管T1的控制端与第一开关电路20电连接，第一晶体管T1的第一端与第一电压端ELV DD电连接，第一晶体管T1的第二端与发光元件10的阳极电连接。电容器C st的第一端与第一电压端ELV DD电连接，电容器C st的第二端与第一开关电路20和第一晶体管T1的控制端电连接。
第二开关电路40与数据线DL、第一晶体管T1的第二端和发光元件10的阳极电连接。第二开关电路40被配置为响应于来自第二扫描线的第二扫描信号S，在导通的情况下使数据线DL上的电位分别稳定在第一固定电位和第二固定电位。这里，第一固定电位使得发光元件10发光，第二固定电位使得第一晶体管T1截止。数据线DL上的电位可以在不同的阶段被分别稳定在第一固定电位和第二固定电位，后文将结合驱动方法进行说明。
应理解，第一固定电位为发光元件10的阴极的电位与发光元件10的工作电压V OLED之和。因此，在数据线DL上的电位稳定在第一固定电位后，可以读取数据线DL上的第一固定电位，进而可以得到发光元件10的工作电压V OLED。例如，提供数据电压的源极驱动器可以读取数据线DL上的第一固定电位，并存储发光元件10的工作电压V OLED。
在显示阶段，源极驱动器向数据线DL提供的数据电压V data可以为原始数据电压V pixel与第二补偿电压f2(V OLED)之和，以对发光元件10的发光效率进行补偿。这里，第二补偿电压f2(V OLED)根据发光元件10的工作电压V OLED来确定。应明白，可以 通过发光元件的工作电压和发光效率的之间的补偿模型确定发光元件10的工作电压V OLED对应的发光效率，进而可以确定为了弥补发光元件10的发光效率的降低需要的补偿电压，即第二补偿电压f2(V OLED)。
还应理解，第二固定电位为第一电压端ELV DD的电位与第一晶体管T1的阈值电压V TH之和。因此，在数据线DL上的电位稳定在第二固定电位后，可以读取数据线DL上的第二固定电位，从而可以得到第一晶体管T1的阈值电压V TH。例如，提供数据电压的源极驱动器可以读取数据线DL上的第二固定电位，并存储第一晶体管T1的阈值电压V TH。
在显示阶段，源极驱动器向数据线DL提供的数据电压V data可以为原始数据电压V pixel与第一补偿电压f1(V TH)之和，以对第一晶体管T1的阈值电压V TH进行补偿，从而减轻由于第一晶体管T1的阈值电压V TH的差异导致的显示亮度不均匀的问题。这里，第一补偿电压f1(V TH)根据第一晶体管T1的阈值电压V TH来确定。例如，第一补偿电压f1(V TH)可以等于阈值电压V TH。又例如，第一补偿电压f1(V TH)可以为阈值电压V TH与其他值之和或之差。这里，其他值例如可以是不同像素中第一晶体管T1的阈值电压V TH的平均值。
上述实施例中，第二开关电路在导通的情况下可以使数据线上的电位分别稳定在第一固定电位和第二固定电位。根据第一固定电位可以得到发光元件的工作电压，根据第二固定电位可以得到第一晶体管的阈值电压。进而，可以以外部补偿的方式对发光元件的发光效率和第一晶体管的阈值电压进行补偿，以减轻由于发光元件的发光效率的下降和第一晶体管的阈值电压的差异导致的显示亮度不均匀的问题。
在一些实施例中，如图1所示，数据线DL与复位电路50电连接。数据线DL的电位被复位电路50分别复位到第一初始电位V ini1和第二初始电位V ini2。第一初始电位V ini1使得发光元件10不发光，第二初始电位V ini2使得第一晶体管T1导通。应理解，第一初始电位V ini1与发光元件10的阴极的电位之差小于发光元件10的工作电压V OLED，故发光元件10不发光。在一些实施例中，第一初始电位V ini1与第二初始电位V ini2可以相同。在另一些实施例中，第一初始电位V ini1与第二初始电位V ini2也可以不同。
上述实施例中，数据线上的电位在被稳定在使得发光元件发光的第一固定电位之前，可以先被复位到使得发光元件不发光的第一初始电位。另外，在被稳定在使得第一晶体管截止的第二固定电位之前，可以先被复位到使得第一晶体管导通的第二初始 电位。这样的方式可以减小数据线的电位在稳定在第一固定电位之前的电位波动对第一固定电位的影响，使得第一固定电位更为准确，从而使得最终得到的发光元件的工作电压V OLED更为准确。另外，还可以减小数据线的电位在稳定在第二固定电位之前的电位波动对第二固定电位的影响，使得第二固定电位更为准确，从而使得最终得到的第一晶体管的阈值电压V TH更为准确。
在一些实施例中，如图1所示，发光元件10的阴极可以与控制电路60电连接。在控制电路60的控制下，发光元件10的阴极与第二电压端ELV SS或第四电压端ELV DD’电连接。这里，第二电压端ELV SS的电位使得发光元件10处于正向偏置，第四电压端ELV DD’的电位使得发光元件10处于反向偏置。在一些实施例中，第四电压端ELV DD’的电位与第一电压端ELV DD的电位可以相同，以减少电源端的数量。
应理解，在发光元件10的阴极连接到第二电压端ELV SS的情况下，发光元件10处于正向偏置状态，故在满足条件的情况下可以发光；而在发光元件10的阴极连接到第四电压端ELV DD’的情况下，发光元件10处于反向偏置状态，故不会发光。
图2是根据本公开一个实施例的像素电路的驱动方法的流程示意图。图3是根据本公开一个实施例的一个显示周期的示意图。在图3中，像素电路所在的显示面板的开机时刻与显示面板的关机时刻之间为一个显示周期。
下面结合图2和图3对像素电路的驱动方法进行说明。
在步骤202，在第一阶段M1，使数据线DL上的电位稳定在使得发光元件10发光的第一固定电位。
在一些实施例中，参见图3，第一阶段M1可以位于显示面板的开机时刻与显示阶段的开始时刻(即显示面板开始显示画面的时刻)之间。在显示阶段之前，发光元件10不发光，发光元件10的工作电压受发光元件10的结温的影响较小，此时得到的第一固定电位更准确，从而使最终得到的发光元件10的工作电压V OLED更为准确。
在步骤204，在第二阶段M2，使数据线DL上的电位稳定在使得第一晶体管T1截止的第二固定电位。
在一些实施例中，第二阶段M2可以位于显示阶段的结束时刻(即显示面板结束显示画面的时刻)与显示面板的关机时刻之间。由于已经经过显示阶段，第一晶体管T1的结温处于稳定状态，减小了阈值电压V TH受第一晶体管T1的结温的影响。这种情况下得到的第二固定电位更准确，从而使得到的阈值电压V TH更接近第一晶体管T1工作时的电压，更为准确。
应理解，图3示出的显示周期仅为一个示例。在某些实施例中，在同一显示周期内，第一阶段M1和第二阶段M2可以均位于显示面板的开机时刻与显示阶段的开始时刻之间，或者，可以均位于显示阶段的结束时刻与显示面板的关机时刻之间。
在步骤206，在显示阶段，向数据线DL提供补偿后的数据电压，以驱动发光元件10发光。这里，补偿后的数据电压根据第一固定电位和第二固定电位来确定。
在一些实施例中，在显示阶段，第一开关电路20响应于第一扫描信号G导通，以将来自数据线DL的补偿后的数据电压传输至电容器C st的第二端和第一晶体管T1的控制端。第一晶体管T1在补偿后的数据电压的控制下导通以产生用于驱动发光元件10发光的驱动电流。另外，在显示阶段，第二开关电路40响应于第二扫描信号S不导通。
这里，补偿后的数据电压为补偿前的数据电压(也可以称为原始数据电压V pixel)、第一补偿电压f1(V TH)和第二补偿电压f2(V OLED)之和。第一补偿电压f1(V TH)根据第一晶体管T1的阈值电压V TH来确定。第二补偿电压f2(V OLED)根据发光元件10的工作电压V OLED来确定。在一些实施例中，发光元件10的工作电压可以根据当前显示周期的第一固定电位V1来确定，第一晶体管T1的阈值电压V TH可以根据当前显示周期的上一个显示周期的第二固定电位V2来确定。
这种情况下，补偿后的数据电压可以对发光元件10的发光效率和第一晶体管T1的阈值电压V TH进行补偿，以减轻由于发光元件10的发光效率的降低以及由于第一晶体管T1的阈值电压V TH的差异导致的显示亮度不均匀的问题。
下面结合图1和图3介绍根据本公开不同实施例的第一阶段M1。
在一些实施例中，参见图3，第一阶段M1可以包括第一非显示阶段t1和位于第一非显示阶段t1之后的第二非显示阶段t2。
在第一非显示阶段t1，第二开关电路40响应于来自第二扫描线的第二扫描信号S不导通；而第一开关电路20响应于来自第一扫描线的第一扫描信号G导通，以将来自数据线DL的感测电压传输至电容器C st的第二端和第一晶体管T1的控制端。第一晶体管T1在感测电压的控制下导通以产生感测电流。
在一些实现方式中，感测电压为初始电压与第一补偿电压f1(V TH)之和。第一补偿电压f1(V TH)根据第一晶体管T1的阈值电压V TH来确定。换言之，驱动电路30在第一非显示阶段t1接收的感测电压是对第一晶体管T1的阈值电压进行补偿后的电压，从而使得第一晶体管T1产生的感测电流为恒定的感测电流。这里，初始电压 被配置为使得第一晶体管T1产生感测电流。初始电压可以根据实际情况进行设置。例如，可以根据期望得到的感测电流设置初始电压的数值。
在第二非显示阶段T2，第一开关电路20响应于来自第一扫描线的第一扫描信号G不导通；而第二开关电路40响应于来自第二扫描线的第二扫描信号S导通，以使得第一晶体管T1产生的感测电流对数据线DL充电，从而使得数据线DL上的电位稳定在使得发光元件10发光的第一固定电位。
在另一些实施例中，参见图3，第一阶段M1还可以包括位于第一非显示阶段t1和第二非显示阶段t2之间的第四非显示阶段t4。在第四非显示阶段t4，将数据线DL的电位复位到使得发光元件10不发光的第一初始电位。这里，在第四非显示阶段t4，第一开关电路20响应于第一扫描信号G不导通，第二开关电路40响应于第二扫描信号S导通。
上述实施例中，数据线DL上的电位在第二非显示阶段t2被稳定在使得发光元件10发光的第一固定电位之前，先在第四非显示阶段t4被复位到使得发光元件10不发光的第一初始电位。这样的方式可以减小数据线DL的电位在稳定在第一固定电位之前的电位波动对第一固定电位的影响，使得第一固定电位更为准确，从而使得最终得到的发光元件的工作电压V OLED更为准确。
在又一些实施例中，参见图3，第一阶段M1还包括在第二非显示阶段t2之后的第六非显示阶段t6。在第六非显示阶段t6，源极驱动器从数据线DL读取第一固定电位。
下面结合图3介绍根据本公开不同实施例的第二阶段M2。
在一些实施例中，参见图3，第二阶段M2可以包括第三非显示阶段t3。
在第三非显示阶段t3，第二开关电路40响应于第二扫描信号S导通以向数据线DL充电。另外，第一开关电路20响应于第一扫描信号G导通以使得数据线DL对电容器进行充电，从而使得数据线DL上的电位稳定在使得第一晶体管T1截止的第二固定电位。
在另一些实施例中，参见图3，第二阶段M2还可以包括在第三非显示阶段t3之前的第五非显示阶段t5。在第五非显示阶段t5，将数据线DL的电位复位到使得驱动电路中的第一晶体管T1导通的第二初始电位。这里，在第五非显示阶段t5，第一开关电路20响应于第一扫描信号G导通，第二开关电路40响应于第二扫描信号S导通。
上述实施例中，数据线DL上的电位在被稳定在使得第一晶体管T1截止的第二 固定电位之前，先被复位到使得第一晶体管T1导通的第二初始电位。这样的方式可以减小数据线DL的电位在稳定在第二固定电位之前的电位波动对第二固定电位的影响，使得第二固定电位更为准确，从而使得最终得到的第一晶体管T1的阈值电压V TH更为准确。
在又一些实施例中，参见图3，第二阶段M2还可以包括在第三非显示阶段t3之后的第七非显示阶段t7。在第七非显示阶段t7，源极驱动器从数据线DL读取第二固定电位。
图4是根据本公开又一个实施例的像素电路的结构示意图。下面结合图4介绍像素电路中的各电路、以及复位电路和控制电路的具体实现方式。应理解，虽然图4中的像素电路示出了每个电路的具体实现方式，但是，在某些实施例中，一个或多个电路并不限于图4所示的实现方式。
在一些实现方式中，第二开关电路40包括第二晶体管T2。第二晶体管T2的控制端被配置为接收第二扫描信号S，第二晶体管T2的第一端与数据线DL电连接，第二晶体管T2的第二端与发光元件10的阳极电连接。
在一些实现方式中，第一开关电路20包括第三晶体管T3。第三晶体管T3的控制端被配置为接收第一扫描信号G，第三晶体管T3的第一端与数据线DL电连接，第三晶体管T3的第二端与电容器C st的第二端和第一晶体管T1的控制端电连接。
在一些实现方式中，复位电路50包括第四晶体管T4。第四晶体管T4的控制端被配置为接收复位信号R，第四晶体管T4的第一端与数据线DL电连接，第四晶体管T4的第二端与第三电压端V ini电连接。
在一些实现方式中，控制电路60包括第五晶体管T5和第六晶体管T6。第五晶体管T5的控制端被配置为接收第一控制信号SEN，第五晶体管T5的第一端与发光元件10的阴极电连接，第五晶体管T5的第二端与第四电压端ELV DD’电连接。第六晶体管T6的控制端被配置为接收第二控制信号EM，第六晶体管T6的第一端与发光元件10的阴极电连接，第六晶体管T6的第二端与第二电压端ELV SS电连接。
上述实施例中，像素电路仅包括3个晶体管和一个电容器(即3T1C)。这样的像素电路结构简单，不仅能够实现对发光元件的工作电压和第一晶体管(即驱动晶体管)的阈值电压的感测，还有助于提高像素的开口率和显示面板的分辨率。
在一些实施例中，图4的像素电路中各晶体管可以均为P型薄膜晶体管(Thin Film Transistor，TFT)。在另一些实施例中，图4所示的像素电路中的第一晶体管T1可 以为P型晶体管，其他晶体管中的一部分晶体管可以为N型TFT，而剩余的晶体管可以为P型TFT。在一些实施例中，各晶体管的有源层可以包括但不限于低温多晶硅(Low Temperature Poly-silicon，LTPS)。
下面结合图5-图7对图4所示的像素电路的工作过程进行说明。在下面的说明中，假设图4所示的像素电路中的各晶体管均为P型TFT。
图5是根据本公开一个实施例的像素电路的时序控制信号图。下面结合图4所示的像素电路和图5所示的时序控制信号，对获得发光元件10的工作电压的过程进行说明。
如图5所示，在T11阶段(对应t1阶段)，第一扫描信号G和第二控制信号EM为低电平VGL，第二扫描信号S、复位信号R和第一控制信号SEN为高电平VGH。因此，第三晶体管T3和第六晶体管T6导通，第二晶体管T2、第四晶体管T4和第五晶体管T5截止。
另外，对数据线DL施加的感测电压V sense经第三晶体管T3传输至第一晶体管T1的控制端和电容器C st的第二端。第一晶体管T1在感测电压V sense的控制下导通，从而产生感测电流I s。感测电流I s可以表示为下式：
Figure PCTCN2019077927-appb-000001
在上式中，μ为第一晶体管T1的载流子迁移率，C OX为第一晶体管T1的栅极电介质层的电容，W/L为第一晶体管T1的沟道的宽长比，V TH为第一晶体管T1的阈值电压。
在一些实施例中，感测电压V sense可以为初始电压V s和第一补偿电压f1(V TH)之和。例如，第一补偿电压f1(V TH)等于第一晶体管T1的阈值电压V TH。这种情况下，感测电流I s可以表示为下式：
Figure PCTCN2019077927-appb-000002
可见，感测电流I s与第一晶体管T1的阈值电压V TH无关。这样，不同像素电路中的第一晶体管T1的感测电流I s可以相同。
初始电压V s可以根据实际情况进行设置。例如，可以根据期望得到的感测电流I s设置初始电压V s的数值。第一晶体管T1的阈值电压V TH可以但不限于通过后面介绍的方法来获得。
接下来，在T12阶段(对应t4阶段)，第一扫描信号G变为高电平VGH，复位信号R和第二扫描信号S变为低电平VGL，其他信号的电平与S1阶段相同。因此， 第二晶体管T2、第四晶体管T4和第六晶体管T6导通，第三晶体管T3和第五晶体管T5截止。另外，由于感测电压V sense被存储在电容器C st中，故第一晶体管T1在数据电压V sense的控制下保持导通状态，从而持续输出感测电流I s。
由于第四晶体管T4导通，故数据线DL的电位被复位至使得发光元件10不发光第一初始电位V ini1。应理解，可以通过设置第一初始电位V ini1的数值，使得第一初始电位V ini1与第二电压端ELV SS的电位之差小于发光元件10的工作电压，从而使得发光元件10不发光。另外，由于发光元件10不发光，故第一晶体管T1产生的感测电流I s会流向数据线DL。
接下来，在T13阶段(对应t2阶段)，复位信号R变为高电平VGH，其他信号的电平与T12阶段相同。因此，第二晶体管T2和第六晶体管T6导通，第三晶体管T3、第四晶体管T4和第五晶体管T5截止。与T12阶段相同，第一晶体管T1在感测电压V sense的控制下保持导通状态，从而持续输出感测电流I s。
第一晶体管T1输出的感测电流I s会流向数据线DL，从而对数据线DL进行充电。应理解，数据线DL与其他线(例如数据线、扫描线等)间存在分布电容C data。数据线DL上的电位从第一初始电位V ini1开始上升，经过一段时间后上升到第一固定电位V1，此时发光元件10开始发光。
接下来，在T14阶段(对应t6阶段)，数据线DL上的电位稳定在第一固定电位V1。源极驱动器响应于采样信号SMPL从低电平VGL变为高电平VGH，读取数据线DL上的电位，从而得到第一固定电位V1。应理解，在某些实施例中，源极驱动器也可以响应于采样信号SMPL从高电平VGH变为低电平VGL，读取数据线DL上的电位。在得到第一固定电位V1后，可以计算第一固定电位V1与第二电压端ELV SS的电位之差，从而得到发光元件10的工作电压V OLED。
图6是根据本公开另一个实施例的像素电路时序控制信号图。下面结合图4所示的像素电路和图6所示的时序控制信号，对获得第一晶体管T1的阈值电压的过程进行说明。
如图6所示，在T21(对应t5阶段)阶段，第一扫描信号G、第二扫描信号S、复位信号R和第一控制信号SEN为低电平VGL，第二控制信号EM为高电平VGH。因此，第二晶体管T2、第三晶体管T3、第四晶体管T4和第五晶体管T5导通，第六晶体管T6截止。
数据线DL的电位被复位至使得第一晶体管T1导通的第二初始电位V ini2。第二 初始电位V ini2经由第三晶体管T3被写入第一晶体管T1的控制端和电容器C st的第二端。应理解，可以通过设置第二初始电位V ini2的数值，使得第二初始电位V ini2与第一电压端ELV DD的电位之差小于第一晶体管T1的阈值电压V TH，从而使得第一晶体管T1导通。
接下来，在T22阶段(对应t3阶段)，复位信号R变为高电平VGH，其他信号的电平与T21阶段相同。因此，第二晶体管T2、第三晶体管T3和第五晶体管T5导通，第四晶体管T4和第六晶体管T6截止。
第一晶体管T1输出的电流会流向数据线DL，从而对数据线DL进行充电。数据线DL通过第三晶体管T3向电容器C st充电，第一晶体管T1的控制端的电位从第二初始电位V ini2开始上升，经过一段时间后上升到第二固定电位V2，此时第一晶体管T1截止。
接下来，在T23阶段(对应t7阶段)，数据线DL上的电位稳定在第二固定电位V2。第二固定电位V2与第一电压端ELV DD的电位之差的绝对值等于第一晶体管T1的阈值电压V TH的绝对值|V TH|。源极驱动器响应于采样信号SMPL从低电平VGL变为高电平VGH，读取数据线DL上的电位，从而得到第二固定电位V2。在某些实施例中，源极驱动器也可以响应于采样信号SMPL从高电平VGH变为低电平VGL，读取数据线DL上的电位，从而得到第二固定电位V2。在得到第二固定电位V2后，可以计算第二固定电位V2与第一电压端ELV DD的电位之差，从而得到第一晶体管T1的阈值电压V TH。
图7是根据本公开又一个实施例的像素电路时序控制信号图。下面结合图4所示的像素电路和图7所示的时序控制信号，对驱动像素电路进行显示的过程进行说明。
如图7所示，在显示阶段，第一扫描信号G和第二控制信号EM为低电平VGL，第二扫描信号S、复位信号R和第一控制信号SEN为高电平VGH。因此，第三晶体管T3和第六晶体管T6导通，第二晶体管T2、第四晶体管T4和第五晶体管T5截止。
数据线DL上的数据电压V data通过第三晶体管T3被写入到第一晶体管T1的控制端和电容器C st的第二端。第一晶体管T1在数据电压V data的控制下导通，从而驱动发光元件10发光。
在一些实施例中，可以根据之前得到的发光元件的工作电压V OLED和第一晶体管T1的阈值电压V TH调整数据电压V data的数值。例如，数据电压V data为补偿后的数据电压，补偿后的数据电压为原始数据电压V pixel与第一补偿电压f1(V TH)和第二补偿 电压f2(V OLED)之和，以减轻由于发光元件10的发光效率降低和第一晶体管T1的阈值电压V TH的差异导致的显示亮度不均匀的问题。这里，第一补偿电压f1(V TH)为与第一晶体管T1的阈值电压V TH相关的补偿电压，第二补偿电压f2(V OLED)为与发光元件10的工作电压V OLED相关的补偿电压。
图8是根据本公开一个实施例的显示装置的结构示意图。
如图8所示，显示装置包括多个像素单元801(例如，图8示出了n(行)×m(列)个像素单元801)。每个像素单元801包括上述任意一个实施例的像素电路，例如图1、图3或图4所示的像素电路。在一些实施例中，显示装置例如可以是显示面板、移动终端、电视机、显示器、笔记本电脑、数码相框、导航仪、电子纸等任何具有显示功能的产品或部件。
在一些实施例中，参见图8，显示装置还包括多条第一扫描线，例如第一扫描线G1、第一扫描线G2…第一扫描线Gn。每条第一扫描线与同一行像素单元801中的像素电路电连接。例如，第一扫描线G1与第一行像素单元801中的像素电路电连接，第一扫描线G2与第二行像素单元801中的像素电路电连接，以此类推。
在一些实施例中，参见图8，显示装置还包括多条第二扫描线，例如第二扫描线S1、第二扫描线S2…第二扫描线Sn。每条第二扫描线与同一行像素单元801中的像素电路电连接。例如，第二扫描线S1与第一行像素单元801中的像素电路电连接，第二扫描线S2与第二行像素单元801中的像素电路电连接，以此类推。
在一些实施例中，参见图8，显示装置还包括与源极驱动器802电连接的多条数据线，例如，数据线DL1、数据线DL2…数据线DLm。每条数据线DL与同一列像素单元801中的像素电路电连接。例如，数据线DL1与第一列像素单元801中的像素电路电连接，数据线DL2与第二列像素单元801中的像素电路电连接，以此类推。
应理解，多个像素单元801、多条第一扫描线、多条第二扫描线和多条数据线设置在显示装置的显示区。在一些实施例中，多条第一扫描线和多条第二扫描线可以与栅极驱动器电连接。
在一些实施例中，参见图8，显示装置还包括设置在显示装置的非显示区或源极驱动器802中的多个复位电路50。多个复位电路50可以与同一条复位线Rn电连接。每个复位电路50与一条对应的数据线电连接，即，多个复位电路50与多条数据线一一对应。每个复位电路50被配置为响应于复位信号R，将对应的数据线的电位分别复位到第一初始电位V ini1(例如在第四非显示阶段t4)和第二初始电位V ini2(例如在第 五非显示阶段t5)。
第一初始电位V ini1使得与该条数据线电连接的每个像素单元801中的发光元件10不发光。例如，与数据线DL1电连接的复位电路50将数据线DL1的电位复位到使得与数据线DL1电连接的第一列像素单元801中的发光元件不发光的第一初始电位V ini1，与数据线DL2电连接的复位电路50将数据线DL2的电位复位到使得与数据线DL2电连接的第二列像素单元801中的发光元件不发光的第一初始电位V ini1，以此类推。
第二初始电位V ini2使得与该条数据线电连接的每个像素单元801中的第一晶体管T1导通。例如，与数据线DL1电连接的复位电路50将数据线DL1的电位复位到使得与数据线DL1电连接的第一列像素单元801中的第一晶体管T1导通的第二初始电位V ini2，与数据线DL2电连接的复位电路50将数据线DL2的电位复位到使得与数据线DL2电连接的第二列像素单元801中的第一晶体管T1导通的第二初始电位V ini2，以此类推。
在一些实现方式中，复位电路50的结构例如可以参照图4所示的复位电路50的结构。每个复位电路50可以包括第四晶体管T4。第四晶体管T4的控制端被配置为接收复位信号R，第四晶体管T4的第一端与对应的数据线电连接，第四晶体管T4的第二端与第三电压端V ini电连接。
在一些实施例中，显示装置还包括设置在显示装置的非显示区或显示装置的电源中的控制电路60。控制电路60与每个像素单元801中的发光元件10的阴极电连接。控制电路60被配置为响应于至少一个控制信号，使得每个像素单元801中的发光元件10的阴极与第二电压端ELV SS或第四电压端ELV DD’电连接。例如，控制电路60使得每个像素单元801中的发光元件10的阴极在第一阶段M1与第二电压端ELV SS电连接，在第二阶段M2与第四电压端ELV DD’电连接。
在一些实现方式中，控制电路60的结构例如可以参照图4所示的控制电路60的结构。至少一个控制信号可以包括第一控制信号SEN和第二控制信号EM。控制电路包括第五晶体管T5和第六晶体管T6。第五晶体管T5的控制端被配置为接收第一控制信号SEN，第五晶体管T5的第一端与每个像素单元801中的发光元件10的阴极电连接，第五晶体管T5的第二端与第四电压端ELV DD’电连接。第六晶体管T6的控制端被配置为接收第二控制信号EM，第六晶体管T6的第一端与每个像素单元801中的发光元件10的阴极电连接，第六晶体管T6的第二端与第二电压端ELV SS电连接。
在一些实施例中，在每个显示周期的显示阶段之前可以逐行地实现对各像素单元中的发光元件的工作电压的感测，在每个显示周期的显示阶段可以逐行地驱动各像素单元中的发光元件发光，在每个显示周期的显示阶段之后可以逐行地实现对各像素单元中的第一晶体管的阈值电压的感测。
至此，已经详细描述了本公开的各实施例。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节。本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。
虽然已经通过示例对本公开的一些特定实施例进行了详细说明，但是本领域的技术人员应该理解，以上示例仅是为了进行说明，而不是为了限制本公开的范围。本领域的技术人员应该理解，可在不脱离本公开的范围和精神的情况下，对以上实施例进行修改或者对部分技术特征进行等同替换。本公开的范围由所附权利要求来限定。

Claims (20)

  1. 一种像素电路，包括：
    发光元件，包括阳极和阴极；
    第一开关电路，被配置为响应于来自第一扫描线的第一扫描信号，在导通的情况下传输来自数据线的电压；
    驱动电路，被配置为在所述第一开关电路传输的电压的控制下驱动所述发光元件发光，所述驱动电路包括：
    第一晶体管，所述第一晶体管的控制端被配置为与所述第一开关电路电连接，所述第一晶体管的第一端与第一电压端电连接，所述第一晶体管的第二端与所述发光元件的阳极电连接；和
    电容器，所述电容器的第一端与所述第一电压端电连接，所述电容器的第二端与所述第一开关电路电连接；和
    第二开关电路，与所述数据线、所述第一晶体管的第二端和所述发光元件的阳极电连接，被配置为响应于来自第二扫描线的第二扫描信号，在导通的情况下使所述数据线上的电位分别稳定在第一固定电位和第二固定电位，所述第一固定电位使得所述发光元件发光，所述第二固定电位使得所述第一晶体管截止。
  2. 根据权利要求1所述的像素电路，其中，所述第二开关电路包括第二晶体管，所述第二晶体管的控制端被配置为接收所述第二扫描信号，所述第二晶体管的第一端与所述数据线电连接，所述第二晶体管的第二端与所述发光元件的阳极电连接。
  3. 根据权利要求1所述的像素电路，其中，所述数据线与复位电路电连接，所述数据线的电位被所述复位电路分别复位到第一初始电位和第二初始电位，所述第一初始电位使得所述发光元件不发光，所述第二初始电位使得所述第一晶体管导通。
  4. 根据权利要求1所述的像素电路，其中，所述发光元件的阴极与控制电路电连接，在所述控制电路的控制下，所述发光元件的阴极与第二电压端或第四电压端电连接；
    其中，所述第二电压端的电位使得所述发光元件处于正向偏置，所述第四电压端 的电位使得所述发光元件处于反向偏置。
  5. 根据权利要求1-4任意一项所述的像素电路，其中，
    所述第一开关电路包括第三晶体管，所述第三晶体管的控制端被配置为接收所述第一扫描信号，所述第三晶体管的第一端与所述数据线电连接，所述第三晶体管的第二端与所述电容器的第二端和所述第一晶体管的控制端电连接。
  6. 一种显示装置，包括多个像素单元，每个像素单元包括如权利要求1-5任意一项所述的像素电路。
  7. 根据权利要求6所述的显示装置，还包括：
    多条第一扫描线，每条第一扫描线与同一行像素单元中的像素电路电连接；
    多条第二扫描线，每条第二扫描线与同一行像素单元中的像素电路电连接；和
    多条数据线，每条数据线与同一列像素单元中的像素电路电连接。
  8. 根据权利要求7所述的显示装置，还包括：
    多个复位电路，设置在所述显示装置的非显示区或源极驱动器中，每个复位电路与一条对应的数据线电连接，每个复位电路被配置为响应于复位信号，将对应的数据线的电位分别复位到第一初始电位和第二初始电位，所述第一初始电位使得与该条数据线电连接的每个像素单元中的发光元件不发光，所述第二初始电位使得与该条数据线电连接的每个像素单元中的第一晶体管导通。
  9. 根据权利要求8所述的显示装置，其中，每个复位电路包括第四晶体管，所述第四晶体管的控制端被配置为接收所述复位信号，所述第四晶体管的第一端与对应的数据线电连接，所述第四晶体管的第二端与第三电压端电连接。
  10. 根据权利要求6所述的显示装置，还包括：
    控制电路，设置在所述显示装置的非显示区或所述显示装置的电源中，所述控制电路与每个像素单元中的发光元件的阴极电连接；
    所述控制电路被配置为响应于至少一个控制信号，使得每个像素单元中的发光元 件的阴极与第二电压端或第四电压端电连接，其中，所述第二电压端的电位使得所述发光元件处于正向偏置，所述第四电压端的电位使得所述发光元件处于反向偏置。
  11. 根据权利要求10所述的显示装置，其中，所述至少一个控制信号包括第一控制信号和第二控制信号；
    所述控制电路包括：
    第五晶体管，所述第五晶体管的控制端被配置为接收所述第一控制信号，所述第五晶体管的第一端与每个像素单元中的发光元件的阴极电连接，所述第五晶体管的第二端与所述第四电压端电连接；和
    第六晶体管，所述第六晶体管的控制端被配置为接收所述第二控制信号，所述第六晶体管的第一端与每个像素单元中的发光元件的阴极电连接，所述第六晶体管的第二端与所述第二电压端电连接。
  12. 一种如权利要求1-6任意一项所述的像素电路的驱动方法，包括：
    在第一阶段，使数据线上的电位稳定在使得发光元件发光的第一固定电位；
    在第二阶段，使所述数据线上的电位稳定在使得第一晶体管截止的第二固定电位；
    在显示阶段，向所述数据线提供补偿后的数据电压，以驱动所述发光元件发光，其中，补偿后的数据电压根据所述第一固定电位和所述第二固定电位来确定。
  13. 根据权利要求12所述的驱动方法，其中，所述第一阶段包括第一非显示阶段和在所述第一非显示阶段之后的第二非显示阶段；
    在所述第一非显示阶段，第一开关电路响应于来自第一扫描线的第一扫描信号导通以将来自数据线的感测电压传输至所述电容器的第二端和所述第一晶体管的控制端，所述第一晶体管在所述感测电压的控制下导通以产生感测电流，第二开关电路响应于来自第二扫描线的第二扫描信号不导通；
    在所述第二非显示阶段，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通以使得所述感测电流对所述数据线充电，从而使得所述数据线上的电位稳定在所述第一固定电位。
  14. 根据权利要求12所述的驱动方法，其中，所述第二阶段包括第三非显示阶 段；
    在所述第三非显示阶段，所述第二开关电路响应于所述第二扫描信号导通以向所述数据线充电，所述第一开关电路响应于所述第一扫描信号导通以使得所述数据线对电容器进行充电，从而使得所述数据线上的电位稳定在所述第二固定电位。
  15. 根据权利要求13所述的驱动方法，其中，所述第一阶段还包括位于所述第一非显示阶段和所述第二非显示阶段之间的第四非显示阶段；
    在所述第四非显示阶段，将所述数据线的电位复位到使得所述发光元件不发光的第一初始电位，所述第一开关电路响应于所述第一扫描信号不导通，所述第二开关电路响应于所述第二扫描信号导通。
  16. 根据权利要求14所述的驱动方法，其中，所述第二阶段还包括在所述第三非显示阶段之前的第五非显示阶段；
    在所述第五非显示阶段，将所述数据线的电位复位到使得所述第一晶体管导通的第二初始电位，所述第一开关电路响应于所述第一扫描信号导通，所述第二开关电路响应于所述第二扫描信号导通。
  17. 根据权利要求13所述的驱动方法，其中，所述第一阶段还包括在所述第二非显示阶段之后的第六非显示阶段；
    在所述第六非显示阶段，源极驱动器从所述数据线读取所述第一固定电位。
  18. 根据权利要求14所述的驱动方法，其中，所述第二阶段还包括在所述第三非显示阶段之后的第七非显示阶段；
    在所述第七非显示阶段，源极驱动器从所述数据线读取所述第二固定电位。
  19. 根据权利要求12-18任意一项所述的驱动方法，其中，所述像素电路所在的显示面板的开机时刻与所述显示面板的关机时刻之间为一个显示周期；
    在同一显示周期内，所述第一阶段位于所述显示面板的开机时刻与所述显示阶段的开始时刻之间，所述第二阶段位于所述显示阶段的结束时刻与所述显示面板的关机时刻之间。
  20. 根据权利要求19所述的驱动方法，其中，在所述显示阶段，所述第一开关电路响应于所述第一扫描信号导通以将来自所述数据线的补偿后的数据电压传输至所述电容器的第二端和所述第一晶体管的控制端，所述第一晶体管在补偿后的数据电压的控制下导通以产生用于驱动所述发光元件发光的驱动电流，所述第二开关电路响应于所述第二扫描信号不导通；
    其中，补偿后的数据电压为补偿前的数据电压、第一补偿电压和第二补偿电压之和，所述第一补偿电压根据所述第一晶体管的阈值电压来确定，所述第二补偿电压根据所述发光元件的工作电压来确定，所述第一晶体管的阈值电压根据当前显示周期的上一个显示周期的第二固定电位来确定，所述发光元件的工作电压根据当前显示周期的第一固定电位来确定。
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