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WO2019237756A1 - 像素电路及其驱动方法、显示面板和显示装置 - Google Patents

像素电路及其驱动方法、显示面板和显示装置 Download PDF

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Publication number
WO2019237756A1
WO2019237756A1 PCT/CN2019/074839 CN2019074839W WO2019237756A1 WO 2019237756 A1 WO2019237756 A1 WO 2019237756A1 CN 2019074839 W CN2019074839 W CN 2019074839W WO 2019237756 A1 WO2019237756 A1 WO 2019237756A1
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Prior art keywords
transistor
reset
pole
gate
circuit
Prior art date
Application number
PCT/CN2019/074839
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English (en)
French (fr)
Inventor
冯宏庆
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/489,079 priority Critical patent/US11341912B2/en
Publication of WO2019237756A1 publication Critical patent/WO2019237756A1/zh

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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G09G3/3241—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror
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    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
    • G—PHYSICS
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    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
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    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/067—Special waveforms for scanning, where no circuit details of the gate driver are given
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    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G09G2320/045—Compensation of drifts in the characteristics of light emitting or modulating elements
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0693—Calibration of display systems

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • Light-emitting diode Light Emitting Diode, LED for short
  • the pixel display device of the LED display panel is a light emitting diode.
  • the LED display panel emits light by driving a transistor to generate a driving current in a saturated state, and the driving current drives the LED to emit light.
  • An embodiment of the present disclosure provides a pixel circuit including a reset compensation circuit, a data writing circuit, a light emitting control circuit, a driving transistor, and a light emitting device, the reset compensation circuit, a gate of the driving transistor, and the driving
  • the first pole of the transistor, the second pole of the driving transistor, and the reset control signal line are all connected, and are configured to respond to the control of the reset control signal provided by the reset control signal line to the drive transistor in a reset compensation phase.
  • reset the gate of the driving transistor and obtain the threshold voltage of the driving transistor, the data writing circuit is connected to the reset compensation circuit, the data line, and the gate line, and is configured to respond to the gate provided by the gate line.
  • the control of the driving signal transfers the data voltage provided by the data line to the reset compensation circuit during the writing phase, so that the reset compensation circuit writes the light-emitting voltage to the gate of the driving transistor.
  • the light-emission voltage is equal to the sum of the data voltage and the threshold voltage, and the light-emission control circuit and the light-emission control signal line, the The first pole and the first power terminal of the driving transistor are both connected, and are configured to respond to a light-emission control signal provided by the light-emission control signal line, and switch the first working voltage provided by the first power terminal in the light-emitting stage.
  • the second pole of the driving transistor is connected to the first terminal of the light emitting device, and the driving transistor is configured to The first operating voltage generates a corresponding driving current to drive the light emitting device to emit light, and a second terminal of the light emitting device is connected to a second power source terminal.
  • the reset compensation circuit includes a reset sub-circuit and a compensation sub-circuit
  • the reset sub-circuit is connected to the gate of the driving transistor and a reset power supply terminal, and is configured to reset all
  • the reset voltage provided by the reset power supply terminal is written to the gate of the driving transistor to reset the gate of the driving transistor, the compensation sub-circuit, the gate of the driving transistor, and the driving transistor
  • the first pole of the driving transistor is connected to the second pole of the driving transistor, and is configured to write a reset voltage at the gate of the driving transistor to the second pole of the driving transistor during the reset compensation phase, and obtain An output voltage at a first pole of the driving transistor that is equal to a difference between the reset voltage and the threshold voltage, and generates the data based on the received data voltage and the acquired threshold voltage in the writing phase
  • the light-emitting voltage is written to the gate of the driving transistor.
  • the reset sub-circuit includes a first transistor, a gate of the first transistor is connected to the reset control signal line, and a first pole of the first transistor is connected to a gate of the driving transistor. Connected, the second pole of the first transistor is connected to the reset power terminal.
  • the compensation sub-circuit includes a second transistor, a third transistor, and a capacitor, a gate of the second transistor is connected to the reset control signal line, and a first electrode of the second transistor is connected to the reset transistor.
  • the gate of the driving transistor is connected, the second pole of the second transistor is connected to the second pole of the driving transistor, the gate of the third transistor is connected to the reset control signal line, and the third transistor
  • the first pole of the capacitor is connected to the first terminal of the capacitor, the second pole of the third transistor is connected to the first pole of the driving transistor, and the second terminal of the capacitor is connected to the gate of the driving transistor.
  • the data writing circuit includes a fourth transistor, a gate of the fourth transistor is connected to the gate line, and a first pole of the fourth transistor is connected to the reset compensation circuit.
  • a first terminal of the capacitor is connected to a first electrode of the third transistor, and a second electrode of the fourth transistor is connected to the data line.
  • the light emission control circuit includes a fifth transistor, a gate of the fifth transistor is connected to the light emission control signal line, and a first electrode of the fifth transistor is connected to the first power supply terminal.
  • the second pole of the fifth transistor is connected to the first pole of the driving transistor.
  • the pixel circuit further includes a false light emission control circuit
  • the second pole of the driving transistor is connected to the first end of the light emitting device through the false light emission control circuit, and the false light emission control circuit is in communication with
  • the light emission control signal line is connected and configured to, in response to the control of the light emission control signal, cause the second electrode of the driving transistor and the first end of the light emitting device to be disconnected during a reset compensation phase, and to emit light
  • the stage makes a path between the second pole of the driving transistor and the first end of the light emitting device.
  • the false light emission control circuit includes a sixth transistor, a gate of the sixth transistor is connected to the light emission control signal line, and a first electrode of the sixth transistor is connected to a first electrode of the driving transistor. Diode connection, the second pole of the sixth transistor is connected to the first end of the light emitting device.
  • all the transistors in the pixel circuit are P-type transistors.
  • An embodiment of the present disclosure further provides a pixel circuit including first to sixth transistors, a capacitor, a driving transistor, and a light emitting device, a first pole of the first transistor, a second terminal of the capacitor, and the first The first pole of the two transistors and the gate of the driving transistor are connected to the first node, the first pole of the third transistor, the first terminal of the capacitor, and the first pole of the fourth transistor are connected to the first node.
  • Two nodes, the second pole of the second transistor, the second pole of the driving transistor, and the first pole of the sixth transistor are connected to a third node, the first pole of the driving transistor, the third pole A second pole of the transistor and a second pole of the fifth transistor are connected to a fourth node, and gates of the first transistor to the third transistor are connected to a reset control signal line, and the fifth transistor and the The gate of the sixth transistor is connected to the light emission control signal line, the second electrode of the first transistor is connected to the reset power supply terminal, the gate of the fourth transistor is connected to the gate line, and the second electrode of the fourth transistor is connected Connect to data cable A first terminal of the fifth transistor is connected to a first power terminal, a first terminal of the light emitting device is connected to a second electrode of the sixth transistor, and a second terminal of the light emitting device is connected to a second Power side.
  • An embodiment of the present disclosure also provides a display panel including any one of the pixel circuits described above.
  • An embodiment of the present disclosure also provides a display device including the display panel as described above.
  • An embodiment of the present disclosure further provides a pixel circuit driving method.
  • the pixel circuit is any one of the pixel circuits described above.
  • the driving method includes: in the reset compensation phase, driving the driver through the reset compensation circuit. The gate of the transistor is reset, and the threshold voltage of the driving transistor is obtained; in the writing phase, the data voltage is transferred to the reset compensation circuit through the data writing circuit, and the reset compensation circuit Writing the light-emitting voltage having a voltage equal to the sum of the data voltage and the threshold voltage to the gate of the driving transistor; and in the light-emitting stage, writing the first operating voltage through the light-emitting control circuit It is written to the first pole of the driving transistor, and the driving transistor generates a corresponding driving current according to the light-emitting voltage and the first operating voltage to drive the light-emitting device to emit light.
  • the reset compensation circuit includes a reset sub-circuit and a compensation sub-circuit, the reset sub-circuit is connected to a gate and a reset power terminal of the driving transistor, and the compensation sub-circuit is connected to the driving transistor.
  • the method includes: writing a reset voltage provided by the reset power terminal to a gate of the driving transistor through the reset sub-circuit to reset the gate of the driving transistor;
  • the reset voltage at the gate of the drive transistor is written to the second pole of the drive transistor, and an output voltage at the first pole of the drive transistor is obtained, where the output voltage is equal to the reset voltage and the threshold The difference in voltage.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure
  • FIG. 2 is a schematic circuit configuration diagram of a pixel circuit provided by an embodiment of the present disclosure
  • FIG. 3 and FIG. 4 are working timing diagrams of the pixel circuit shown in FIG. 2;
  • FIG. 5 is a flowchart of a pixel circuit driving method according to an embodiment of the present disclosure.
  • each driving transistor The uniformity of the threshold voltage of each driving transistor on the LED display panel is poor, and the threshold voltage of each driving transistor will drift during use, so when the gate line (scanning line) controls the switching transistor to turn on to each driving transistor
  • each driving transistor When the same data voltage is input, each driving transistor generates different driving currents due to different threshold voltages thereof, resulting in poor uniformity of light emission brightness of each LED in a display device including the LED display panel.
  • a threshold voltage compensation circuit may be provided in the pixel circuit to compensate the threshold voltage of each driving transistor.
  • the threshold voltage compensation circuit is generally composed of a plurality of transistors.
  • the threshold voltage compensation circuit needs to be configured with multiple control signal lines and corresponding control chips, and the control chip also needs to be provided with multiple corresponding control signal sources to control the threshold voltage compensation circuit to work. In this way, the structure of the threshold voltage compensation circuit in the pixel circuit is complicated, and more control signal lines and control signal sources are required, resulting in a larger overall power consumption of the pixel circuit.
  • FIG. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure.
  • the pixel circuit includes a reset compensation circuit 1, a data writing circuit 2, a light emission control circuit 3, a driving transistor DTFT, and a light emitting device.
  • the light emitting device may be, for example, an organic light emitting diode (OLED).
  • the light emitting device may be other light emitting diodes of a current driving type.
  • the reset compensation circuit 1 is connected to the gate of the driving transistor DTFT, the first pole of the driving transistor DTFT, the second pole of the driving transistor DTFT, and the reset control signal line RST.
  • the reset compensation circuit 1 is configured to, in response to control of a reset control signal provided by the reset control signal line RST, reset the gate of the driving transistor DTFT in the reset compensation phase, and obtain a threshold voltage of the driving transistor DTFT.
  • the data writing circuit 2 is connected to the reset compensation circuit 1, the data line DATA, and the gate line GATE.
  • the data writing circuit 2 is configured to transfer the data voltage provided by the data line DATA to the reset compensation circuit 1 in response to the control of the gate driving signal provided by the gate line GATE, so that the reset compensation circuit 1 transmits the light-emitting voltage.
  • the light-emitting voltage written to the gate of the driving transistor DTFT is equal to the sum of the data voltage and the threshold voltage.
  • the light emission control circuit 3 is connected to the light emission control signal line EM, the first electrode of the driving transistor DTFT, and the first power terminal.
  • the light emission control circuit 3 is configured to write the first operating voltage provided by the first power supply terminal to the first electrode of the driving transistor DTFT in the light emitting phase in response to the light emission control signal provided by the light emission control signal line EM.
  • the second pole of the driving transistor DTFT is connected to the first terminal (for example, the anode) of the light-emitting device (for example, the OLED).
  • the driving transistor DTFT is used to generate a corresponding driving current according to the light-emitting voltage and the first working voltage during the light-emitting stage to drive The light emitting device emits light.
  • a second terminal (for example, a cathode) of the light emitting device is connected to a second power terminal (for example, a low voltage terminal or a ground terminal).
  • a circuit for resetting the gate of the driving transistor DTFT and a circuit for threshold voltage compensation of the driving transistor DTFT are integrated into the same circuit, that is, the reset compensation circuit 1, and in addition to the reset that provides a reset voltage Outside the power supply terminal, the reset compensation circuit 1 only needs to be provided with a reset control signal line RST and a reset control signal. Therefore, in the pixel circuit of this embodiment, the reset compensation circuit 1 can not only Resetting the gate of the driving transistor under control can also compensate the threshold voltage of the driving transistor without having to configure additional control signal lines for threshold voltage compensation. In the case of implementing the threshold voltage compensation for the driving transistor DTFT, the technical solution of this embodiment can effectively reduce the types of control signal lines and control signals, simplify the structure of the pixel circuit, and reduce power consumption.
  • the reset compensation circuit 1 includes a reset sub-circuit 101 and a compensation sub-circuit 102.
  • the reset sub-circuit 101 is connected to the gate of the driving transistor DTFT and the reset power terminal, and is used to write the reset voltage provided by the reset power terminal to the gate of the driving transistor DTFT during the reset compensation phase, so as to Perform a reset.
  • the compensation sub-circuit 102 is connected to the gate of the driving transistor DTFT, the first pole of the driving transistor DTFT, and the second pole of the driving transistor DTFT, and is used to write the reset voltage at the gate of the driving transistor DTFT to the driver during the reset compensation phase.
  • the second pole of the transistor DTFT and obtains the output voltage at the first pole of the driving transistor DTFT, the output voltage is equal to the difference between the reset voltage and the threshold voltage, and generates light according to the received data voltage and the obtained threshold voltage during the writing phase Voltage and write the light-emitting voltage to the gate of the driving transistor DTFT.
  • the pixel circuit further includes a false light emission control circuit 4, the second pole of the driving transistor DTFT is connected to the first end of the light emitting device through the false light emission control circuit 4, and the false light emission control circuit 4 and the light emission control signal line
  • the EM is connected and configured to, in response to the control of the light emission control signal, cause the second pole of the driving transistor DTFT and the first end of the light emitting device to be disconnected during the reset compensation phase, and to cause the second pole of the driving transistor DTFT and A path between the first ends of the light emitting device.
  • the driving transistor DTFT In the reset compensation phase, when a reset voltage is input to the gate and the second pole of the driving transistor DTFT, the first pole of the driving transistor DTFT will be discharged through the driving transistor DTFT. At this time, the driving transistor DTFT will output an unstable current, which may cause Causes the light emitting device to emit light by mistake (described in detail later). In order to prevent the light emitting device from emitting light by mistake, a false light emitting control circuit 4 may be provided in this embodiment, so that the second electrode of the driving transistor DTFT and the first end of the light emitting device are disconnected during the reset compensation stage, thereby preventing the light emitting device from emitting light by mistake. .
  • a circuit for resetting the gate of the driving transistor DTFT and a circuit for compensating the threshold voltage of the driving transistor are integrated into the same circuit, and the circuit only needs to be configured with a reset control signal line and
  • the reset control signal can effectively reduce the types of control signal lines and control signals, simplify the structure of the pixel circuit, and reduce power consumption in the case of performing threshold voltage compensation on the driving transistor DTFT.
  • FIG. 2 is a schematic circuit configuration diagram of a pixel circuit provided by an embodiment of the present disclosure.
  • the pixel circuit shown in FIG. 2 is a specific implementation of the pixel circuit of the above embodiment.
  • the reset sub-circuit 101 includes a first transistor T1, a gate of the first transistor T1 is connected to a reset control signal line RST, a first pole of the first transistor T1 is connected to a gate of a driving transistor DTFT, and a first transistor The second pole of T1 is connected to the reset power terminal.
  • the compensation sub-circuit 102 includes a second transistor T2, a third transistor T3, and a capacitor C.
  • the gate of the second transistor T2 is connected to the reset control signal line RST, the first pole of the second transistor T2 is connected to the gate of the driving transistor DTFT, and the second pole of the second transistor T2 is connected to the second pole of the driving transistor DTFT.
  • the gate of the third transistor T3 is connected to the reset control signal line RST, the first pole of the third transistor T3 is connected to the first terminal of the capacitor C, and the second pole of the third transistor T3 is connected to the first pole of the driving transistor DTFT.
  • the second terminal of the capacitor C is connected to the gate of the driving transistor DTFT.
  • the data writing circuit 2 includes a fourth transistor T4.
  • the gate of the fourth transistor T4 is connected to the gate line GATE.
  • the first pole of the fourth transistor T4 is connected to the first pole of the third transistor T3 in the reset compensation circuit 1 and the first terminal of the capacitor C.
  • the second pole is connected to the data line DATA.
  • the light emission control circuit 3 includes a fifth transistor T5.
  • the gate of the fifth transistor T5 is connected to the light emission control signal line EM, the first pole of the fifth transistor T5 is connected to the first power terminal, and the second pole of the fifth transistor T5 is connected to the first pole of the driving transistor DTFT.
  • the false light emission control circuit 4 includes a sixth transistor T6.
  • the gate of the sixth transistor T6 is connected to the light emission control signal line EM, the first pole of the sixth transistor T6 is connected to the second pole of the driving transistor DTFT, and the second pole of the sixth transistor T6 is connected to the first end of the light emitting device.
  • each transistor may be one of a polysilicon thin film transistor, an amorphous silicon thin film transistor, an oxide thin film transistor, and an organic thin film transistor.
  • the “first electrode” may refer to a source of a transistor
  • the “second electrode” may refer to a drain of a transistor.
  • first pole and second pole are interchangeable, that is, the "first pole” can also refer to the drain of a transistor, and the “second pole” can refer to The source of a transistor.
  • all the transistors in the pixel circuit can be P-type transistors. At this time, the same manufacturing process can be used to simultaneously prepare the above transistors, thereby shortening the production cycle of the pixel circuit. It should be noted that all the transistors in the pixel circuit are P-type thin film transistors, which is only an optional solution of this embodiment, which does not limit the technical solution of the present disclosure.
  • the driving transistor may be a P-type thin film transistor, and other transistors (the first transistor T1 to the sixth transistor T6) may be selectively configured as N-type thin film transistors.
  • the driving transistor DTFT and the first to sixth transistors T1 to T6 are all P-type thin film transistors as an example.
  • the first power supply terminal provides a first working voltage VDD
  • the second power supply terminal provides a second working voltage.
  • the operating voltage VSS for example, a ground voltage
  • the reset power supply terminal provides a reset voltage Vrst
  • the threshold voltage of the driving transistor DTFT is Vth.
  • the node connected to the second end of the capacitor C, the first pole of the first transistor T1, the first pole of the second transistor T2, and the gate of the driving transistor DTFT is labeled N1.
  • the node of the first terminal, the first pole of the third transistor T3, and the first pole of the fourth transistor T4 is labeled N2, and is connected to the second pole of the second transistor T2, the second pole of the driving transistor DTFT, and the sixth transistor T6.
  • the node of the first pole is labeled N3, and the node connected to the second pole of the third transistor T3, the second pole of the fifth transistor T5, and the first pole of the driving transistor DTFT is marked N4.
  • FIG. 3 is a working timing diagram of the pixel circuit shown in FIG. 2. As shown in FIG. 3, the working process of the pixel circuit includes three phases, namely, a reset compensation phase t1, a writing phase t2, and a light emitting phase t3.
  • the reset control signal provided by the reset control signal line RST is at a low level
  • the gate drive signal (also called a scan signal) provided by the gate line GATE is at a high level
  • the light emission control provided by the light emission control signal line EM The signal is high.
  • the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on, and the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off.
  • the reset voltage Vrst provided by the reset power terminal is written to the first node N1 through the first transistor T1.
  • the reset voltage at the first node N1 is Vrst is written to the third node N3 through the second transistor T2.
  • the fourth node N4 (at the end of the previous frame display, the voltage of the fourth node N4 is the first working voltage VDD) is discharged through the driving transistor DTFT until the voltage of the fourth node N4 is Vrst-Vth.
  • the driving transistor DTFT is turned off. Because the third transistor T3 is turned on, the voltage at the fourth node N4 is written to the second node N2 through the third transistor T3, and the voltage at the second node N2 is Vrst-Vth.
  • the voltage of the first terminal of the capacitor C is Vrst-Vth
  • the voltage of the second terminal of the capacitor C is Vrst
  • the voltage difference between the first terminal and the second terminal of the capacitor C is -Vth.
  • the sixth transistor T6 is turned off, during the discharge of the fourth node N4 through the driving transistor DTFT, the current output from the driving transistor DTFT cannot be transferred to the light emitting device (such as OLED), so the light emitting device (for example, OLED) does not emit light by mistake.
  • the light emitting device such as OLED
  • the reset control signal provided by the reset control signal line RST is at a high level
  • the gate drive signal provided by the gate line GATE is at a low level
  • the light emission control signal provided by the light emission control signal line EM is at a high level.
  • the fourth transistor T4 is turned on, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are all turned off.
  • the fourth transistor T4 Since the fourth transistor T4 is turned on, the data voltage Vdata in the data line DATA can be written to the second node N2 through the fourth transistor T4, and the voltage at the second node N2 jumps from Vrst-Vth to Vdata. Because both the first transistor T1 and the second transistor T2 are turned off, the first node N1 is in a floating state. Under the bootstrapping effect of the capacitor C (keeping the voltage difference across the capacitor C constant), the The voltage jumps from Vrst-Vth to Vdata + Vth.
  • the reset control signal provided by the reset control signal line RST is at a high level
  • the gate drive signal provided by the gate line GATE is at a high level
  • the light emission control signal provided by the light emission control signal line EM is at a low level.
  • the fifth transistor T5 and the sixth transistor T6 are both turned on, and the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are all turned off.
  • the gate-source voltage Vgs (the voltage difference between the gate and the source) of the driving transistor DTFT is Vdata + Vth-VDD.
  • I is the driving current output by the driving transistor DTFT
  • K is a constant, which is related to the channel characteristics of the driving transistor DTFT.
  • the driving current output by the driving transistor DTFT has nothing to do with the threshold voltage of the driving transistor DTFT, that is, the threshold voltage compensation of the driving transistor DTFT is realized, so that the threshold voltage of each driving transistor DTFT can be solved.
  • the threshold voltage compensation of the driving transistor DTFT is realized, so that the threshold voltage of each driving transistor DTFT can be solved. Different causes the problem of uneven light emission brightness of the display panel.
  • control signal line configured by the compensation sub-circuit of the pixel circuit in this embodiment is a reset control signal line in the reset sub-circuit, so there is no need to additionally configure a control signal line for the compensation sub-circuit, which can effectively reduce pixels.
  • the types of control signal lines and control signals required by the circuit simplify the structure of the pixel circuit and reduce power consumption.
  • the working timing diagram of the pixel circuit may be as shown in FIG. 4.
  • FIG. 5 is a flowchart of a pixel circuit driving method provided by an embodiment of the present disclosure.
  • the pixel circuit is the pixel circuit provided by the above embodiment.
  • the driving method includes the following steps S1 to S3.
  • Step S1 In the reset compensation phase, the gate of the driving transistor is reset by a reset compensation circuit, and a threshold voltage of the driving transistor is obtained.
  • the reset compensation circuit may include a reset sub-circuit and a compensation sub-circuit.
  • step S1 includes: sub-step S101, writing the reset voltage provided by the reset power supply terminal to the gate of the driving transistor through the reset sub-circuit to reset the gate of the driving transistor; Sub-step S102: write the reset voltage at the gate of the driving transistor to the second pole of the driving transistor through the compensation sub-circuit, and obtain the output voltage at the first pole of the driving transistor, so The output voltage is equal to the difference between the reset bit voltage and the threshold voltage.
  • Step S2 In the writing phase, the data voltage is transmitted to the reset compensation circuit through the data writing circuit, and the reset compensation circuit writes the light-emitting voltage whose voltage is equal to the sum of the data voltage and the threshold voltage. Into the gate of the drive transistor.
  • Step S3 In the light-emitting phase, write a first operating voltage to a first pole of the driving transistor through the light-emitting control circuit, and the driving transistor generates a corresponding drive according to the light-emitting voltage and the first operating voltage. A current to drive the light emitting device to emit light.
  • An embodiment of the present disclosure further provides a display panel including the pixel circuit provided in the foregoing embodiment.
  • the display panel according to an embodiment of the present disclosure may be an OLED display panel or the like manufactured using a low-temperature polysilicon process.
  • An embodiment of the present disclosure provides a display device.
  • the display device includes the display panel provided in the foregoing embodiment.
  • the display panel provided in the foregoing embodiment.

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Abstract

一种像素电路及其驱动方法、显示面板和显示装置，像素电路包括：复位补偿电路（1）、数据写入电路（2）、发光控制电路（3）、驱动晶体管（DTFT）和发光器件（OLED），其中，复位补偿电路（1）与驱动晶体管（DTFT）的栅极、驱动晶体管（DTFT）的第一极、驱动晶体管（DTFT）的第二极以及复位控制信号线（RST）均连接，并且配置为响应于复位控制信号线（RST）所提供的复位控制信号的控制，在复位补偿阶段（t1）对驱动晶体管（DTFT）的栅极进行复位、以及获取驱动晶体管（DTFT）的阈值电压。

Description

像素电路及其驱动方法、显示面板和显示装置
相关申请的交叉引用
本申请要求于2018年6月15日提交的中国专利申请No.201810619675.2的优先权，该中国专利申请所公开的内容以引用的方式全文并入本文中。
技术领域
本公开涉及显示技术领域，特别涉及像素电路及其驱动方法、显示面板和显示装置。
背景技术
发光二极管(Light Emitting Diode，简称：LED)显示面板的应用越来越广泛。LED显示面板的像素显示器件为发光二极管，LED显示面板发光是通过驱动晶体管在饱和状态下产生驱动电流、该驱动电流驱动LED发光实现的。
发明内容
本公开的实施例提供了一种像素电路，包括：复位补偿电路、数据写入电路、发光控制电路、驱动晶体管和发光器件，所述复位补偿电路与所述驱动晶体管的栅极、所述驱动晶体管的第一极、所述驱动晶体管的第二极和复位控制信号线均连接，并且配置为响应所述复位控制信号线所提供的复位控制信号的控制，在复位补偿阶段对所述驱动晶体管的栅极进行复位、以及获取所述驱动晶体管的阈值电压，所述数据写入电路与所述复位补偿电路、数据线和栅线均连接，并且配置为响应于所述栅线所提供的栅驱动信号的控制，在写入阶段将所述数据线所提供的数据电压传递至所述复位补偿电路，以供所述复位补偿电路将发光电压写入至所述驱动晶体管的栅极，所述发光电压等 于所述数据电压与所述阈值电压的和，所述发光控制电路与发光控制信号线、所述驱动晶体管的第一极、第一电源端均连接，并且被配置为响应于所述发光控制信号线所提供的发光控制信号，在发光阶段将所述第一电源端所提供的第一工作电压写入至所述驱动晶体管的第一极，所述驱动晶体管的第二极与所述发光器件的第一端连接，所述驱动晶体管被配置为在所述发光阶段根据所述发光电压和所述第一工作电压产生相应的驱动电流，以驱动所述发光器件发光，以及所述发光器件的第二端与第二电源端连接。
在一些实施方式中，所述复位补偿电路包括复位子电路和补偿子电路，所述复位子电路与所述驱动晶体管的栅极和复位电源端连接，并且配置为在所述复位补偿阶段将所述复位电源端所提供的复位电压写入至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位，所述补偿子电路与所述驱动晶体管的栅极、所述驱动晶体管的第一极、所述驱动晶体管的第二极连接，并且配置为在所述复位补偿阶段将所述驱动晶体管的栅极处的复位电压写入至所述驱动晶体管的第二极，并获取所述驱动晶体管的第一极处的等于所述复位电压与所述阈值电压之差的输出电压，以及在所述写入阶段根据接收到的所述数据电压和获取的所述阈值电压生成所述发光电压，并将所述发光电压写入至所述驱动晶体管的栅极。
在一些实施方式中，所述复位子电路包括第一晶体管，所述第一晶体管的栅极与所述复位控制信号线连接，所述第一晶体管的第一极与所述驱动晶体管的栅极连接，所述第一晶体管的第二极与所述复位电源端连接。
在一些实施方式中，所述补偿子电路包括第二晶体管、第三晶体管和电容，所述第二晶体管的栅极与所述复位控制信号线连接，所述第二晶体管的第一极与所述驱动晶体管的栅极连接，所述第二晶体管的第二极与所述驱动晶体管的第二极连接，所述第三晶体管的栅极与所述复位控制信号线连接，所述第三晶体管的第一极与所述电容的第一端连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接，所述电容的第二端与所述驱动晶体管的栅极连接。
在一些实施方式中，所述数据写入电路包括第四晶体管，所述第四晶体管的栅极与所述栅线连接，所述第四晶体管的第一极与所述复位补偿电路的所述电容的第一端和所述第三晶体管的第一极连接，所述第四晶体管的第二极与所述数据线连接。
在一些实施方式中，所述发光控制电路包括第五晶体管，所述第五晶体管的栅极与所述发光控制信号线连接，所述第五晶体管的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述驱动晶体管的第一极连接。
在一些实施方式中，所述像素电路还包括误发光控制电路，所述驱动晶体管的第二极通过所述误发光控制电路与所述发光器件的第一端连接，所述误发光控制电路与所述发光控制信号线连接，并且配置为响应于所述发光控制信号的控制，在复位补偿阶段使得所述驱动晶体管的第二极与所述发光器件的第一端之间断路，以及在发光阶段使得所述驱动晶体管的第二极与所述发光器件的第一端之间通路。
在一些实施方式中，所述误发光控制电路包括第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述驱动晶体管的第二极连接，所述第六晶体管的第二极与所述发光器件的第一端连接。
在一些实施方式中，所述像素电路内的所有晶体管均为P型晶体管。
本公开的实施例还提供一种像素电路，包括第一晶体管至第六晶体管、电容、驱动晶体管和发光器件，所述第一晶体管的第一极、所述电容的第二端、所述第二晶体管的第一极、所述驱动晶体管的栅极连接于第一节点，所述第三晶体管的第一极、所述电容的第一端、所述第四晶体管的第一极连接于第二节点，所述第二晶体管的第二极、所述驱动晶体管的第二极、所述第六晶体管的第一极连接于第三节点，所述驱动晶体管的第一极、所述第三晶体管的第二极和所述第五晶体管的第二极连接于第四节点，所述第一晶体管至所述第三晶体管的栅极连接至复位控制信号线，所述第五晶体管和所述第六晶体管的栅极连接至发光控制信号线，所述第一晶体管的第二极连接至复位 电源端，所述第四晶体管的栅极连接至栅线，所述第四晶体管的第二极连接至数据线，所述第五晶体管的第一极连接至第一电源端，所述发光器件的第一端连接至所述第六晶体管的第二极，以及所述发光器件的第二端连接至第二电源端。
本公开的实施例还提供了一种显示面板，包括如上述的任一种像素电路。
本公开的实施例还提供了一种显示装置，包括如上述的显示面板。
本公开的实施例还提供了一种像素电路驱动方法，所述像素电路为上述任一种像素电路，所述驱动方法包括：在所述复位补偿阶段，通过所述复位补偿电路对所述驱动晶体管的栅极进行复位，以及获取所述驱动晶体管的阈值电压；在所述写入阶段，通过所述数据写入电路将所述数据电压传递至所述复位补偿电路，所述复位补偿电路将电压大小等于所述数据电压与所述阈值电压之和的所述发光电压写入至所述驱动晶体管的栅极；以及在所述发光阶段，通过所述发光控制电路将所述第一工作电压写入至所述驱动晶体管的第一极，所述驱动晶体管根据所述发光电压和所述第一工作电压产生相应的驱动电流，以驱动所述发光器件发光。
在一些实施方式中，所述复位补偿电路包括复位子电路和补偿子电路，所述复位子电路与所述驱动晶体管的栅极和复位电源端连接，所述补偿子电路与所述驱动晶体管的栅极、所述驱动晶体管的第一极、所述驱动晶体管的第二极连接，通过所述复位补偿电路对所述驱动晶体管的栅极进行复位、以及获取所述驱动晶体管的阈值电压的步骤包括：通过所述复位子电路将所述复位电源端所提供的复位电压写入至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位；通过所述补偿子电路将所述驱动晶体管的栅极处的复位电压写入至所述驱动晶体管的第二极，并获取所述驱动晶体管的第一极处的输出电压，所述输出电压等于所述复位电压与所述阈值电压之差。
附图说明
图1为本公开的实施例提供的像素电路的结构示意图；
图2为本公开的实施例提供的像素电路的电路构成示意图；
图3和图4为图2所示像素电路的工作时序图；
图5为本公开的实施例提供的像素电路驱动方法的流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的像素电路及其驱动方法、显示面板和显示装置进行详细描述。
LED显示面板上各个驱动晶体管的阈值电压的均匀性较差，而且在使用过程中各个驱动晶体管的阈值电压还会发生漂移，这样当栅线(扫描线)控制开关晶体管导通以向各驱动晶体管输入相同的数据电压时，各驱动晶体管由于其阈值电压的不同而产生不同的驱动电流，从而导致包括该LED显示面板的显示装置中各LED的发光亮度的均一性较差。
例如，可在像素电路中设置阈值电压补偿电路来对各驱动晶体管的阈值电压进行补偿，阈值电压补偿电路一般由多个晶体管构成。然而，阈值电压补偿电路需要配置多条控制信号线及相应的控制芯片，控制芯片中也需要设置对应的多个控制信号源，以控制阈值电压补偿电路进行工作。这样，像素电路中的阈值电压补偿电路的结构复杂，且所需的控制信号线和控制信号源较多，导致像素电路的整体功耗较大。
图1为本公开的实施例提供的像素电路的结构示意图，如图1所示，该像素电路包括复位补偿电路1、数据写入电路2、发光控制电路3、驱动晶体管DTFT和发光器件。本实施例中，发光器件可以是例如有机发光二极管(OLED)。可替代地，发光器件还可以是电流驱动型的其他发光二极管。
在一些实施方式中，复位补偿电路1与驱动晶体管DTFT的栅极、驱动晶体管DTFT的第一极、驱动晶体管DTFT的第二极和复位控制信号线RST均连接。复位补偿电路1配置为响应于复位控制信号线RST 所提供的复位控制信号的控制，在复位补偿阶段对驱动晶体管DTFT的栅极进行复位，以及获取驱动晶体管DTFT的阈值电压。
数据写入电路2与复位补偿电路1、数据线DATA和栅线GATE均连接。数据写入电路2配置为响应于栅线GATE所提供的栅驱动信号的控制，在写入阶段将数据线DATA所提供的数据电压传递至复位补偿电路1，以供复位补偿电路1将发光电压写入至驱动晶体管DTFT的栅极，发光电压等于数据电压与阈值电压的和。
发光控制电路3与发光控制信号线EM、驱动晶体管DTFT的第一极、第一电源端均连接。发光控制电路3配置为响应于发光控制信号线EM所提供的发光控制信号，在发光阶段将第一电源端所提供的第一工作电压写入至驱动晶体管DTFT的第一极。
驱动晶体管DTFT的第二极与发光器件(例如，OLED)的第一端(例如，阳极)连接，驱动晶体管DTFT用于在发光阶段根据发光电压和第一工作电压产生相应的驱动电流，以驱动发光器件发光。发光器件的第二端(例如，阴极)与第二电源端(例如，低电压端或接地端)连接。
在本实施例中，将用于对驱动晶体管DTFT的栅极进行复位的电路和对驱动晶体管DTFT进行阈值电压补偿的电路整合为同一电路，即，复位补偿电路1，且除了提供复位电压的复位电源端之外，复位补偿电路1仅需配置复位控制信号线RST和复位控制信号，从而，本实施例的像素电路中，复位补偿电路1不仅能够在复位控制信号线RST提供的复位控制信号的控制下对驱动晶体管的栅极进行复位，还能够实现对驱动晶体管的阈值电压进行补偿，而无需为进行阈值电压补偿而配置额外的控制信号线。本实施例的技术方案在实现对驱动晶体管DTFT进行阈值电压补偿的情况下，能够有效减少控制信号线和控制信号的种类，简化像素电路的结构，降低功耗。
在一些实施方式中，复位补偿电路1包括复位子电路101和补偿子电路102。
复位子电路101与驱动晶体管DTFT的栅极和复位电源端连接，用于在复位补偿阶段将复位电源端所提供的复位电压写入至驱动晶 体管DTFT的栅极，以对驱动晶体管DTFT的栅极进行复位。
补偿子电路102与驱动晶体管DTFT的栅极、驱动晶体管DTFT的第一极、驱动晶体管DTFT的第二极连接，用于在复位补偿阶段将驱动晶体管DTFT的栅极处的复位电压写入至驱动晶体管DTFT的第二极，并获取驱动晶体管DTFT的第一极处的输出电压，输出电压等于复位电压与阈值电压之差，以及在写入阶段根据接收到的数据电压和获取的阈值电压生成发光电压，并将发光电压写入至驱动晶体管DTFT的栅极。
在本实施例中，仅需要配置复位控制信号线RST和复位控制信号即可控制复位子电路101和补偿子电路102的工作状态。
在一些实施方式中，所述像素电路还包括误发光控制电路4，驱动晶体管DTFT的第二极通过误发光控制电路4与发光器件的第一端连接，误发光控制电路4与发光控制信号线EM连接，并且配置为响应于发光控制信号的控制，在复位补偿阶段使得驱动晶体管DTFT的第二极与发光器件的第一端之间断路，以及在发光阶段使得驱动晶体管DTFT的第二极与发光器件的第一端之间通路。
在复位补偿阶段，当驱动晶体管DTFT的栅极和第二极输入有复位电压时，驱动晶体管DTFT的第一极会通过驱动晶体管DTFT进行放电，此时驱动晶体管DTFT会输出不稳定电流，从而可能导致发光器件误发光(稍后将详细描述)。为避免发光器件误发光，本实施例中可设置误发光控制电路4，以使得在复位补偿阶段驱动晶体管DTFT的第二极与发光器件的第一端之间断路，从而能避免发光器件误发光。
本实施例提供的像素电路中，通过将用于对驱动晶体管DTFT的栅极进行复位的电路和对驱动晶体管进行阈值电压补偿的电路整合为同一电路，且该电路仅需配置复位控制信号线和复位控制信号，从而在实现对驱动晶体管DTFT进行阈值电压补偿的情况下，有效减少了控制信号线和控制信号的种类，简化了像素电路的结构，降低了功耗。
图2为本公开的实施例提供的像素电路的电路构成示意图。图2 所示的像素电路为上述实施例的像素电路的具体实施。
本实施例中，复位子电路101包括第一晶体管T1，第一晶体管T1的栅极与复位控制信号线RST连接，第一晶体管T1的第一极与驱动晶体管DTFT的栅极连接，第一晶体管T1的第二极与复位电源端连接。
本实施例中，补偿子电路102包括第二晶体管T2、第三晶体管T3和电容C。
第二晶体管T2的栅极与复位控制信号线RST连接，第二晶体管T2的第一极与驱动晶体管DTFT的栅极连接，第二晶体管T2的第二极与驱动晶体管DTFT的第二极连接。
第三晶体管T3的栅极与复位控制信号线RST连接，第三晶体管T3的第一极与电容C的第一端连接，第三晶体管T3的第二极与驱动晶体管DTFT的第一极连接。
电容C的第二端与驱动晶体管DTFT的栅极连接。
本实施例中，数据写入电路2包括第四晶体管T4。
第四晶体管T4的栅极与栅线GATE连接，第四晶体管T4的第一极与复位补偿电路1中的第三晶体管T3的第一极和电容C的第一端连接，第四晶体管T4的第二极与数据线DATA连接。
本实施例中，发光控制电路3包括第五晶体管T5。
第五晶体管T5的栅极与发光控制信号线EM连接，第五晶体管T5的第一极与第一电源端连接，第五晶体管T5的第二极与驱动晶体管DTFT的第一极连接。
本实施例中，误发光控制电路4包括第六晶体管T6。
第六晶体管T6的栅极与发光控制信号线EM连接，第六晶体管T6的第一极与驱动晶体管DTFT的第二极连接，第六晶体管T6的第二极与发光器件的第一端连接。
在本实施例中，各晶体管可分别为多晶硅薄膜晶体管、非晶硅薄膜晶体管、氧化物薄膜晶体管以及有机薄膜晶体管中的一种。本实施例中，“第一极”可以指晶体管的源极，“第二极”可以指晶体管的漏极。当然，本领域的技术人员应该知晓的是，该“第一极”与“第 二极”可进行互换，即“第一极”也可指晶体管的漏极，“第二极”可以指晶体管的源极。
本实施例中，像素电路中的所有晶体管可均为P型晶体管，此时可采用的相同的制备工艺以同时制备出上述晶体管，进而缩短像素电路的生产周期。需要说明的是，像素电路中的所有晶体管均为P型薄膜晶体管仅为本实施例的一种可选方案，这并不会对本公开的技术方案产生限制。在另一个实施例中，驱动晶体管可为P型薄膜晶体管，其他晶体管(第一晶体管T1至第六晶体管T6)可选择性的设置为N型薄膜晶体管。
下面将结合附图，对本实施例提供的像素电路的工作过程进行详细描述。在下述描述中，以驱动晶体管DTFT、第一晶体管T1至第六晶体管T6均为P型薄膜晶体管为例进行说明，其中，第一电源端提供第一工作电压VDD，第二电源端提供第二工作电压VSS(例如，接地电压)，复位电源端提供复位电压Vrst，驱动晶体管DTFT的阈值电压为Vth。此外，如图2所示，连接电容C的第二端、第一晶体管T1的第一极、第二晶体管T2的第一极以及驱动晶体管DTFT的栅极的节点标记为N1，连接电容C的第一端、第三晶体管T3的第一极、第四晶体管T4的第一极的节点标记为N2，连接第二晶体管T2的第二极、驱动晶体管DTFT的第二极以及第六晶体管T6的第一极的节点标记为N3，以及连接第三晶体管T3的第二极、第五晶体管T5的第二极以及驱动晶体管DTFT的第一极的节点标记为N4。
图3为图2所示像素电路的工作时序图，如图3所示，该像素电路的工作过程包括三个阶段，即，复位补偿阶段t1、写入阶段t2和发光阶段t3。
在复位补偿阶段t1，复位控制信号线RST提供的复位控制信号处于低电平，栅线GATE提供的栅驱动信号(又称为扫描信号)处于高电平，发光控制信号线EM提供的发光控制信号处于高电平。
此时，第一晶体管T1、第二晶体管T2、第三晶体管T3均导通，第四晶体管T4、第五晶体管T5和第六晶体管T6均截止。
由于第一晶体管T1导通，复位电源端提供的复位电压Vrst通 过第一晶体管T1写入至第一节点N1，与此同时，由于第二晶体管T2导通，则第一节点N1处的复位电压Vrst通过第二晶体管T2写入至第三节点N3。此时，第四节点N4(在上一帧画面显示结束时，第四节点N4的电压为第一工作电压VDD)通过驱动晶体管DTFT进行放电，直至第四节点N4的电压为Vrst-Vth，此时驱动晶体管DTFT截止。又由于第三晶体管T3导通，则第四节点N4处的电压通过第三晶体管T3写入至第二节点N2，第二节点N2处的电压为Vrst-Vth。
此时，电容C的第一端的电压为Vrst-Vth，电容C的第二端的电压为Vrst，电容C的第一端与第二端的电压差为-Vth。
需要说明的是，由于第六晶体管T6截止，因此在第四节点N4通过驱动晶体管DTFT进行放电的过程中，驱动晶体管DTFT处输出的电流无法被传递至发光器件(例如OLED)，所以发光器件(例如OLED)不会出现误发光。
在写入阶段t2，复位控制信号线RST提供的复位控制信号处于高电平，栅线GATE提供的栅驱动信号处低电平，发光控制信号线EM提供的发光控制信号处于高电平。
此时，第四晶体管T4导通，第一晶体管T1、第二晶体管T2、第三晶体管T3、第五晶体管T5和第六晶体管T6均截止。
由于第四晶体管T4导通，则数据线DATA中的数据电压Vdata可通过第四晶体管T4写入至第二节点N2，第二节点N2处的电压由Vrst-Vth跳变为Vdata。又由于第一晶体管T1、第二晶体管T2均截止，因此第一节点N1处于浮接状态，在电容C的自举作用(保持电容C两端的电压差不变)下，第一节点N1处的电压由Vrst-Vth跳变为Vdata+Vth。
在发光阶段t3，复位控制信号线RST提供的复位控制信号处于高电平，栅线GATE提供的栅驱动信号处高电平，发光控制信号线EM提供的发光控制信号处于低电平。
此时，第五晶体管T5和第六晶体管T6均导通，第一晶体管T1、第二晶体管T2、第三晶体管T3和第四晶体管T4均截止。
由于第五晶体管T5导通，则第一工作电压VDD通过第五晶体管 T5写入至第四节点N4。驱动晶体管DTFT的栅源电压Vgs(栅极与源极的电压差)为Vdata+Vth-VDD。
根据驱动晶体管DTFT的饱和状态驱动电流公式可得：
I＝K*(Vgs-Vth) 2
＝K*(Vdata+Vth-VDD-Vth) 2
＝K*(Vdata-VDD) 2
其中，I为驱动晶体管DTFT输出的驱动电流，K为一个常量，与驱动晶体管DTFT的沟道特征相关。
通过上式可知，在发光阶段t3时，驱动晶体管DTFT输出的驱动电流与驱动晶体管DTFT的阈值电压无关，即实现了对驱动晶体管DTFT的阈值电压补偿，从而可解决因各驱动晶体管DTFT的阈值电压不同而导致显示面板发光亮度不均一的问题。
此外，通过上述内容可见，本实施例的像素电路的补偿子电路所配置的控制信号线为复位子电路中的复位控制信号线，因此无需为补偿子电路额外配置控制信号线，可有效减少像素电路所需配置的控制信号线和控制信号的种类，简化了像素电路的结构，降低了功耗。
可以理解的是，在第一晶体管T1至第六晶体管T6设置为N型薄膜晶体管的情况下，则像素电路的工作时序图可以为如图4所示。
图5为本公开的实施例提供的像素电路驱动方法的流程图，该像素电路为上述实施例提供的像素电路，该驱动方法包括以下步骤S1至S3。
步骤S1、在复位补偿阶段，通过复位补偿电路对驱动晶体管的栅极进行复位，以及获取驱动晶体管的阈值电压。
在一些实施方式中，所述复位补偿电路可包括复位子电路和补偿子电路。该情况下，步骤S1包括：子步骤S101，通过所述复位子电路将所述复位电源端所提供的复位电压写入至驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位；子步骤S102，通过所述补偿子电路将所述驱动晶体管的栅极处的复位电压写入至所述驱动晶体管的第二极，并获取所述驱动晶体管的第一极处的输出电压，所述输出电压等于复所述位电压与所述阈值电压之差。
步骤S2、在写入阶段，通过所述数据写入电路将数据电压传递至所述复位补偿电路，所述复位补偿电路将电压大小等于所述数据电压与所述阈值电压之和的发光电压写入至驱动晶体管的栅极。
步骤S3、在发光阶段，通过所述发光控制电路将第一工作电压写入至所述驱动晶体管的第一极，所述驱动晶体管根据所述发光电压和所述第一工作电压产生相应的驱动电流，以驱动所述发光器件发光。
对于上述步骤S1至S3的具体描述，可参见上述实施例中的相应内容，此处不再赘述。
本公开的实施例还提供了一种显示面板，该显示面板包括上述实施例中提供的像素电路，具体描述可参见上述实施例中的内容，此处不再赘述。根据本公开的实施例的显示面板可以是利用低温多晶硅工艺制造的OLED显示面板等。
本公开的实施例提供了一种显示装置，该显示装置包括上述实施例中提供的显示面板，具体描述可参见上述实施例中的内容，此处不再赘述。
可以理解的是，以上实施例及实施方式仅仅是为了说明本公开的技术方案的原理而采用的示例性实施例及实施方式，然而本公开的技术方案并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的技术方案的精神和实质的情况下，可以对本公开的技术方案做出各种变型和改进，这些变型和改进也视为落入本公开的保护范围内。

Claims (14)

  1. 一种像素电路，包括：复位补偿电路、数据写入电路、发光控制电路、驱动晶体管和发光器件，其中：
    所述复位补偿电路与所述驱动晶体管的栅极、所述驱动晶体管的第一极、所述驱动晶体管的第二极和复位控制信号线均连接，并且配置为响应所述复位控制信号线所提供的复位控制信号的控制，在复位补偿阶段对所述驱动晶体管的栅极进行复位、以及获取所述驱动晶体管的阈值电压；
    所述数据写入电路与所述复位补偿电路、数据线和栅线均连接，并且配置为响应于所述栅线所提供的栅驱动信号的控制，在写入阶段将所述数据线所提供的数据电压传递至所述复位补偿电路，以供所述复位补偿电路将发光电压写入至所述驱动晶体管的栅极，所述发光电压等于所述数据电压与所述阈值电压的和；
    所述发光控制电路与发光控制信号线、所述驱动晶体管的第一极、第一电源端均连接，并且配置为响应于所述发光控制信号线所提供的发光控制信号，在发光阶段将所述第一电源端所提供的第一工作电压写入至所述驱动晶体管的第一极；
    所述驱动晶体管的第二极与所述发光器件的第一端连接，所述驱动晶体管配置为在所述发光阶段根据所述发光电压和所述第一工作电压产生相应的驱动电流，以驱动所述发光器件发光；以及
    所述发光器件的第二端与第二电源端连接。
  2. 根据权利要求1所述的像素电路，其中，所述复位补偿电路包括复位子电路和补偿子电路，
    所述复位子电路与所述驱动晶体管的栅极和复位电源端连接，并且配置为在所述复位补偿阶段将所述复位电源端所提供的复位电压写入至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位，
    所述补偿子电路与所述驱动晶体管的栅极、所述驱动晶体管的 第一极、所述驱动晶体管的第二极连接，并且配置为在所述复位补偿阶段将所述驱动晶体管的栅极处的复位电压写入至所述驱动晶体管的第二极，并获取所述驱动晶体管的第一极处的等于所述复位电压与所述阈值电压之差的输出电压，以及在所述写入阶段根据接收到的所述数据电压和获取的所述阈值电压生成所述发光电压，并将所述发光电压写入至所述驱动晶体管的栅极。
  3. 根据权利要求2所述的像素电路，其中，所述复位子电路包括第一晶体管，所述第一晶体管的栅极与所述复位控制信号线连接，所述第一晶体管的第一极与所述驱动晶体管的栅极连接，所述第一晶体管的第二极与所述复位电源端连接。
  4. 根据权利要求2所述的像素电路，其中，所述补偿子电路包括第二晶体管、第三晶体管和电容，
    所述第二晶体管的栅极与所述复位控制信号线连接，所述第二晶体管的第一极与所述驱动晶体管的栅极连接，所述第二晶体管的第二极与所述驱动晶体管的第二极连接，
    所述第三晶体管的栅极与所述复位控制信号线连接，所述第三晶体管的第一极与所述电容的第一端连接，所述第三晶体管的第二极与所述驱动晶体管的第一极连接，
    所述电容的第二端与所述驱动晶体管的栅极连接。
  5. 根据权利要求4所述的像素电路，其中，所述数据写入电路包括第四晶体管，
    所述第四晶体管的栅极与所述栅线连接，所述第四晶体管的第一极与所述复位补偿电路的所述电容的第一端和所述第三晶体管的第一极连接，所述第四晶体管的第二极与所述数据线连接。
  6. 根据权利要求1所述的像素电路，其中，所述发光控制电路包括第五晶体管，所述第五晶体管的栅极与所述发光控制信号线连 接，所述第五晶体管的第一极与所述第一电源端连接，所述第五晶体管的第二极与所述驱动晶体管的第一极连接。
  7. 根据权利要求1所述的像素电路，还包括误发光控制电路，所述驱动晶体管的第二极通过所述误发光控制电路与所述发光器件的第一端连接，
    所述误发光控制电路与所述发光控制信号线连接，并且配置为响应于所述发光控制信号的控制，在所述复位补偿阶段使得所述驱动晶体管的第二极与所述发光器件的第一端之间断路，以及在所述发光阶段使得所述驱动晶体管的第二极与所述发光器件的第一端之间通路。
  8. 根据权利要求7所述的像素电路，其中，所述误发光控制电路包括第六晶体管，所述第六晶体管的栅极与所述发光控制信号线连接，所述第六晶体管的第一极与所述驱动晶体管的第二极连接，所述第六晶体管的第二极与所述发光器件的第一端连接。
  9. 根据权利要求1-8中任一项所述的像素电路，其中，所述像素电路内的所有晶体管均为P型晶体管。
  10. 一种像素电路，包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、电容、驱动晶体管和发光器件，其中，
    所述第一晶体管的第一极、所述电容的第二端、所述第二晶体管的第一极、所述驱动晶体管的栅极连接于第一节点；
    所述第三晶体管的第一极、所述电容的第一端、所述第四晶体管的第一极连接于第二节点；
    所述第二晶体管的第二极、所述驱动晶体管的第二极、所述第六晶体管的第一极连接于第三节点；
    所述驱动晶体管的第一极、所述第三晶体管的第二极和所述第 五晶体管的第二极连接于第四节点；
    所述第一晶体管的栅极、所述第二晶体管的栅极、和所述第三晶体管的栅极连接至复位控制信号线；
    所述第五晶体管的栅极和所述第六晶体管的栅极连接至发光控制信号线；
    所述第一晶体管的第二极连接至复位电源端；
    所述第四晶体管的栅极连接至栅线，所述第四晶体管的第二极连接至数据线；
    所述第五晶体管的第一极连接至第一电源端；
    所述发光器件的第一端连接至所述第六晶体管的第二极，所述发光器件的第二端连接至第二电源端。
  11. 一种显示面板，包括：如上述权利要求1-10中任一所述的像素电路。
  12. 一种显示装置，包括：如上述权利要求11中所述的显示面板。
  13. 一种像素电路驱动方法，所述像素电路为根据权利要求1所述的像素电路，所述驱动方法包括：
    在所述复位补偿阶段，通过所述复位补偿电路对所述驱动晶体管的栅极进行复位，以及获取所述驱动晶体管的阈值电压；
    在所述写入阶段，通过所述数据写入电路将所述数据电压传递至所述复位补偿电路，所述复位补偿电路将电压大小等于所述数据电压与所述阈值电压之和的所述发光电压写入至所述驱动晶体管的栅极；以及
    在所述发光阶段，通过所述发光控制电路将所述第一工作电压写入至所述驱动晶体管的第一极，所述驱动晶体管根据所述发光电压和所述第一工作电压产生相应的驱动电流，以驱动所述发光器件发光。
  14. 根据权利要求13所述的驱动方法，其中，所述复位补偿电路包括复位子电路和补偿子电路，所述复位子电路与所述驱动晶体管的栅极和复位电源端连接，所述补偿子电路与所述驱动晶体管的栅极、所述驱动晶体管的第一极、所述驱动晶体管的第二极连接，通过所述复位补偿电路对所述驱动晶体管的栅极进行复位、以及获取所述驱动晶体管的阈值电压的步骤包括：
    通过所述复位子电路将所述复位电源端所提供的复位电压写入至所述驱动晶体管的栅极，以对所述驱动晶体管的栅极进行复位；
    通过所述补偿子电路将所述驱动晶体管的栅极处的复位电压写入至所述驱动晶体管的第二极，并获取所述驱动晶体管的第一极处的输出电压，所述输出电压等于所述复位电压与所述阈值电压之差。
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