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WO2019200967A1 - 移位寄存器单元及驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2019200967A1
WO2019200967A1 PCT/CN2018/124931 CN2018124931W WO2019200967A1 WO 2019200967 A1 WO2019200967 A1 WO 2019200967A1 CN 2018124931 W CN2018124931 W CN 2018124931W WO 2019200967 A1 WO2019200967 A1 WO 2019200967A1
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WIPO (PCT)
Prior art keywords
transistor
control
circuit
input
node
Prior art date
Application number
PCT/CN2018/124931
Other languages
English (en)
French (fr)
Inventor
张洁
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
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Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/474,650 priority Critical patent/US11417256B2/en
Publication of WO2019200967A1 publication Critical patent/WO2019200967A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0283—Arrangement of drivers for different directions of scanning
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • Embodiments of the present disclosure relate to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • At least one embodiment of the present disclosure provides a shift register unit including: a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit.
  • the first input sub-circuit is connected to the first input end, the first control signal end and the first control sub-circuit, and the first input sub-circuit is configured to be under the control of the first input signal of the first input end Outputting a first control signal of the first control signal end to the first control sub-circuit;
  • the first control sub-circuit is connected to a second input end, a first node, and the second control sub-circuit,
  • the first control sub-circuit is configured to output the second input signal of the second input terminal to the first node under control of the first control signal output by the first input sub-circuit; or the first a control subcircuit configured to output the second input signal to the second control subcircuit;
  • the output subcircuit is coupled to the first node and an output, the output subcircuit configured
  • a shift register unit provided by an embodiment of the present disclosure further includes a noise reduction sub-circuit.
  • the noise reduction sub-circuit is connected to the second node, the first node, the first voltage end, and the output end, and the noise reduction sub-circuit is configured to control the level of the second node And outputting the first voltage of the first voltage terminal to the first node and the output end.
  • the first input sub-circuit includes a first transistor.
  • a gate of the first transistor is connected to the first input terminal to receive the first input signal, and a first pole of the first transistor is connected to the first control signal terminal to receive the first control signal,
  • the second pole of the first transistor is connected to the first control sub-circuit as an output of the first input sub-circuit.
  • the first control sub-circuit includes a second transistor and a third transistor.
  • a gate of the second transistor is coupled to an output of the first input sub-circuit, and a first electrode of the second transistor is coupled to the second input to receive the second input signal, the second transistor a second pole is connected to the control node;
  • a gate of the third transistor and a first pole are electrically connected to each other, and are respectively configured to be connected to the control node, and a second pole of the third transistor is connected to the first pole One node.
  • the output sub-circuit includes a fourth transistor and a first capacitor.
  • a gate of the fourth transistor is connected to the first node, a first pole of the fourth transistor is connected to the first clock signal terminal to receive a first clock signal as the output signal, and a second transistor is a second The pole is connected to the output end; the first end of the first capacitor is connected to the first node, and the second end of the first capacitor is connected to the output end.
  • the second control sub-circuit includes a fifth transistor, a sixth transistor, and a second capacitor.
  • the gate and the first pole of the fifth transistor are electrically connected to each other, and are respectively configured to be connected to the second clock signal terminal to receive the second clock signal, and the second pole of the fifth transistor is connected to the a second node;
  • a gate of the sixth transistor is connected to the control node, a first pole of the sixth transistor is connected to the second node, and a second pole of the sixth transistor is connected to the first voltage end Receiving the first voltage;
  • a first end of the second capacitor is connected to the second node, and a second end of the second capacitor is connected to the first voltage end to receive the first voltage.
  • the noise reduction sub-circuit includes a seventh transistor and an eighth transistor.
  • a gate of the seventh transistor is connected to the second node, a first pole of the seventh transistor is connected to the first node, and a second pole of the seventh transistor is connected to the first voltage terminal to receive a first voltage;
  • a gate of the eighth transistor is connected to the second node, a first pole of the eighth transistor is connected to the output end, and a second pole of the eighth transistor is connected to the first voltage End to receive the first voltage.
  • a shift register unit provided by an embodiment of the present disclosure further includes a second input sub-circuit.
  • the second input sub-circuit is connected to the third input end, the fourth input end, the second control signal end and the control node, and the second input sub-circuit is configured as a third input signal at the third input end and And outputting, by the second control signal of the second control signal end, the fourth input signal of the fourth input terminal to the control node.
  • the second input sub-circuit includes a ninth transistor and a tenth transistor.
  • a gate of the ninth transistor is connected to the third input terminal to receive the third input signal, and a first pole of the ninth transistor is connected to the second control signal terminal to receive the second control signal, a second pole of the ninth transistor is connected to a gate of the tenth transistor; a first pole of the tenth transistor is connected to the fourth input terminal to receive the fourth input signal, the tenth transistor The second pole is connected to the control node.
  • At least one embodiment of the present disclosure also provides a shift register unit including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor.
  • a gate of the first transistor is coupled to the first input terminal to receive a first input signal
  • a first pole of the first transistor is coupled to the first control signal terminal to receive a first control signal
  • a second of the first transistor a pole connected to a gate of the second transistor
  • a first pole of the second transistor coupled to the second input to receive a second input signal
  • a second pole of the second transistor coupled to a gate of the third transistor a first pole of the third transistor and a gate of the sixth transistor
  • a second pole of the third transistor is connected to the first node
  • a gate of the fourth transistor is connected to the first node
  • a first pole of the fourth transistor is connected to the first clock signal terminal to receive the first clock signal
  • a second pole of the fourth transistor is connected to the
  • the fifth transistor a second pole is connected to the second node; a first pole of the sixth transistor is connected to the second node, a second pole of the sixth transistor is connected to the first voltage terminal to receive the first voltage; One end is connected to the second node, and the second end of the second capacitor is connected to the first voltage end to receive the first voltage.
  • a shift register unit provided by an embodiment of the present disclosure further includes a seventh transistor and an eighth transistor.
  • a gate of the seventh transistor is connected to the second node, a first pole of the seventh transistor is connected to the first node, and a second pole of the seventh transistor is connected to the first voltage terminal to receive a first voltage;
  • a gate of the eighth transistor is connected to the second node, a first pole of the eighth transistor is connected to the output end, and a second pole of the eighth transistor is connected to the first voltage End to receive the first voltage.
  • a shift register unit provided by an embodiment of the present disclosure further includes a ninth transistor and a tenth transistor.
  • a gate of the ninth transistor is connected to the third input terminal to receive a third input signal
  • a first pole of the ninth transistor is connected to the second control signal terminal to receive a second control signal
  • a second of the ninth transistor a pole connected to the second pole of the first transistor, a gate of the second transistor, and a gate of the tenth transistor
  • a first pole of the tenth transistor is connected to the fourth input terminal to receive the fourth input signal
  • a second pole of the tenth transistor is coupled to a gate of the third transistor, a first pole of the third transistor, and a gate of the sixth transistor.
  • the first transistor to the tenth transistor are both N-type transistors or both P-type transistors.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: an input stage, the first input sub-circuit will be the first under the control of the first input signal of the first input end a first control signal of the control signal end is output to the first control sub-circuit; under the control of the second clock signal of the second clock signal end, the pull-down control sub-circuit sets a second clock of the second clock signal end a signal signal is output to the second node; in a pre-charging phase, the first control sub-circuit outputs a second input signal of the second input terminal under the control of the first control signal output by the first input sub-circuit The first control sub-circuit further outputs a second input signal of the second input terminal to the second control sub-circuit, under the control of the second input signal of the second input end, The second control sub-circuit outputs a first voltage of the first voltage terminal to the second node; an output stage, under the control of a level of the first node, the output sub-circuit
  • the shift register unit further includes a noise reduction sub-circuit
  • the driving method further includes a reset phase.
  • the noise reduction sub-circuit In the input phase, under the control of the level of the second node, the noise reduction sub-circuit outputs a first voltage of the first voltage terminal to the first node and the output terminal; a second control sub-circuit outputting the second clock signal to the second node under control of a second clock signal of the second clock signal terminal; at a level of the second node Under control, the noise reduction sub-circuit outputs a first voltage of the first voltage terminal to the first node and the output terminal.
  • At least one embodiment of the present disclosure also provides a driving method of a shift register unit, including: an input stage, the second input sub-circuit outputs the second under the control of a third input signal of the third input end a second control signal of the control signal end; the second control sub-circuit outputs the second clock signal signal of the second clock signal end to the second control under the control of the second clock signal of the second clock signal end a pre-charging phase, the second input sub-circuit outputs a fourth input signal of the fourth input to the control node under control of the second control signal, and controls the level of the control node
  • the first control sub-circuit outputs a fourth input signal of the fourth input terminal to the first node; the first control sub-circuit further outputs a fourth input signal of the fourth input terminal to the a second control sub-circuit, the second control sub-circuit outputs a first voltage of the first voltage terminal to the second node under control of a fourth input signal of the fourth input end
  • the output stage under the control of the level
  • At least one embodiment of the present disclosure further provides a gate driving circuit including a plurality of cascaded shift register units provided by any one of the embodiments of the present disclosure; a first stage shift register unit and a second stage shift register unit The first input terminal is connected to the first signal terminal; the first input terminal of the Nth stage shift register unit is connected to the N-2th stage except the first stage shift register unit and the second stage shift register unit An output terminal of the shift register unit; a second input terminal of the first stage shift register unit is coupled to the second signal terminal; wherein the Nth stage shift register unit is other than the first stage shift register unit The second input is coupled to the output of the N-1th stage shift register unit; wherein N is an integer greater than or equal to 3.
  • the shift register unit includes the second input sub-circuit or includes the ninth transistor and the tenth transistor, except for the last two stages of shift registers
  • the third input of the Nth stage shift register unit is coupled to the output of the N+2 stage shift register unit; the Nth stage shift register unit except for the last stage shift register unit
  • the fourth input terminal is connected to the output end of the N+1th stage shift register unit; wherein the third input end of the last two stages of the shift register unit is connected to the first signal end, and the last stage shift A fourth input of the register unit is coupled to the second signal terminal.
  • At least one embodiment of the present disclosure further provides a display device including a gate driving circuit provided by any embodiment of the present disclosure.
  • 1 is a circuit diagram of a conventional GOA unit
  • FIG. 2 is a block diagram of a shift register unit according to an embodiment of the present disclosure
  • FIG. 3 is a circuit configuration diagram of the shift register unit shown in FIG. 2;
  • FIG. 4 is a timing control diagram of the shift register unit shown in FIG. 3;
  • FIG. 5 is a block diagram of the shift register unit shown in FIG. 2 including a second input sub-circuit
  • FIG. 6 is a circuit configuration diagram of the shift register unit shown in FIG. 3 including a second input sub-circuit
  • FIG. 7 is a structural diagram of a plurality of gate drive circuits formed by cascading shift register units as shown in FIG. 3;
  • FIG. 8 is a structural diagram of a plurality of gate drive circuits formed by cascading shift register units as shown in FIG. 6;
  • FIG. 9 is a timing chart of a clock signal of the gate driving circuit shown in FIG. 7 or FIG. 8;
  • FIG. 10 is a schematic diagram of a display device according to an embodiment of the present disclosure.
  • FIG. 1 is a circuit diagram of a GOA unit.
  • each transistor in the GOA cell is an N-type transistor
  • the first input terminal INPUT1 is at a high level, so that the first transistor T1 is turned on, and at this time, the first node PU is charged, and under the control of the first node PU, the fifth transistor T5 Turning on, so that the second node PD is connected to the low voltage terminal VGL; meanwhile, in this phase, the clock signal terminal CKB provides a high level, so that the fourth transistor T4 is turned on, and the high level output provided by the clock signal terminal CKB is turned to the second Node PD.
  • a DC path is formed.
  • the high level of the first node PU is used to pull down the level of the second node PD by controlling the fifth transistor T5 to be turned on, and the fourth transistor T4 is at the second clock signal end CKB.
  • the second node PD may be at a high level, and the sixth transistor T6 is responsive to the second node.
  • the high level of the PD is turned on, thereby pulling down the high level of the first node PU, so that the potentials of the first node PU and the second node PD compete with each other.
  • the above-mentioned DC path leads to an increase in power consumption of the gate driving circuit including a plurality of cascaded GOA units; on the other hand, the DC path is a bad phenomenon of the GOA unit, which may lower the clock signal.
  • the voltage of the CKB causes insufficient charging of the second node PD, resulting in the GOA unit of the stage not working properly, thereby reducing the stability of the GOA unit.
  • An embodiment of the present disclosure provides a shift register unit including a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit.
  • the first input sub-circuit is connected to the first input end, the first control signal end and the first control sub-circuit, and the first input sub-circuit is configured to control the first control signal end under the control of the first input signal of the first input end a control signal is output to the first control sub-circuit;
  • the first control sub-circuit is coupled to the second input, the first node and the second control sub-circuit, the first control sub-circuit being configured as a first control output at the first input sub-circuit Controlling, by the signal, outputting the second input signal of the second input terminal to the first node; or, the first control sub-circuit is configured to output the second input signal to the second control sub-circuit;
  • the output sub-circuit is connected to the first node and The output terminal is configured to output an output signal to the
  • Embodiments of the present disclosure provide a shift register unit that can avoid a phenomenon in which potentials of a first node and a second node compete with each other during operation, thereby reducing gate drive of a shift register unit including the plurality of cascades
  • the power consumption of the circuit improves the stability of the circuit structure.
  • Embodiments of the present disclosure provide a shift register unit (also referred to as a GOA unit) including: a first input sub-circuit, a first control sub-circuit, an output sub-circuit, and a second control sub-circuit.
  • the shift register unit 100 includes a first input sub-circuit 10, a pull-up control sub-circuit 20, an output sub-circuit 30, and a pull-down control sub-circuit 40.
  • the pull-up control sub-circuit 20 in the embodiment of the present disclosure is an example of the first control sub-circuit
  • the pull-down control sub-circuit 40 is an example of the second control sub-circuit
  • the first control sub-circuit is The pull-up control sub-circuit 20 and the second control sub-circuit.
  • the embodiments of the present disclosure are not limited thereto, and the following embodiments are the same, and are not described again.
  • the first input sub-circuit 10 is connected to the first input terminal INPUT1, the first control signal terminal CN and the pull-up control sub-circuit 20, and the first input sub-circuit 10 is configured to be controlled by the first input signal at the first input terminal INPUT1.
  • the first control signal of the first control signal terminal CN is output to the pull-up control sub-circuit 20, thereby controlling the pull-up control sub-circuit 20 to be turned on.
  • the pull-up control sub-circuit 20 is connected to the second input terminal INPUT2, the first node PU, and the pull-down control sub-circuit 40.
  • the pull-up control sub-circuit 20 is configured to be turned on under the control of the first control signal output by the first input sub-circuit 10, and to connect the second input terminal INPUT2 with the first node PU, thereby placing the second input terminal INPUT2
  • the second input signal is output to the first node PU to charge (eg, pull up) the first node PU; or the pull-up control sub-circuit 20 is configured as the first control outputted by the first input sub-circuit 10
  • the second input terminal INPUT2 is connected to the pull-down control sub-circuit 40, so that the second input signal of the second input terminal INPUT2 is output to the pull-down control sub-circuit 40, so that the pull-down control sub-circuit 40 responds.
  • the second input signal is turned on, so that the first node PU is connected to the first voltage terminal VGL or a separately provided voltage terminal (for example, a low voltage terminal, providing a low level signal).
  • the first voltage terminal VGL can be configured, for example, to maintain an input DC low level signal, for example, the DC low level signal is referred to as a first voltage.
  • the output sub-circuit 30 is connected to the first node PU and the output terminal OUT, and the output sub-circuit 30 is configured to output an output signal to the output terminal OUT under the control of the level of the first node PU.
  • the output sub-circuit 30 is connected to the first clock signal terminal CK, the first node PU, and the output terminal OUT, and is configured to be turned on under the control of the level of the first node PU such that the first clock signal terminal CK and the output The terminal is connected so that the first clock signal of the first clock signal terminal CK can be output as an output signal to the output terminal OUT.
  • the pull-down control sub-circuit 40 is connected to the second input terminal INPUT2 through the pull-up control sub-circuit 20.
  • the pull-down control sub-circuit 40 is connected to the second clock signal terminal CKB, the second node PD, the control node PUCN, and the first voltage terminal VGL, and the pull-down control sub-circuit 40 is configured as a second clock signal at the second clock signal terminal CKB. Part of the control is turned on, so that the second clock signal terminal CKB is connected to the second node PD, thereby outputting the second clock signal of the second clock signal terminal CKB to the second node PD to charge the second node PD to the high power.
  • the pull-down control sub-circuit 40 is configured to be partially turned on under the control of the level of the control node PUCN (ie, the second input signal of the second input terminal INPUT2) such that the second node PD and the first voltage terminal VGL or A separately provided voltage terminal (for example, a low voltage terminal, providing a low level signal) is connected to output the first voltage of the first voltage terminal VGL to the second node PD.
  • the second clock signal terminal CKB is second.
  • the clock signal and the first voltage of the first voltage terminal VGL are time-divisionally controlled to the second node PD, thereby preventing the pull-down control sub-circuit 40 from being fully turned on to cause a DC path from the second clock signal terminal CKB to the first voltage terminal VGL.
  • the power consumption of the gate driving circuit including the plurality of cascaded shift register units can be reduced, and the stability of the circuit structure can be improved.
  • the shift register unit 100 also includes a noise reduction sub-circuit.
  • the shift register unit 100 further includes a pull-down sub-circuit 50.
  • the pull-down sub-circuit 50 is an example of the noise reduction sub-circuit.
  • the following uses the noise reduction sub-circuit as the pull-down sub-circuit 50 as an example.
  • embodiments of the present disclosure are not limited thereto, and the following embodiments The same, no longer repeat them.
  • the pull-down sub-circuit 50 is connected to the second node PD, the first node PU, the first voltage terminal VGL and the output terminal OUT, and the pull-down sub-circuit 50 is configured to be turned on under the control of the level of the second node PD, so that the first node The PU and the output terminal OUT are connected to the first voltage terminal VGL, thereby outputting the first voltage of the first voltage terminal VGL to the first node PU and the output terminal OUT to achieve noise reduction.
  • the shift register unit provided by the embodiment of the present disclosure, in the input stage, under the control of the first input signal of the first input terminal INPUT1, the first input sub-circuit 10 will first control the first control signal terminal CN Outputting to the pull-up control sub-circuit 20; under the control of the second clock signal of the second clock signal terminal CKB, the pull-down control sub-circuit 40 outputs the second clock signal of the second clock signal terminal CKB to the second node PD; Under the control of the level of the two-node PD, the pull-down sub-circuit 50 outputs the first voltage of the first voltage terminal to the first node PU to achieve noise reduction.
  • the pull-up control sub-circuit 20 In the pre-charging phase, under the control of the first control signal output by the first input sub-circuit 10, the pull-up control sub-circuit 20 outputs the second input signal of the second input terminal INPUT2 to the first node PU; the pull-up controller The circuit 20 also outputs a second input signal of the second input terminal INPUT2 to the pull-down control sub-circuit 40. Under the control of the second input signal of the second input terminal INPUT2, the pull-down control sub-circuit 40 sets the first voltage terminal VGL. A voltage is output to the second node PD, thereby pulling down the level of the second node PD to ensure normal charging of the first node PU at this stage.
  • the high-level signal provided by the second clock signal terminal CKB can be input to the second node PD, and the first voltage of the first voltage terminal VGL can be input to the second node in the pre-charging phase.
  • PD therefore, there is no case where the high level of the clock signal terminal CKB and the low level of the first voltage terminal VGL form a DC path, that is, the occurrence of the circuit in which the potentials of the first node PU and the second node PD compete with each other is avoided.
  • the problem of increased power consumption can also improve the stability of the shift register unit.
  • the first input sub-circuit 10 includes a first transistor T1, the gate of the first transistor T1 is connected to the first input terminal INPUT1 to receive the first input signal, and the first pole of the first transistor T1 is connected to the first control signal terminal CN to receive the first A control signal, the second pole of the first transistor T1 is connected to the pull-up control sub-circuit 20 as an output of the first input sub-circuit 10.
  • the first input signal provided by the first input terminal INPUT1 is an active level
  • the first transistor is turned on, so that the pull-up control sub-circuit 20 is connected to the first control signal terminal CN, so that the first control signal terminal CN can be
  • the first control signal provided is turned on under the control of the control signal.
  • the pull-up control sub-circuit 20 includes a second transistor T2 and a third transistor T3.
  • the gate of the second transistor T2 is connected to the output end of the first input sub-circuit 10, that is, the second pole of the first transistor T1 is connected, and the second transistor T2 is connected.
  • the first pole is connected to the second input terminal INPUT2 to receive the second input signal
  • the second pole of the second transistor T2 is connected to the control node PUCN, that is, the gate of the third transistor T3, the first pole of the third transistor T3, and the pull-down Controlling the sub-circuit 40, that is, the gate of the sixth transistor T6 in FIG. 3; for example, the gate and the first pole of the third transistor are electrically connected to each other, and are respectively configured to be connected to the control node PUCN, and the second of the third transistor T3 The pole is connected to the first node PU.
  • the output sub-circuit 30 includes a fourth transistor T4 and a first capacitor C1; the gate of the fourth transistor T4 is connected to the first node PU, and the first pole of the fourth transistor T4 is connected to the first clock signal terminal CK to receive the first clock signal.
  • the output terminal, the second terminal of the fourth transistor T4 is connected to the output terminal OUT; the first end of the first capacitor C1 is connected to the first node PU, and the second end of the first capacitor C1 is connected to the output terminal OUT.
  • the pull-down control sub-circuit 40 includes a fifth transistor T5, a sixth transistor T6, and a second capacitor C2; the gate and the first pole of the fifth transistor T5 are electrically connected to each other, and are respectively configured to be connected to the second clock signal terminal CKB to receive a second clock signal, a second pole of the fifth transistor T5 is connected to the second node PD; a gate of the sixth transistor T6 is connected to the control node PUCN (ie, the pull-up control sub-circuit 20), and the first pole of the sixth transistor T6 is connected.
  • PUCN ie, the pull-up control sub-circuit 20
  • the second pole of the sixth transistor T6 is connected to the first voltage terminal VGL to receive the first voltage; the first end of the second capacitor C2 is connected to the second node PD, and the second end is connected to the first voltage terminal VGL to receive the first A voltage.
  • the fifth transistor T5 is turned on, so that the second node PD and the second clock signal terminal CKB are connected, thereby charging the second node PD to a high level;
  • the control node PUCN is active
  • the sixth transistor T6 is turned on, so that the second node PD and the first voltage terminal VGL are connected, thereby pulling the second node PD to a low level.
  • the second clock signal terminal CKB is second.
  • the second signal PD is controlled by the clock signal and the first voltage division of the first voltage terminal VGL.
  • the second clock signal terminal CKB provides a high level, so that the fifth transistor T5 is turned on, thereby inputting the high level of the second clock signal to the second node PD, and storing it in the second capacitor C2.
  • the second clock signal terminal CKB provides a low level
  • the sixth transistor T6 is turned on under the control of the high level of the control node PUCN, thereby connecting the second node PD and the first voltage terminal VGL, thereby pulling The level of the second node PD is low.
  • the fifth transistor T5 and the sixth transistor T6 are turned on in the input phase and the pre-charging phase, so that the fifth transistor T5 and the sixth transistor T6 can be prevented from being simultaneously turned on by the second clock signal terminal CKB to the first.
  • the DC path of the voltage terminal VGL can reduce the power consumption of the gate driving circuit including the plurality of cascaded shift register units, thereby improving the stability of the circuit structure.
  • the pull-down sub-circuit 50 includes a seventh transistor T7 and an eighth transistor T8; the gate of the seventh transistor T7 is connected to the second node PD, the first pole of the seventh transistor T7 is connected to the first node PU, and the second pole of the seventh transistor T7 Connecting the first voltage terminal VGL to receive the first voltage; the gate of the eighth transistor T8 is connected to the second node PD, the first electrode of the eighth transistor T8 is connected to the output terminal OUT, and the second electrode of the eighth transistor T8 is connected to the first voltage The terminal VGL receives the first voltage.
  • the first node PU, the second node PD, and the control node PUCN do not represent components that actually exist, but represent convergence points of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may each be a thin film transistor, a field effect transistor, or other switching device having the same characteristics.
  • a thin film transistor is taken as an example for description.
  • the source and drain of the transistor used here may be structurally symmetrical, so that the source and the drain may be structurally indistinguishable.
  • the embodiment of the present disclosure in order to distinguish the two poles of the transistor except the gate, one of the first poles and the other pole are directly described.
  • the embodiment of the present disclosure does not limit the nth (n is an integer greater than or equal to 1) transistor as one transistor, which may be a series connection of a plurality of transistors, and the example in which the nth transistor includes one transistor is illustrated in FIG. .
  • the transistors may be P-type transistors or both N-type transistors.
  • the first source is the first source and the second terminal is the drain.
  • the above transistors are all N-type transistors, their first extreme drain and the second extreme source.
  • the embodiment of the present disclosure is described by taking each transistor as an N-type transistor as an example, and the first voltage terminal VGL outputs a constant low level.
  • pulse-up means charging one node or one electrode of a transistor such that the level of the node or the electrode is absolute. The value is increased to achieve the operation of the corresponding transistor (eg, conduction); “pull-down” means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby achieving corresponding Operation of the transistor (eg cut-off).
  • pulse-up means discharging one electrode of one node or one transistor, so that the absolute value of the level of the node or the electrode is lowered, thereby implementing the corresponding transistor.
  • Operation eg, conduction
  • pulse-down means charging one node or one electrode of a transistor to increase the absolute value of the level of the node or the electrode to achieve operation of the corresponding transistor (eg, cutoff) .
  • the working process of the shift register unit shown in FIG. 3 is specifically described below with reference to FIG. 4.
  • the working process of the shift register unit includes: an input phase P1, a precharge phase P2, an output phase P3, and Reset phase P4.
  • the first input terminal INPUT1 provides a high level (ie, the first input signal is a high level), and the second clock signal terminal CKB provides a high level (ie, the second clock signal is a high level), at the first
  • the first input sub-circuit 10 outputs the signal of the first control signal terminal CN to the pull-up control sub-circuit 20; under the control of the high level of the second clock signal terminal CKB, the pull-down
  • the control sub-circuit 40 outputs a high-level signal of the second clock signal terminal CKB to the second node PD to charge the second node PD; under the control of the level of the second node PD, the pull-down sub-circuit 50 will be the first
  • the first voltage of the voltage terminal VGL is output to the first node PU to avoid charging the first node PU at this stage.
  • “1" indicates a high level
  • "0" indicates a low level.
  • the first transistor T1 under the control of the high level of the first input terminal INPUT1, the first transistor T1 is turned on, and the first control signal of the first control signal terminal CN is output to the gate of the second transistor T2 through the first transistor T1.
  • a second transistor T2 is turned on, and a low level of the second input terminal INPUT2 is output to the control node PUCN through the second transistor T2.
  • the third transistor T3 and the sixth transistor T6 are in an off state.
  • the fifth transistor T5 is turned on under the control of the second clock signal of the second clock signal terminal CKB, and the second clock signal provided by the second clock signal terminal CKB charges the second node PD through the fifth transistor T5, thereby Node PD is high.
  • the seventh transistor T7 and the eighth transistor T8 are turned on, and the first voltage of the first voltage terminal VGL is output to the output terminal OUT through the seventh transistor T7 and the eighth transistor T8, respectively.
  • the first node PU under the control of the first node PU, the fourth transistor T4 is in an off state, so that at this stage, the output terminal OUT outputs a low level.
  • the fifth transistor T5 is turned on, and the sixth transistor T6 is turned off, which avoids the occurrence of the fifth clock signal terminal CKB to the first when the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on.
  • a DC path ie, a short circuit
  • the shift register unit including the plurality of cascades can be reduced
  • the power consumption of the gate drive circuit improves the stability of the circuit structure.
  • the second input terminal INPUT2 provides a high level
  • the first clock signal terminal CK provides a low level.
  • the first control signal outputted by the first input sub-circuit 10 can be maintained to the pre-charging phase P2, thereby Under the control of the first control signal output by the first input sub-circuit 10, the pull-up control sub-circuit 20 outputs the high level (ie, the second input signal) of the second input terminal INPUT2 to the first node PU to The one-node PU is charged to the first high level; the pull-up control sub-circuit 20 also outputs the high level of the second input terminal INPUT2 to the pull-down control sub-circuit 40, under the control of the high level of the second input terminal INPUT2, The pull-down control sub-circuit 40 outputs the first voltage of the first voltage terminal VGL to the second node PD, thereby pulling down the level of the second node PD to avoid its influence on the charging of the first node PD.
  • INPUT1 0
  • CK 0
  • PUCN 1
  • the first transistor T1 under the control of the high level of the first input terminal INPUT1, the first transistor T1 is turned off; the high level of the second input terminal INPUT2 is output to the control node PUCN through the second transistor T2, at the control node PUCN.
  • the third transistor T3 and the sixth transistor T6 are turned on.
  • the high level of the control node PUCN is output to the first node PU through the third transistor T3.
  • the fourth transistor T4 Under the control of the level of the first node PU, the fourth transistor T4 is turned on, and the low level of the first clock signal terminal CK passes.
  • the four transistor T4 is output to the output terminal OUT, so that at this stage, the output terminal OUT outputs a low level.
  • the first voltage of the first voltage terminal VGL is output to the second node PD through the sixth transistor T6, and the seventh transistor T7 and the eighth transistor T8 are turned off under the control of the level of the second node PD.
  • the fifth transistor T5 is turned off under the control of the low level of the second clock signal terminal CKB.
  • the fifth transistor T5 is turned off, and the sixth transistor T6 is turned on, avoiding the simultaneous occurrence of the fifth transistor T5 and the sixth transistor T6 being simultaneously turned on by the second clock signal terminal CKB to the first a DC path (ie, a short circuit) of the voltage terminal VGL, thereby avoiding the problem that the potentials of the first node PU and the second node PD compete with each other due to the DC path, and therefore, the shift register unit including the plurality of cascades can be reduced
  • the power consumption of the gate drive circuit improves the stability of the circuit structure. Since the first clock signal terminal CK supplies a low level, in this phase, the output terminal OUT does not output a gate line scan signal.
  • Output phase P3 The first clock signal terminal CK provides a high level. Under the control of the level of the first node PU, the output sub-circuit 30 outputs the high level of the first clock signal terminal CK to the output terminal OUT.
  • the low level of the second input terminal INPUT2 is output to the node PUCN through the second transistor T2, and the third transistor T3 and the sixth transistor T6 are turned off under the control of the level of the node PUCN.
  • the fourth transistor T4 is turned on, and the high level of the first clock signal terminal CK is output to the output terminal OUT through the fourth transistor T4; due to the bootstrap action of the first capacitor C1, The potential of the first node PU is further increased and charged to a second high level.
  • the states of the first transistor T1, the fifth transistor T5, the seventh transistor T7, and the eighth transistor T8 are the same as the pre-charging phase, and are not described herein again.
  • the output terminal OUT outputs a gate line scan signal in this stage.
  • the reset phase P4 the second clock signal terminal CKB provides a high level, and under the control of the high level of the second clock signal terminal CKB, the pull-down control sub-circuit 40 outputs the high level of the second clock signal terminal CKB to the second level.
  • the node PD thereby charging the second node PD to a high level; under the control of the level of the second node PD, the pull-down sub-circuit 50 outputs the first voltage of the first voltage terminal VGL to the first node PU and the output terminal OUT .
  • the fifth transistor T5 under the control of the level of the second clock signal terminal CKB, the fifth transistor T5 is turned on, and the high level of the second clock signal terminal CKB is output to the second node PD through the fifth transistor T5, and is stored.
  • the second node PD In the second capacitor C2, the second node PD is maintained at a high level; under the control of the second node PD, the seventh transistor T7 and the eighth transistor T8 are turned on, and the first voltage of the first voltage terminal VGL passes through The seven-transistor T7 is output to the first node PU, and the first voltage of the first voltage terminal VGL is output to the output terminal OUT through the eighth transistor T8, thereby realizing resetting of the first node PU and the output terminal OUT.
  • the fourth transistor T4 is turned off under the control of the level of the first node PU. Further, the first transistor T1, the second transistor T2, and the third transistor T3 are in an off state.
  • the fifth transistor T5 is turned off, and under the action of the second capacitor C2, the second node PD remains at a high level, so that at the second node PD Under the control of the level, the potentials of the first node PU and the output terminal OUT are maintained at a low level to ensure the normal output of the shift register unit.
  • the shift register unit since the fifth register T5 and the sixth transistor T6 are turned on in a period of time during operation, the shift register unit provided in the embodiment of the present disclosure avoids the occurrence of the second clock signal end when both are turned on. a DC path of the CKB to the first voltage terminal VGL, and avoiding the problem that the potentials of the first node PU and the second node PD compete with each other, so that the second node PD has higher charging efficiency and the voltage of the first node PU is more stable, thereby The stability of the shift register unit is improved.
  • the shift register unit provided by the embodiment of the present disclosure may further include a second input sub-circuit 60, and a second input sub-circuit.
  • 60 is connected to the third input terminal INPUT3, the fourth input terminal INPUT4, the second control signal terminal CNB and the control node PUCN, the second input sub-circuit 60 is configured as a third input signal at the third input terminal INPUT3 and the second control
  • the fourth input signal of the fourth input terminal INPUT4 is output to the control node PUCN under the control of the second control signal of the signal terminal CNB.
  • the second input sub-circuit 60 includes a ninth transistor T9 and a tenth transistor T10, and a gate of the ninth transistor T9 is connected to the third input terminal INPUT3 to receive a third input signal, and the ninth transistor T9
  • the first pole is connected to the second control signal terminal CNB to receive the second control signal
  • the second pole of the ninth transistor T9 is connected to the gate of the tenth transistor T10.
  • the first pole of the tenth transistor T10 is connected to the fourth input terminal INPUT4 to receive the fourth input signal
  • the second pole of the tenth transistor T10 is connected to the control node PUCN.
  • the gate driving circuit formed by the cascade of the shift registers can implement forward scanning and reverse scanning.
  • the first control signal terminal CN and the second control signal terminal CNB are used as forward scanning and inverse.
  • the sixth is used for reverse scanning, in the input phase, the first input sub-circuit 10 does not operate, and the second input sub-circuit 20 operates, that is, the third input signal at the third input terminal INPUT3 and Under the control of the fourth input signal of the fourth input terminal INPUT4, the ninth transistor T9 and the tenth transistor T10 are turned on, and the second control signal terminal CNB is connected to the gate of the tenth transistor T10, so that the second control signal terminal CNB
  • the second control signal is output to the gate of the tenth transistor T10 through the ninth transistor T9, thereby controlling the tenth transistor T10 to be turned on, and inputting the fourth input signal input by the fourth input terminal INPUT4 to the control node PUCN, thereby controlling the third
  • the transistor T3 is turned on; the operation process of the other sub-circuits is the same as the foregoing, and details are not described herein again.
  • each transistor is an N-type transistor as an example, and those skilled in the art can understand that when each transistor is a P-type, only the respective ones in FIG. 4 are needed. The timing signal is reversed, which is not described in this embodiment.
  • the embodiment of the present disclosure provides a control method of a shift register unit as described in the foregoing embodiment. As shown in FIG. 4, the method includes an input phase P1, a precharge phase P2, an output phase P3, and a reset phase P4.
  • the first input terminal INPUT1 provides a high level (ie, the first input signal is high level), and the second clock signal terminal CKB provides a high level, under the control of the high level of the first input terminal INPUT1,
  • the first input sub-circuit 10 outputs a high level signal of the first control signal terminal CN to the pull-up control sub-circuit 20; under the control of the high level of the second clock signal terminal CKB, the pull-down control sub-circuit 40 sets the second clock.
  • the high level signal of the signal terminal CKB is output to the second node PD; under the control of the level of the second node PD, the pull-down sub-circuit 50 outputs the first voltage of the first voltage terminal VGL to the first node PU.
  • the second input terminal INPUT2 provides a high level
  • the first clock signal terminal CK provides a low level.
  • the first control signal outputted by the first input sub-circuit 10 can be maintained to the pre-charging phase P2, thereby Under the control of the first control signal outputted by the first input sub-circuit 10, the pull-up control sub-circuit 20 outputs a high-level signal of the second input terminal INPUT2 to the first node PU; the pull-up control sub-circuit 20 will also The high level signal of the two input terminals INPUT2 is output to the pull-down control sub-circuit 40. Under the control of the high-level signal of the second input terminal INPUT2, the pull-down control sub-circuit 40 outputs the first voltage of the first voltage terminal VGL to the first Two-node PD.
  • Output phase P3 The first clock signal terminal CK provides a high level. Under the control of the level of the first node PU, the output sub-circuit 30 outputs a high level signal of the first clock signal terminal CK to the output terminal OUT.
  • the reset phase P4 the second clock signal terminal CKB provides a high level, and under the control of the high level of the second clock signal terminal CKB, the pull-down control sub-circuit 40 outputs the high level signal of the second clock signal terminal CKB to the first The two-node PD; under the control of the level of the second node PD, the pull-down control sub-circuit 40 outputs the first voltage of the first voltage terminal VGL to the first node PU and the output terminal OUT.
  • the control method of the shift register unit in the input stage, under the control of the first input signal of the first input terminal INPUT1, the first input sub-circuit 10 will be the first control signal terminal CN
  • the first control signal is output to the pull-up control sub-circuit 20; under the control of the second clock signal of the second clock signal terminal CKB, the pull-down control sub-circuit 40 outputs the second clock signal of the second clock signal terminal CKB to the second node.
  • PD under the control of the level of the second node PD, the pull-down sub-circuit 50 outputs the first voltage of the first voltage terminal to the first node PU.
  • the pull-up control sub-circuit 20 In the pre-charging phase, under the control of the first control signal output by the first input sub-circuit 10, the pull-up control sub-circuit 20 outputs the second input signal of the second input terminal INPUT2 to the first node PU; the pull-up controller The circuit 20 also outputs a second input signal of the second input terminal INPUT2 to the pull-down control sub-circuit 40. Under the control of the second input signal of the second input terminal INPUT2, the pull-down control sub-circuit 40 sets the first voltage terminal VGL. A voltage is output to the second node PD so that the level of the second node PD can be pulled down to ensure normal charging of the first node PU at this stage.
  • the problem that the potentials of the first node PU and the second node PD compete with each other to increase the power consumption of the circuit is avoided, and the occurrence of the fifth transistor T5 and the sixth transistor T6 is avoided.
  • a DC path from the second clock signal terminal CKB to the first voltage terminal VGL is caused, thereby improving the stability of the shift register unit.
  • the register unit includes a first transistor T1, a second transistor T2, a third transistor T3 to a sixth transistor T6, and a first Capacitor C1 and second capacitor C2.
  • the gate of the first transistor T1 is connected to the first input terminal INPUT1 to receive the first input signal, and the first electrode of the first transistor T1 is connected to the first control signal terminal CN to receive the first control signal, and the second pole of the first transistor T1 Connecting the gate of the second transistor T2; the first electrode of the second transistor T2 is connected to the second input terminal INPUT2 to receive the second input signal, and the second electrode of the second transistor T2 is connected to the gate of the third transistor T3, the third transistor The first pole of T3 and the gate of the sixth transistor T6, and the second pole of the third transistor T3 are connected to the first node PU.
  • the gate of the fourth transistor T4 is connected to the first node PU, the first pole of the fourth transistor T4 is connected to the first clock signal terminal CK to receive the first clock signal, and the second pole of the fourth transistor T4 is connected to the output terminal OUT;
  • the first end of the capacitor C1 is connected to the first node PU, and the second end of the first capacitor C1 is connected to the output end OUT.
  • the gate of the fifth transistor T5 and the first pole are connected to the second clock signal terminal CKB to receive the second clock signal, the second pole of the fifth transistor T5 is connected to the second node PD; the first pole of the sixth transistor T6 is connected to the second The node PD, the second pole of the sixth transistor T6 is connected to the first voltage terminal VGL to receive the first voltage; the first end of the second capacitor C2 is connected to the second node PD, and the second end is connected to the first voltage terminal VGL to receive the first Voltage.
  • the shift register unit further includes a seventh transistor T7 and an eighth transistor T8.
  • the gate of the seventh transistor T7 is connected to the second node PD, the first pole of the seventh transistor T7 is connected to the first node PU, and the second pole of the seventh transistor T7 is connected to the first voltage terminal VGL to receive the first voltage; the eighth transistor The gate of T8 is connected to the second node PD, the first pole of the eighth transistor T8 is connected to the output terminal OUT, and the second pole of the eighth transistor T8 is connected to the first voltage terminal VGL to receive the first voltage.
  • the shift register unit further includes a ninth transistor T9 and a tenth transistor T10, and the gate connection of the ninth transistor T9 is
  • the third input terminal INPUT3 receives the third input signal
  • the first pole of the ninth transistor T9 is connected to the second control signal terminal CNB to receive the second control signal
  • the second pole of the ninth transistor T9 is connected to the second pole of the first transistor T1, a gate of the second transistor T2 and a gate of the tenth transistor T10
  • a first pole of the tenth transistor T10 is connected to the fourth input terminal INPUT4 to receive a fourth input signal
  • a second pole of the tenth transistor T10 is connected to the third transistor T3
  • each of the above transistors may be an N-type transistor or a P-type transistor, which is not limited in the embodiment of the present disclosure.
  • the gate driving circuit composed of the shift register cascade can realize forward scanning and reverse scanning, and the foregoing embodiment has performed the working process and beneficial effects of the shift register unit shown in FIG. 6. Detailed description will not be repeated here.
  • At least one embodiment of the present disclosure also provides a gate driving circuit including a plurality of cascaded shift register units as described in the foregoing embodiments.
  • the gate driving circuit in FIG. 7 is described by taking a circuit structure as shown in FIG. 3 for each shift register unit.
  • the circuit structure shown in FIG. 6 is taken as an example for each shift register unit. Description is made, but embodiments of the present disclosure are not limited thereto.
  • the gate driving circuit can be directly integrated on the array substrate of the display device by using a process similar to that of the thin film transistor to realize a progressive scan driving function.
  • the first stage shift register unit and the first input terminal INPUT1 of the second stage shift register unit are connected to the first signal terminal V1 to receive a trigger signal; in addition to the first stage shift register unit and the second stage In addition to the shift register unit, the first input terminal INPUT1 of the Nth (N is an integer greater than or equal to 3) stage shift register unit is connected to the output terminal OUT_(N-2) of the N-2th shift register unit;
  • the second input terminal INPUT2 of the first stage shift register unit is connected to the second signal terminal V2; in addition to the first stage shift register unit, the second input terminal INPUT2 of the Nth stage shift register unit is connected to the N-1th stage shift The output of the bit register unit OUT_(N-1).
  • the shift register unit of the gate driving circuit provided by the embodiment of the present disclosure has the same structure and advantageous effects as the shift register unit provided by the foregoing embodiment, and the structure and advantageous effects thereof have been described in detail since the foregoing. No longer.
  • the Nth The third input terminal INPUT3 of the stage shift register unit is connected to the output terminal OUT_(N+2) of the N+2 stage shift register unit; the fourth input terminal INPUT4 of the last stage shift register unit is connected to the second signal terminal V2.
  • the fourth input terminal INPUT4 of the Nth stage shift register unit is connected to the output terminal OUT_(N+1) of the N+1th stage shift register unit; the last two stages of shift registers
  • the third input terminal INPUT3 of the unit is connected to the first signal terminal V1.
  • the gate drive circuit can be used for forward scan and reverse scan.
  • OUT_1, OUT_2, OUT_3, and OUT_4 represent output terminals of the first stage, the second stage, the third stage, and the fourth stage shift register unit in the gate driving circuit 20, respectively.
  • OUT_(N-1), OUT_(N) represent the output of the N-1th stage and the Nth stage shift register unit, and so on.
  • the gate driving circuit further includes a first clock signal line CKL, a second clock signal line CKBL, a third clock signal line CKR, and a fourth clock signal line CKBR.
  • the shift register unit further includes a first clock signal terminal CK, and is configured to be connected to the first clock signal line CKL or the third clock signal line CKR to receive the first clock signal.
  • the first clock signal line CKL and the second m-1 (m is an integer greater than 0) stage clock register terminal CK are connected, the third clock signal line CKR and the clock signal terminal of the second m-stage shift register unit CK connection.
  • the embodiments of the present disclosure include, but are not limited to, the foregoing connection manner.
  • the first clock signal line CKL and the clock signal terminal CK of the 2m-stage shift register unit may be connected, and the third clock signal line CKR may be used. It is connected to the clock signal terminal CLK of the 2m-1th stage shift register unit.
  • the shift register unit further includes a second clock signal terminal CKB and is configured to be respectively coupled to the second clock signal line CKBL or the fourth clock signal line CKBR to receive the second clock signal.
  • the specific connection mode is similar to that of the first clock signal terminal CK and the first clock signal line CKL and the third clock signal line CKR, and details are not described herein again.
  • the gate driving circuit further includes a first control signal line CN and a second control signal line CNB to provide a first control signal and a second control signal, respectively.
  • the shift register unit further includes a first control signal terminal CN and a second control signal terminal CNB, and is configured to be respectively connected to the first control signal line CN and the second control signal line CNB to respectively receive the first control signal And a second control signal.
  • the CN can represent both the first control signal end and the first control signal line (providing the first control signal), and the CNB can represent the second control signal end and the CNB. Indicates a second control signal line (providing a second control signal).
  • the gate drive circuit further includes a first voltage line VGL to provide a first voltage.
  • each stage of the shift register unit further includes a first voltage terminal VGL and is configured to be respectively coupled to the first voltage line VGL to receive the first voltage.
  • the VGL can represent both the first voltage terminal and the first voltage line (providing the first voltage).
  • the gate drive circuit may further include a timing controller (not shown).
  • the timing controller may be configured to and the first clock signal line CKL, the second clock signal line CKBL, the third clock signal line CKR, the fourth clock signal line CKBR, the first control signal line CN, and the second control signal.
  • the line CNB is connected to the first voltage line VGL or the like to supply a clock signal and a control signal and a first voltage to each shift register unit.
  • the timing controller can also be configured to provide a trigger signal STV and a reset signal RESET.
  • the gate driving circuit may be disposed on one side of the display panel.
  • the display panel includes a plurality of rows of gate lines, and the output ends of the shift register units in the gate driving circuit may be configured to be sequentially connected to the plurality of rows of gate lines for outputting the gate scan signals.
  • the gate driving circuit shown in FIGS. 7 and 8 can also be used to alternately drive the gate lines bilaterally.
  • the even-numbered shift register unit is disposed on one side of the display panel for driving the even-numbered grids.
  • a line-level shift register unit is disposed on the other side of the display panel for driving odd-numbered gate lines.
  • the clock signal in the gate driving circuit provided by the embodiment of the present disclosure may be cycled in the form of CKBL, CKBR, CKL, CKR, that is, each adjacent four-stage shift register unit is connected.
  • the incoming clock signal is one cycle.
  • the duty ratios of CKBL, CKBR, CKL, and CKR are both 25%, and only one clock of the clock signals CKBL, CKBR, CKL, and CKR at the same time. The signal is high.
  • the gate driving circuit may further include a plurality of clock signal lines such as six or eight clock signal lines, and the number of clock signal lines is determined according to specific conditions, and embodiments of the present disclosure are here. Not limited.
  • Embodiments of the present disclosure provide a display device including a gate driving circuit as shown in FIG. 7 or FIG. It has the same structure and advantageous effects as the gate driving circuit provided by the foregoing embodiment. Since the foregoing embodiment has been described in detail for the structure and advantageous effects of the gate driving circuit, details are not described herein again.
  • the display device 1 includes a gate driving circuit 200 provided by an embodiment of the present disclosure.
  • the display device 1 further includes a display panel 400 including an array of a plurality of sub-pixel units 410.
  • the display device 1 may further include a data driving circuit 300.
  • the data driving circuit 300 is for providing a data signal to the pixel array;
  • the gate driving circuit 200 is for providing a driving signal to the pixel array, for example, the driving signal can drive the scanning transistor and the sensing transistor in the sub-pixel unit 410.
  • the data driving circuit 300 is electrically connected to the sub-pixel unit 410 through the data line DL, and the gate driving circuit 200 is electrically connected to the sub-pixel unit 410 through the gate line GL.
  • the display device may specifically include at least a liquid crystal display device and an organic light emitting diode display device.
  • the display device may be any product or component having a display function, such as a liquid crystal display, a liquid crystal television, a digital photo frame, a mobile phone, or a tablet computer. .
  • Embodiments of the present disclosure also provide a driving method of a shift register unit that can be used to drive the shift register unit 100 provided by an embodiment of the present disclosure, for example, in one example, the driving method includes the following operations.
  • the first input sub-circuit 10 In the input phase, under the control of the first input signal of the first input terminal INPUT1, the first input sub-circuit 10 outputs the first control signal of the first control signal terminal CN to the pull-up control sub-circuit 20; at the second clock signal end Under the control of the second clock signal of the CKB, the pull-down control sub-circuit 40 outputs the second clock signal signal of the second clock signal terminal CKB to the second node PD;
  • the pull-up control sub-circuit 20 outputs the second input signal of the second input terminal INPUT2 to the first node PU; the pull-up control sub-circuit 20, the second input signal of the second input terminal INPUT2 is also output to the pull-down control sub-circuit 40.
  • the pull-down control sub-circuit 40 firstly sets the first voltage terminal VGL. The voltage is output to the second node PD;
  • the output sub-circuit 30 outputs an output signal to the output terminal OUT under the control of the level of the first node PU.
  • the shift register unit further includes a pull-down sub-circuit 50
  • the driving method further includes a reset phase
  • the pull-down sub-circuit 50 outputs the first voltage of the first voltage terminal VGL to the first node PU and the output terminal OUT;
  • the pull-down control sub-circuit 40 In the reset phase, under the control of the second clock signal of the second clock signal terminal CKB, the pull-down control sub-circuit 40 outputs the second clock signal to the second node PD; under the control of the level of the second node PD, pull-down The sub-circuit 50 outputs the first voltage of the first voltage terminal VGL to the first node PD and the output terminal OUT.
  • the driving method further includes:
  • the second input sub-circuit 60 In the input phase, under the control of the third input signal of the third input terminal INPUT3, the second input sub-circuit 60 outputs the second control signal of the second control signal terminal CNB; the second clock signal at the second clock signal terminal CKB Controlled, the pull-down control sub-circuit 40 outputs the second clock signal signal of the second clock signal terminal CKB to the second node;
  • the first input sub-circuit 10 outputs the fourth input signal of the fourth input terminal INPUT4 to the control node PUCN under the control of the first control signal, and the pull-up control sub-circuit is under the control of the level of the control node PUCN.
  • the fourth input signal of the fourth input terminal INPUT4 is output to the first node PU;
  • the pull-up control sub-circuit 20 also outputs the fourth input signal of the fourth input terminal INPUT4 to the pull-down control sub-circuit 40, at the fourth input end Under the control of the fourth input signal of the INPUT4, the pull-down control sub-circuit 40 outputs the first voltage of the first voltage terminal VGL to the second node PD;
  • the output sub-circuit 30 outputs an output signal to the output terminal OUT under the control of the level of the first node PU.

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Abstract

一种移位寄存器单元及驱动方法、栅极驱动电路和显示装置。移位寄存器单元(100)包括第一输入子电路(10)、第一控制子电路(20)、输出子电路(30)和第二控制子电路(40)。第一输入子电路(10)配置为在第一输入端(INPUT1)的第一输入信号的控制下，将第一控制信号端(CN)的第一控制信号输出至第一控制子电路(20)；第一控制子电路(20)配置为在第一输入子电路(10)输出的第一控制信号的控制下，将第二输入端(INPUT2)的第二输入信号输出至第一节点(PU)，或者第一控制子电路(20)配置为将第二输入信号输出至第二控制子电路(40)；第二控制子电路(40)配置为在第二时钟信号端(CKB)的第二时钟信号的控制下，将第二时钟信号输出至第二节点(PD)；或者，第二控制子电路(40)配置为在控制节点(PUCN)的电平的控制下，将第一电压端VGL的第一电压输出至第二节点(PD)。该移位寄存器单元可以用于避免GOA单元在工作过程中出现的第一节点和第二节点的电位互相竞争的现象，从而可以降低GOA单元的功耗和提高GOA单元的稳定性。

Description

移位寄存器单元及驱动方法、栅极驱动电路和显示装置
本申请要求于2018年4月18日递交的中国专利申请第201810350299.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种移位寄存器单元及驱动方法、栅极驱动电路和显示装置。
背景技术
随着LCD(Liquid Crystal Display，液晶显示器)显示技术的不断发展和日趋激烈的市场趋势，GOA(Gate driver On Array)的技术能力以及性能品质的提升也变得尤为迫切，GOA的稳定性也是GOA电路性能技术堡垒的一种考虑重点。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括：第一输入子电路、第一控制子电路、输出子电路和第二控制子电路。所述第一输入子电路连接第一输入端、第一控制信号端和所述第一控制子电路，所述第一输入子电路配置为在所述第一输入端的第一输入信号的控制下，将所述第一控制信号端的第一控制信号输出至所述第一控制子电路；所述第一控制子电路连接第二输入端、第一节点和所述第二控制子电路，所述第一控制子电路配置为在所述第一输入子电路输出的第一控制信号的控制下，将所述第二输入端的第二输入信号输出至所述第一节点；或者，所述第一控制子电路配置为将所述第二输入信号输出至所述第二控制子电路；所述输出子电路连接所述第一节点和输出端，所述输出子电路配置为在所述第一节点的电平的控制下，将输出信号输出至所述输出端；所述第二控制子电路连接第二时钟信号端、第二节点、控制节点和第一电压端，所述第二控制子电路配置为在所述第二时钟信 号端的第二时钟信号的控制下，将所述第二时钟信号输出至所述第二节点；或者，所述第二控制子电路配置为在所述控制节点的电平的控制下，将所述第一电压端的第一电压输出至所述第二节点。
例如，本公开一实施例提供的移位寄存器单元，还包括降噪子电路。所述降噪子电路连接所述第二节点、所述第一节点、所述第一电压端和所述输出端，所述降噪子电路配置为在所述第二节点的电平的控制下，将所述第一电压端的第一电压输出至所述第一节点和所述输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一输入子电路包括第一晶体管。所述第一晶体管的栅极连接所述第一输入端以接收所述第一输入信号，所述第一晶体管的第一极连接所述第一控制信号端以接收所述第一控制信号，所述第一晶体管的第二极作为所述第一输入子电路的输出端连接所述第一控制子电路。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一控制子电路包括第二晶体管和第三晶体管。所述第二晶体管的栅极连接所述第一输入子电路的输出端，所述第二晶体管的第一极连接所述第二输入端以接收所述第二输入信号，所述第二晶体管的第二极连接所述控制节点；所述第三晶体管的栅极和第一极彼此电连接，且分别配置为和所述控制节点连接，所述第三晶体管的第二极连接所述第一节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述输出子电路包括第四晶体管和第一电容。所述第四晶体管的栅极连接所述第一节点，所述第四晶体管的第一极连接第一时钟信号端以接收第一时钟信号作为所述输出信号，所述第四晶体管的第二极连接所述输出端；所述第一电容的第一端连接所述第一节点，所述第一电容的第二端连接所述输出端。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二控制子电路包括第五晶体管、第六晶体管和第二电容。所述第五晶体管的栅极和第一极彼此电连接，且分别配置为和所述第二时钟信号端连接以接收所述第二时钟信号，所述第五晶体管的第二极连接所述第二节点；所述第六晶体管的栅极连接所述控制节点，所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极连接所述第一电压端以接收所述第一电压；所述第二电容的第一端连接所述第二节点，所述第二电容的第二端连接所述第一电压端以 接收所述第一电压。
例如，在本公开一实施例提供的移位寄存器单元中，所述降噪子电路包括第七晶体管和第八晶体管。所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的第一极连接所述第一节点，所述第七晶体管的第二极连接所述第一电压端以接收所述第一电压；所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一极连接所述输出端，所述第八晶体管的第二极连接所述第一电压端以接收所述第一电压。
例如，本公开一实施例提供的移位寄存器单元，还包括第二输入子电路。所述第二输入子电路连接第三输入端、第四输入端、第二控制信号端和所述控制节点，所述第二输入子电路配置为在所述第三输入端的第三输入信号以及所述第二控制信号端的第二控制信号的控制下，将所述第四输入端的第四输入信号输出至所述控制节点。
例如，在本公开一实施例提供的移位寄存器单元中，所述第二输入子电路包括第九晶体管和第十晶体管。所述第九晶体管的栅极连接所述第三输入端以接收所述第三输入信号，所述第九晶体管的第一极连接所述第二控制信号端以接收所述第二控制信号，所述第九晶体管的第二极连接所述第十晶体管的栅极；所述第十晶体管的第一极连接所述第四输入端以接收所述第四输入信号，所述第十晶体管的第二极连接所述控制节点。
本公开至少一实施例还提供一种移位寄存器单元，包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第一电容和第二电容。所述第一晶体管的栅极连接第一输入端以接收第一输入信号，所述第一晶体管的第一极连接第一控制信号端以接收第一控制信号，所述第一晶体管的第二极连接所述第二晶体管的栅极；所述第二晶体管的第一极连接第二输入端以接收第二输入信号，所述第二晶体管的第二极连接所述第三晶体管的栅极、所述第三晶体管的第一极以及所述第六晶体管的栅极；所述第三晶体管的第二极连接第一节点；所述第四晶体管的栅极连接所述第一节点，所述第四晶体管的第一极连接第一时钟信号端以接收第一时钟信号，所述第四晶体管的第二极连接输出端；所述第一电容的第一端连接所述第一节点，所述第一电容的第二端连接所述输出端；所述第五晶体管的栅极和第一极彼此电连接，且分别配置为与第二时钟信号端连接以接收第二时钟信号， 所述第五晶体管的第二极连接第二节点；所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极连接第一电压端以接收第一电压；所述第二电容的第一端连接所述第二节点，所述第二电容的第二端连接所述第一电压端以接收所述第一电压。
例如，本公开一实施例提供的移位寄存器单元，还包括第七晶体管和第八晶体管。所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的第一极连接所述第一节点，所述第七晶体管的第二极连接所述第一电压端以接收所述第一电压；所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一极连接所述输出端，所述第八晶体管的第二极连接所述第一电压端以接收所述第一电压。
例如，本公开一实施例提供的移位寄存器单元，还包括第九晶体管和第十晶体管。所述第九晶体管的栅极连接第三输入端以接收第三输入信号，所述第九晶体管的第一极连接第二控制信号端以接收第二控制信号，所述第九晶体管的第二极连接所述第一晶体管的第二极、第二晶体管的栅极以及所述第十晶体管的栅极；所述第十晶体管的第一极连接第四输入端以接收第四输入信号，所述第十晶体管的第二极连接所述第三晶体管的栅极、所述第三晶体管的第一极以及所述第六晶体管的栅极。
例如，在本公开一实施例提供的移位寄存器单元中，所述第一晶体管至所述第十晶体管均为N型晶体管或者均为P型晶体管。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：输入阶段，在所述第一输入端的第一输入信号的控制下，所述第一输入子电路将所述第一控制信号端的第一控制信号输出至所述第一控制子电路；在所述第二时钟信号端的第二时钟信号的控制下，所述下拉控制子电路将所述第二时钟信号端的第二时钟信号信号输出至所述第二节点；预充电阶段，在所述第一输入子电路输出的第一控制信号的控制下，所述第一控制子电路将第二输入端的第二输入信号输出至所述第一节点；所述第一控制子电路还将所述第二输入端的第二输入信号输出至所述第二控制子电路，在所述第二输入端的第二输入信号的控制下，所述第二控制子电路将所述第一电压端的第一电压输出至所述第二节点；输出阶段，在所述第一节点的电平的控制下，所述输出子电路将所述输出信号输出至所述输出端。
例如，本公开一实施例提供的驱动方法，所述移位寄存器单元还包括降噪子电路，所述驱动方法还包括复位阶段。在所述输入阶段，在所述第二节点的电平的控制下，所述降噪子电路将第一电压端的第一电压输出至所述第一节点和所述输出端；在所述复位阶段，在所述第二时钟信号端的第二时钟信号的控制下，所述第二控制子电路将所述第二时钟信号输出至所述第二节点；在所述第二节点的电平的控制下，所述降噪子电路将所述第一电压端的第一电压输出至所述第一节点和所述输出端。
本公开至少一实施例还提供一种移位寄存器单元的驱动方法，包括：输入阶段，在所述第三输入端的第三输入信号的控制下，所述第二输入子电路输出所述第二控制信号端的第二控制信号；在所述第二时钟信号端的第二时钟信号的控制下，所述第二控制子电路将所述第二时钟信号端的第二时钟信号信号输出至所述第二节点；预充电阶段，所述第二输入子电路在所述第二控制信号的控制下输出所述第四输入端的第四输入信号至所述控制节点，在所述控制节点的电平的控制下，所述第一控制子电路将所述第四输入端的第四输入信号输出至所述第一节点；所述第一控制子电路还将所述第四输入端的第四输入信号输出至所述第二控制子电路，在所述第四输入端的第四输入信号的控制下，所述第二控制子电路将所述第一电压端的第一电压输出至所述第二节点；输出阶段，在所述第一节点的电平的控制下，所述输出子电路将所述输出信号输出至所述输出端。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的本公开任一实施例提供的移位寄存器单元；第一级移位寄存器单元和第二级移位寄存器单元的第一输入端连接第一信号端；除了所述第一级移位寄存器单元和所述第二级移位寄存器单元以外，第N级移位寄存器单元的第一输入端连接第N-2级移位寄存器单元的输出端；所述第一级移位寄存器单元的第二输入端连接第二信号端；除了所述第一级移位寄存器单元以外，所述第N级移位寄存器单元的第二输入端连接第N-1级移位寄存器单元的输出端；其中，N为大于等于3的整数。
例如，在本公开一实施例提供的栅极驱动电路中，在所述移位寄存器单元包括第二输入子电路，或者包括第九晶体管和第十晶体管的情况下，除了最后两级移位寄存器单元以外，所述第N级移位寄存器单元的第三输入端连 接第N+2级移位寄存器单元的输出端；除了最后一级移位寄存器单元以外，所述第N级移位寄存器单元的第四输入端连接第N+1级移位寄存器单元的输出端；其中，所述最后两级移位寄存器单元的第三输入端连接所述第一信号端，所述最后一级移位寄存器单元的第四输入端连接所述第二信号端。
本公开至少一实施例还提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路。
附图说明
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一种现有的GOA单元的电路图；
图2为本公开实施例提供的一种移位寄存器单元的模块图；
图3为图2所示的移位寄存器单元的电路结构图；
图4为图3所示的移位寄存器单元的时序控制图；
图5为图2所示的移位寄存器单元包括第二输入子电路时的模块图；
图6为图3所示的移位寄存器单元包括第二输入子电路时的电路结构图；
图7为多个如图3所示的移位寄存器单元级联形成的栅极驱动电路的结构图；
图8为多个如图6所示的移位寄存器单元级联形成的栅极驱动电路的结构图；
图9为一种图7或图8中所示的栅极驱动电路的时钟信号的时序图；以及
图10为本公开一实施提供的一种显示装置的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做 出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同或类似的参考标号表示。
图1为一种GOA单元的电路图。下面以该GOA单元中各晶体管采用N型晶体管为例进行说明。例如，在对第一节点PU充电时，第一输入端INPUT1为高电平，使得第一晶体管T1打开，此时对第一节点PU充电，在第一节点PU的控制下，第五晶体管T5打开，使得第二节点PD与低电压端VGL连接；同时，在该阶段中，时钟信号端CKB提供高电平，使得第四晶体管T4打开，时钟信号端CKB提供的高电平输出至第二节点PD。此时，由于时钟信号端CKB提供的高电平与低电压端VGL的低电平同时输入至第二节点PD，形成直流通路。
在形成该直流通路时，第一节点PU的高电平通过控制第五晶体管T5导通而用于拉低第二节点PD的电平，而由于第四晶体管T4在第二时钟信号端CKB的高电平的控制下导通，例如在未设置第四晶体管T4和第五晶体管T5的导通参数的情况下，可能使得第二节点PD处于高电平，第六晶体管T6响应于第二节点PD的高电平导通，从而会拉低第一节点PU的高电平，从而出现第一节点PU与第二节点PD的电位互相竞争的现象。
因此，一方面，上述直流通路会导致包括多个级联的GOA单元的栅极驱动电路的功耗增加；另一方面，该直流通路是GOA单元的一种不良现象，可能会拉低时钟信号CKB的电压，造成对第二节点PD的充电不足，导致该级GOA单元无法正常工作，从而使得该GOA单元的稳定性降低。
本公开一实施例提供一种移位寄存器单元，包括第一输入子电路、第一控制子电路、输出子电路和第二控制子电路。第一输入子电路连接第一输入端、第一控制信号端和第一控制子电路，第一输入子电路配置为在第一输入端的第一输入信号的控制下，将第一控制信号端的第一控制信号输出至第一控制子电路；第一控制子电路连接第二输入端、第一节点和第二控制子电路，第一控制子电路配置为在第一输入子电路输出的第一控制信号的控制下，将第二输入端的第二输入信号输出至第一节点；或者，第一控制子电路配置为将第二输入信号输出至第二控制子电路；输出子电路连接第一节点和输出端，输出子电路配置为在第一节点的电平的控制下，将输出信号输出至输出端；第二控制子电路连接第二时钟信号端、第二节点、控制节点和第一电压端，第二控制子电路配置为在第二时钟信号端的第二时钟信号的控制下，将第二时钟信号输出至第二节点；或者，第二控制子电路配置为在控制节点的电平的控制下，将第一电压端的第一电压输出至第二节点。本公开的实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开的实施例提供移位寄存器单元，可以避免在工作过程中出现第一节点和第二节点的电位互相竞争的现象，从而可以降低包括该多个级联的移位寄存器单元的栅极驱动电路的功耗，提高该电路结构的稳定性。
下面结合附图对本公开的实施例及其示例进行详细说明。
本公开实施例提供一种移位寄存器单元(也称GOA单元)，包括：第一输入子电路、第一控制子电路、输出子电路和第二控制子电路。如图2所示，在一个示例中，该移位寄存器单元100包括：第一输入子电路10、上拉控制子电路20、输出子电路30和下拉控制子电路40。需要注意的是，本公开实施例中的上拉控制子电路20为第一控制子电路的一个示例，下拉控制子电路40为第二控制子电路的一个示例，下面以第一控制子电路为上拉控制子电路20，第二控制子电路为下拉控制子电路40为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
例如，第一输入子电路10连接第一输入端INPUT1、第一控制信号端CN和上拉控制子电路20，该第一输入子电路10配置为在第一输入端INPUT1的第一输入信号控制下，将第一控制信号端CN的第一控制信号输出至上拉控制子电路20，从而控制上拉控制子电路20导通。
例如，上拉控制子电路20连接第二输入端INPUT2、第一节点PU和下拉控制子电路40。例如，该上拉控制子电路20配置为在第一输入子电路10输出的第一控制信号的控制下导通，将第二输入端INPUT2与第一节点PU连接，从而将第二输入端INPUT2的第二输入信号输出至第一节点PU，以对第一节点PU进行充电(例如，上拉)；或者，该上拉控制子电路20配置为在第一输入子电路10输出的第一控制信号的控制下导通时，将第二输入端INPUT2与下拉控制子电路40连接，从而将第二输入端INPUT2的第二输入信号输出至下拉控制子电路40，以使得下拉控制子电路40响应于第二输入信号而导通，从而使得第一节点PU与第一电压端VGL或另行提供的电压端(例如，低电压端，提供低电平信号)连接。需要说明的是，第一电压端VGL例如可以配置为保持输入直流低电平信号，例如，将该直流低电平信号称为第一电压。
输出子电路30连接第一节点PU和输出端OUT，该输出子电路30配置为在第一节点PU的电平的控制下，将输出信号输出至输出端OUT。例如，输出子电路30和第一时钟信号端CK、第一节点PU和输出端OUT连接，且配置为在第一节点PU的电平的控制下导通，使得第一时钟信号端CK与输出端连接，从而可以将第一时钟信号端CK的第一时钟信号作为输出信号输出至输出端OUT。
例如，下拉控制子电路40通过上拉控制子电路20连接第二输入端INPUT2。例如，下拉控制子电路40连接第二时钟信号端CKB、第二节点PD、控制节点PUCN和第一电压端VGL，该下拉控制子电路40配置为在第二时钟信号端CKB的第二时钟信号的控制下部分导通，使得第二时钟信号端CKB和第二节点PD连接，从而将第二时钟信号端CKB的第二时钟信号输出至第二节点PD，以将第二节点PD充电至高电平；或者，下拉控制子电路40配置为在控制节点PUCN的电平(即第二输入端INPUT2的第二输入信号)的控制下部分导通，使得第二节点PD与第一电压端VGL或另行提供 的电压端(例如，低电压端，提供低电平信号)连接，从而将第一电压端VGL的第一电压输出至第二节点PD。例如，通过控制第一输入端INPUT1的第一输入信号、第二输入端INPUT2的第二输入信号以及第二时钟信号端CKB的第二时钟信号的时序，使得第二时钟信号端CKB的第二时钟信号和第一电压端VGL的第一电压分时对第二节点PD进行控制，从而避免了下拉控制子电路40完全导通造成由第二时钟信号端CKB至第一电压端VGL的直流通路，从而可以降低包括该多个级联的移位寄存器单元的栅极驱动电路的功耗，提高该电路结构的稳定性。
例如，在另一个示例中，该移位寄存器单元100还包括降噪子电路。例如，如图2所示，该移位寄存器单元100还包括下拉子电路50。需要注意的是，该下拉子电路50为降噪子电路的一个示例，下面以降噪子电路为下拉子电路50为例进行说明，但是本公开的实施例不限于此，以下实施例与此相同，不再赘述。
下拉子电路50连接第二节点PD、第一节点PU、第一电压端VGL和输出端OUT，该下拉子电路50配置为在第二节点PD的电平的控制下导通，使得第一节点PU和输出端OUT与第一电压端VGL连接，从而将第一电压端VGL的第一电压输出至第一节点PU和输出端OUT，以实现降噪。
基于此，本公开实施例提供的移位寄存器单元，在输入阶段，在第一输入端INPUT1的第一输入信号控制下，第一输入子电路10将第一控制信号端CN的第一控制信号输出至上拉控制子电路20；在第二时钟信号端CKB的第二时钟信号的控制下，下拉控制子电路40将第二时钟信号端CKB的第二时钟信号输出至第二节点PD；在第二节点PD的电平的控制下，下拉子电路50将第一电压端的第一电压输出至第一节点PU，以实现降噪。在预充电阶段，在第一输入子电路10输出的第一控制信号的控制下，上拉控制子电路20将第二输入端INPUT2的第二输入信号输出至第一节点PU；上拉控制子电路20还将第二输入端INPUT2的第二输入信号输出至下拉控制子电路40，在第二输入端INPUT2的第二输入信号的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第二节点PD，从而拉低第二节点PD的电平，以保证在该阶段对第一节点PU的正常充电。
综上所述，在输入阶段，可以将第二时钟信号端CKB提供的高电平信 号输入至第二节点PD，在预充电阶段可以将第一电压端VGL的第一电压输入至第二节点PD，因此不会出现时钟信号端CKB的高电平与第一电压端VGL的低电平形成直流通路的情况，即避免了出现第一节点PU和第二节点PD的电位互相竞争而导致电路功耗增加的问题，同时也能提高该移位寄存器单元的稳定性。
以下结合图3对图2所示的移位寄存器单元的电路结构进行举例说明。
第一输入子电路10包括第一晶体管T1，第一晶体管T1的栅极连接第一输入端INPUT1以接收第一输入信号，第一晶体管T1的第一极连接第一控制信号端CN以接收第一控制信号，第一晶体管T1的第二极作为所述第一输入子电路10的输出端连接上拉控制子电路20。例如，当第一输入端INPUT1提供的第一输入信号为有效电平时，第一晶体管导通，使得上拉控制子电路20与第一控制信号端CN连接，从而可以在第一控制信号端CN提供的第一控制信号的控制下导通。
上拉控制子电路20包括第二晶体管T2和第三晶体管T3，第二晶体管T2的栅极连接第一输入子电路10的输出端，即连接第一晶体管T1的第二极，第二晶体管T2的第一极连接第二输入端INPUT2以接收第二输入信号，第二晶体管T2的第二极连接控制节点PUCN，即连接第三晶体管T3的栅极、第三晶体管T3的第一极以及下拉控制子电路40，即图3中第六晶体管T6的栅极；例如，第三晶体管的栅极和第一极彼此电连接，且分别配置为和控制节点PUCN连接，第三晶体管T3的第二极连接第一节点PU。
输出子电路30包括第四晶体管T4和第一电容C1；第四晶体管T4的栅极连接第一节点PU，第四晶体管T4的第一极连接第一时钟信号端CK以接收第一时钟信号作为输出信号，第四晶体管T4的第二极连接输出端OUT；第一电容C1的第一端连接第一节点PU，第一电容C1的第二端连接输出端OUT。当第一节点PU的电平为有效电平时，第四晶体管T4导通，从而将第一时钟信号输出至输出端OUT；由于第一电容C1具有自举作用，有利于更好地将第一时钟信号中的高电平输出。
下拉控制子电路40包括第五晶体管T5、第六晶体管T6和第二电容C2；第五晶体管T5的栅极和第一极彼此电连接，且分别配置为和第二时钟信号端CKB连接以接收第二时钟信号，第五晶体管T5的第二极连接第二节点 PD；第六晶体管T6的栅极连接控制节点PUCN(即上拉控制子电路20)，第六晶体管T6的第一极连接第二节点PD，第六晶体管T6的第二极连接第一电压端VGL以接收第一电压；第二电容C2的第一端连接第二节点PD，第二端连接第一电压端VGL以接收第一电压。例如，当第二时钟信号为有效电平时，第五晶体管T5导通，使得第二节点PD和第二时钟信号端CKB连接，从而将第二节点PD充电至高电平；当控制节点PUCN为有效电平时，第六晶体管T6导通，使得第二节点PD和第一电压端VGL连接，从而将第二节点PD下拉至低电平。
例如，通过控制第一输入端INPUT1的第一输入信号、第二输入端INPUT2的第二输入信号以及第二时钟信号端CKB的第二时钟信号的时序，使得第二时钟信号端CKB的第二时钟信号和第一电压端VGL的第一电压分时对第二节点PD进行控制。例如，在输入阶段，第二时钟信号端CKB提供高电平，使得第五晶体管T5导通，从而将第二时钟信号的高电平输入至第二节点PD，并存储在第二电容C2中；在预充电阶段，第二时钟信号端CKB提供低电平，第六晶体管T6在控制节点PUCN的高电平的控制下开启，从而将第二节点PD和第一电压端VGL连接，从而拉低第二节点PD的电平。例如，第五晶体管T5和第六晶体管T6在输入阶段和预充电阶段分时导通，从而可以避免了第五晶体管T5和第六晶体管T6同时导通造成由第二时钟信号端CKB至第一电压端VGL的直流通路，从而可以降低包括该多个级联的移位寄存器单元的栅极驱动电路的功耗，提高该电路结构的稳定性。下拉子电路50包括第七晶体管T7和第八晶体管T8；第七晶体管T7的栅极连接第二节点PD，第七晶体管T7的第一极连接第一节点PU，第七晶体管T7的第二极连接第一电压端VGL以接收第一电压；第八晶体管T8的栅极连接第二节点PD，第八晶体管T8的第一极连接输出端OUT，第八晶体管T8的第二极连接第一电压端VGL以接收第一电压。
需要注意的是，在本公开的各个实施例的说明中，第一节点PU、第二节点PD、控制节点PUCN并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管、场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体 管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。
需要说明的是，本公开实施例不限定第n(n为大于等于1的整数)晶体管为一个晶体管，其可以是多个晶体管的串联，图3中以第n晶体管包括一个晶体管为例进行示意。本公开实施例中，上述晶体管可以均为P型晶体管或者均为N型晶体管。当上述晶体管均为P型晶体管时，其第一极为源极，第二极为漏极。当上述晶体管均为N型晶体管时，其第一极为漏极，第二极为源极。本公开实施例以各晶体管为N型晶体管为例进行说明，第一电压端VGL输出恒定的低电平。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
以下结合图4对图3所示的移位寄存器单元的工作过程进行具体的说明，一图像帧内，该移位寄存器单元的工作过程包括：输入阶段P1、预充电阶段P2、输出阶段P3和复位阶段P4。
输入阶段P1，第一输入端INPUT1提供高电平(即第一输入信号为高电平)，第二时钟信号端CKB提供高电平(即第二时钟信号为高电平)，在第一输入端INPUT1的高电平的控制下，第一输入子电路10将第一控制信号端CN的信号输出至上拉控制子电路20；在第二时钟信号端CKB的高电平的控制下，下拉控制子电路40将第二时钟信号端CKB的高电平信号输出至第二节点PD以对第二节点PD进行充电；在第二节点PD的电平的控制下， 下拉子电路50将第一电压端VGL的第一电压输出至第一节点PU，以避免在此阶段对第一节点PU进行充电。
具体地，INPUT1＝1，INPUT2＝0，CN＝1，CKB＝1，CK＝0，PUCN＝0，PU＝0，PD＝1，OUT＝0。其中，“1”表示高电平，“0”表示低电平。
在此情况下，在第一输入端INPUT1的高电平的控制下，第一晶体管T1导通，第一控制信号端CN的第一控制信号通过第一晶体管T1输出至第二晶体管T2的栅极，第二晶体管T2导通，第二输入端INPUT2的低电平通过第二晶体管T2输出至控制节点PUCN，在控制节点PUCN的控制下，第三晶体管T3和第六晶体管T6处于关断状态。在第二时钟信号端CKB的第二时钟信号的控制下，第五晶体管T5导通，第二时钟信号端CKB提供的第二时钟信号通过第五晶体管T5对第二节点PD充电，从而第二节点PD为高电平。同时，在第二节点PD的电平控制下，第七晶体管T7和第八晶体管T8导通，第一电压端VGL的第一电压分别通过第七晶体管T7和第八晶体管T8输出至输出端OUT和第一节点PU，在第一节点PU的控制下，第四晶体管T4处于关断状态，从而在此阶段，输出端OUT输出低电平。
综上所述，输入阶段中，第五晶体管T5导通，第六晶体管T6关断，避免了出现第五晶体管T5和第六晶体管T6同时导通时造成由第二时钟信号端CKB至第一电压端VGL的直流通路(即短路)，从而避免了因该直流通路导致第一节点PU和第二节点PD的电位互相竞争的问题，因此，可以降低包括该多个级联的移位寄存器单元的栅极驱动电路的功耗，提高该电路结构的稳定性。
预充电阶段P2，第二输入端INPUT2提供高电平，第一时钟信号端CK提供低电平，例如，第一输入子电路10输出的第一控制信号可以维持至该预充电阶段P2，从而在第一输入子电路10输出的第一控制信号的控制下，上拉控制子电路20将第二输入端INPUT2的高电平(即第二输入信号)输出至第一节点PU，以将第一节点PU充电至第一高电平；上拉控制子电路20还将第二输入端INPUT2的高电平输出至下拉控制子电路40，在第二输入端INPUT2的高电平的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第二节点PD，从而拉低第二节点PD的电平，避免其对第一节点PD的充电的影响。
具体地，INPUT1＝0，INPUT2＝1，CN＝1，CKB＝0，CK＝0，PUCN＝1，PU＝1，PD＝0，OUT＝0。
在此情况下，在第一输入端INPUT1的高电平的控制下，第一晶体管T1关断；第二输入端INPUT2的高电平通过第二晶体管T2输出至控制节点PUCN，在控制节点PUCN的电平的控制下，第三晶体管T3和第六晶体管T6导通。控制节点PUCN的高电平通过第三晶体管T3输出至第一节点PU，在第一节点PU的电平的控制下，第四晶体管T4导通，第一时钟信号端CK的低电平通过第四晶体管T4输出至输出端OUT，从而在此阶段，输出端OUT输出低电平。第一电压端VGL的第一电压通过第六晶体管T6输出至第二节点PD，在第二节点PD的电平的控制下，第七晶体管T7和第八晶体管T8关断。在第二时钟信号端CKB的低电平的控制下，第五晶体管T5关断。
综上所述，预充电阶段中，第五晶体管T5关断，第六晶体管T6导通，避免了出现第五晶体管T5和第六晶体管T6同时导通造成由第二时钟信号端CKB至第一电压端VGL的直流通路(即短路)，从而避免了该直流通路导致的第一节点PU和第二节点PD的电位互相竞争的问题，因此，可以降低包括该多个级联的移位寄存器单元的栅极驱动电路的功耗，提高该电路结构的稳定性。由于第一时钟信号端CK提供低电平，所以，在该阶段中，输出端OUT不输出栅线扫描信号。
输出阶段P3：第一时钟信号端CK提供高电平，在第一节点PU的电平的控制下，输出子电路30将第一时钟信号端CK的高电平输出至输出端OUT。
具体地，INPUT1＝0，INPUT2＝0，CN＝1，CKB＝0，CK＝1，PUCN＝0，PU＝1，PD＝0，OUT＝1。
在此情况下，第二输入端INPUT2的低电平通过第二晶体管T2输出至节点PUCN，在节点PUCN的电平的控制下，第三晶体管T3和第六晶体管T6关断。在第一节点PU的电平的控制下，第四晶体管T4导通，第一时钟信号端CK的高电平通过第四晶体管T4输出至输出端OUT；由于第一电容C1的自举作用，第一节点PU的电位进一步升高，被充电至第二高电平。此外，第一晶体管T1、第五晶体管T5、第七晶体管T7和第八晶体管T8的状态与预充电阶段相同，此处不再赘述。
综上所述，该阶段中输出端OUT输出栅线扫描信号。
复位阶段P4：第二时钟信号端CKB提供高电平，在第二时钟信号端CKB的高电平的控制下，下拉控制子电路40将第二时钟信号端CKB的高电平输出至第二节点PD，从而将第二节点PD充电至高电平；在第二节点PD的电平的控制下，下拉子电路50将第一电压端VGL的第一电压输出至第一节点PU和输出端OUT。
具体地，INPUT1＝0，INPUT2＝0，CN＝1，CKB＝1，CK＝0，PUCN＝0，PU＝0，PD＝1，OUT＝0。
在此情况下，在第二时钟信号端CKB的电平的控制下，第五晶体管T5导通，第二时钟信号端CKB的高电平通过第五晶体管T5输出至第二节点PD，并存储在第二电容C2中，使得第二节点PD保持在高电平；在第二节点PD的控制下，第七晶体管T7和第八晶体管T8导通，第一电压端VGL的第一电压通过第七晶体管T7输出至第一节点PU，第一电压端VGL的第一电压通过第八晶体管T8输出至输出端OUT，从而实现对第一节点PU和输出端OUT的复位。在第一节点PU的电平的控制下，第四晶体管T4关断。此外，第一晶体管T1、第二晶体管T2、第三晶体管T3处于关断状态。
在此基础上，在下一帧图像开始之前，当CKB＝0时，第五晶体管T5关断，在第二电容C2的作用下，第二节点PD保持高电平，以使得在第二节点PD的电平的控制下，第一节点PU和输出端OUT的电位维持低电平，保证该移位寄存器单元的正常输出。
综上所述，由于本公开实施例提供的移位寄存器单元在工作过程中第五晶体管T5和第六晶体管T6分时段导通，避免了二者同时导通时导致出现由第二时钟信号端CKB至第一电压端VGL的直流通路，且避免了第一节点PU和第二节点PD出现电位互相竞争的问题，使得第二节点PD充电效率更高、第一节点PU的电压更稳定，从而提高了移位寄存器单元的稳定性。
在此基础上(在图2所示的示例的基础上)，例如，如图5所示，本公开实施例提供的移位寄存器单元还可以包括第二输入子电路60，第二输入子电路60连接第三输入端INPUT3、第四输入端INPUT4、第二控制信号端CNB和控制节点PUCN，该第二输入子电路60配置为在第三输入端INPUT3的第三输入信号以及以及第二控制信号端CNB的第二控制信号的控制下，将第 四输入端INPUT4的第四输入信号输出至控制节点PUCN。
例如，如图6所示，第二输入子电路60包括第九晶体管T9和第十晶体管T10，第九晶体管T9的栅极连接第三输入端INPUT3以接收第三输入信号，第九晶体管T9的第一极连接第二控制信号端CNB以接收第二控制信号，第九晶体管T9第二极连接第十晶体管T10的栅极。第十晶体管T10的第一极连接第四输入端INPUT4以接收第四输入信号，第十晶体管T10的第二极连接控制节点PUCN。
在此情况下，由该移位寄存器级联构成的栅极驱动电路可以实现正向扫描和反向扫描，具体地，第一控制信号端CN和第二控制信号端CNB作为正向扫描和反向扫描的控制信号。以第九晶体管T9为N型晶体管为例，当CN＝0，CNB＝1(即第一控制信号为低电平，第二控制信号为高电平)时，上述栅极驱动电路可以用于进行反向扫描；当CN＝1，CNB＝0(即第一控制信号为高电平，第二控制信号为低电平)时，上述栅极驱动电路可以用于进行正向扫描。
当图6所示的移位寄存器用于正向扫描时，在输入阶段，第二输入子电路20不工作，其他子电路的工作过程与前述相同，此处不再赘述。当图6所示的移位寄存器用于反向扫描时，在输入阶段，第一输入子电路10不工作，第二输入子电路20工作，即在第三输入端INPUT3的第三输入信号以及第四输入端INPUT4的第四输入信号的控制下，第九晶体管T9和第十晶体管T10导通，第二控制信号端CNB与第十晶体管T10的栅极连接，使得第二控制信号端CNB的第二控制信号通过第九晶体管T9输出至第十晶体管T10的栅极，从而控制第十晶体管T10导通，将第四输入端INPUT4输入的第四输入信号输入至控制节点PUCN，从而控制第三晶体管T3导通；其他子电路的工作过程与前述相同，此处不再赘述。
需要说明的是，本公开示实施例中以各晶体管均为N型晶体管为例进行说明，本领域技术人员可以理解的是，当各晶体管均为P型时，只需对图4中的各时序信号反向即可，本实施例对此不再说明。
本公开实施例提供一种如前述实施例所述的移位寄存器单元的控制方法，如图4所示，包括：输入阶段P1、预充电阶段P2、输出阶段P3和复位阶段P4。
输入阶段P1，第一输入端INPUT1提供高电平(即第一输入信号为高电平)，第二时钟信号端CKB提供高电平，在第一输入端INPUT1的高电平的控制下，第一输入子电路10将第一控制信号端CN的高电平信号输出至上拉控制子电路20；在第二时钟信号端CKB的高电平的控制下，下拉控制子电路40将第二时钟信号端CKB的高电平信号输出至第二节点PD；在第二节点PD的电平的控制下，下拉子电路50将第一电压端VGL的第一电压输出至第一节点PU。
预充电阶段P2，第二输入端INPUT2提供高电平，第一时钟信号端CK提供低电平，例如，第一输入子电路10输出的第一控制信号可以维持至该预充电阶段P2，从而在第一输入子电路10输出的第一控制信号的控制下，上拉控制子电路20将第二输入端INPUT2的高电平信号输出至第一节点PU；上拉控制子电路20还将第二输入端INPUT2的高电平信号输出至下拉控制子电路40，在第二输入端INPUT2的高电平信号的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第二节点PD。
输出阶段P3：第一时钟信号端CK提供高电平，在第一节点PU的电平的控制下，输出子电路30将第一时钟信号端CK的高电平信号输出至输出端OUT。
复位阶段P4：第二时钟信号端CKB提供高电平，在第二时钟信号端CKB的高电平的控制下，下拉控制子电路40将第二时钟信号端CKB的高电平信号输出至第二节点PD；在第二节点PD的电平的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第一节点PU和输出端OUT。
需要说明的是，前述已经对上述各个阶段的工作过程进行了详细的说明，此处不再赘述。
基于此，本公开实施例提供的移位寄存器单元的控制方法，在输入阶段，在第一输入端INPUT1的第一输入信号的控制下，第一输入子电路10将第一控制信号端CN的第一控制信号输出至上拉控制子电路20；在第二时钟信号端CKB的第二时钟信号的控制下，下拉控制子电路40将第二时钟信号端CKB的第二时钟信号输出至第二节点PD；在第二节点PD的电平的控制下，下拉子电路50将第一电压端的第一电压输出至第一节点PU。在预充电阶段，在第一输入子电路10输出的第一控制信号的控制下，上拉控制子电路20将 第二输入端INPUT2的第二输入信号输出至第一节点PU；上拉控制子电路20还将第二输入端INPUT2的第二输入信号输出至下拉控制子电路40，在第二输入端INPUT2的第二输入信号的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第二节点PD，从而可以拉低第二节点PD的电平，以保证在该阶段对第一节点PU的正常充电。
综上所述，在输入阶段和预充电阶段，避免了第一节点PU和第二节点PD的电位互相竞争导致电路功耗增加的问题，以及避免了出现第五晶体管T5和第六晶体管T6同时导通时造成由第二时钟信号端CKB至第一电压端VGL的直流通路，从而提高了移位寄存器单元的稳定性。
本公开实施例提供一种移位寄存器单元，如图3所示，在一个示例中，该以为寄存器单元包括第一晶体管T1、第二晶体管T2、第三晶体管T3至第六晶体管T6以及第一电容C1和第二电容C2。
第一晶体管T1的栅极连接第一输入端INPUT1以接收第一输入信号，第一晶体管T1的第一极连接第一控制信号端CN以接收第一控制信号，第一晶体管T1的第二极连接第二晶体管T2的栅极；第二晶体管T2的第一极连接第二输入端INPUT2以接收第二输入信号，第二晶体管T2的第二极连接第三晶体管T3的栅极、第三晶体管T3的第一极以及第六晶体管T6的栅极，第三晶体管T3的第二极连接第一节点PU。
第四晶体管T4的栅极连接第一节点PU，第四晶体管T4的第一极连接第一时钟信号端CK以接收第一时钟信号，第四晶体管T4的第二极连接输出端OUT；第一电容C1的第一端连接第一节点PU，第一电容C1的第二端连接输出端OUT。
第五晶体管T5的栅极和第一极连接第二时钟信号端CKB以接收第二时钟信号，第五晶体管T5的第二极连接第二节点PD；第六晶体管T6的第一极连接第二节点PD，第六晶体管T6的第二极连接第一电压端VGL以接收第一电压；第二电容C2的第一端连接第二节点PD，第二端连接第一电压端VGL以接收第一电压。
例如，如图3所示，在另一个示例中，该移位寄存器单元还包括第七晶体管T7和第八晶体管T8。
第七晶体管T7的栅极连接第二节点PD，第七晶体管T7的第一极连接 第一节点PU，第七晶体管T7的第二极连接第一电压端VGL以接收第一电压；第八晶体管T8的栅极连接第二节点PD，第八晶体管T8的第一极连接输出端OUT，第八晶体管T8的第二极连接第一电压端VGL以接收第一电压。
需要说明的是，前述实施例已经对图3所示的移位寄存器单元的工作过程和有益效果进行了详细地说明，此处不再赘述。
在此基础上，例如，如图6所示，在图3所示的示例的基础上，该移位寄存器单元还包括第九晶体管T9和第十晶体管T10，第九晶体管T9的栅极连接第三输入端INPUT3以接收第三输入信号，第九晶体管T9的第一极连接第二控制信号端CNB以接收第二控制信号，第九晶体管T9第二极连接第一晶体管T1的第二极、第二晶体管T2的栅极以及第十晶体管T10的栅极；第十晶体管T10的第一极连接第四输入端INPUT4以接收第四输入信号，第十晶体管T10的第二极连接第三晶体管T3的栅极、第三晶体管T3的第一极以及第六晶体管T6的栅极。
例如，上述各晶体管(第一晶体管T1至第十晶体管T10)可以均为N型晶体管或者均为P型晶体管，本公开的实施例对此不作限制。
在此情况下，由该移位寄存器级联构成的栅极驱动电路可以实现正向扫描和反向扫描，前述实施例已经对图6所示的移位寄存器单元的工作过程和有益效果进行了详细的说明，此处不再赘述。
本公开至少一实施例还提供一种栅极驱动电路，包括多个级联的如前述实施例所述的移位寄存器单元。例如，图7中的栅极驱动电路以每个移位寄存器单元采用如图3所示电路结构为例进行说明，图8中以每个移位寄存器单元采用如图6所示电路结构为例进行说明，但是本公开的实施例不限于此。该栅极驱动电路可以采用与薄膜晶体管同样制程的工艺直接集成在显示装置的阵列基板上，以实现逐行扫描驱动功能。
如图7所示，第一级移位寄存器单元和第二级移位寄存器单元的第一输入端INPUT1连接第一信号端V1以接收触发信号；除了第一级移位寄存器单元和第二级移位寄存器单元以外，第N(N为大于等于3的整数)级移位寄存器单元的第一输入端INPUT1连接第N-2级移位寄存器单元的输出端OUT_(N-2)；
第一级移位寄存器单元的第二输入端INPUT2连接第二信号端V2；除了 第一级移位寄存器单元以外，第N级移位寄存器单元的第二输入端INPUT2连接第N-1级移位寄存器单元的输出端OUT_(N-1)。
本公开实施例提供的栅极驱动电路的移位寄存器单元具有与前述实施例提供的移位寄存器单元相同的结构和有益效果，由于前述已经对其结构和有益效果进行了详细的描述，此处不再赘述。
在此基础上，在上述移位寄存器单元包括第二输入子电路60或者第九晶体管T9和第十晶体管T10的情况下，如图8所示，除了最后两级移位寄存器单元以外，第N级移位寄存器单元的第三输入端INPUT3连接第N+2级移位寄存器单元的输出端OUT_(N+2)；最后一级移位寄存器单元的第四输入端INPUT4连接第二信号端V2；除了最后一级移位寄存器单元以外，第N级移位寄存器单元的第四输入端INPUT4连接第N+1级移位寄存器单元的输出端OUT_(N+1)；最后两级移位寄存器单元的第三输入端INPUT3连接第一信号端V1。在此情况下，该栅极驱动电路可以用于正向扫描和反向扫描。
例如，如图7或图8所示，OUT_1、OUT_2、OUT_3和OUT_4分别表示栅极驱动电路20中的第一级、第二级、第三级以及第四级移位寄存器单元中输出端，类似地，OUT_(N-1)、OUT_(N)分别表示第N-1级以及第N级移位寄存器单元中输出端，以此类推……。
如图7或图8所示，该栅极驱动电路还包括提第一时钟信号线CKL、第二时钟信号线CKBL、第三时钟信号线CKR和第四时钟信号线CKBR。
例如，如图7或图8所示，该移位寄存器单元还包括第一时钟信号端CK，且配置为第一时钟信号线CKL或第三时钟信号线CKR连接以接收第一时钟信号。例如第一时钟信号线CKL和第2m-1(m为大于0的整数)级移位寄存器单元的时钟信号端CK连接，第三时钟信号线CKR和第2m级移位寄存器单元的时钟信号端CK连接。需要说明的是，本公开的实施例包括但不限于上述连接方式，例如还可以采用：第一时钟信号线CKL和第2m级移位寄存器单元的时钟信号端CK连接，第三时钟信号线CKR和第2m-1级移位寄存器单元的时钟信号端CLK连接。
例如，该移位寄存器单元还包括第二时钟信号端CKB，且配置为分别和第二时钟信号线CKBL或第四时钟信号线CKBR连接以接收第二时钟信号。其具体连接方式与第一时钟信号端CK和第一时钟信号线CKL和第三时钟信 号线CKR的连接方式类似，在此不再赘述。
例如，该栅极驱动电路还包括第一控制信号线CN和第二控制信号线CNB，以分别提供第一控制信号和第二控制信号。例如，该移位寄存器单元还包括第一控制信号端CN和第二控制信号端CNB，且配置为分别和第一控制信号线CN和第二控制信号线CNB连接，以分别接收第一控制信号和第二控制信号。
需要注意的是，如图7或图8所示，CN既可以表示第一控制信号端又可以表示第一控制信号线(提供第一控制信号)，CNB既可以表示第二控制信号端又可以表示第二控制信号线(提供第二控制信号)。
例如，该栅极驱动电路还包括第一电压线VGL，以提供第一电压。例如，各级移位寄存器单元还包括第一电压端VGL，且配置为分别和第一电压线VGL连接以接收第一电压。需要注意的是，如图7或图8所示，VGL既可以表示第一电压端又可以表示第一电压线(提供第一电压)。
例如，该栅极驱动电路还可以包括时序控制器(图中未示出)。例如，该时序控制器可以被配置为和第一时钟信号线CKL、第二时钟信号线CKBL、第三时钟信号线CKR、第四时钟信号线CKBR、第一控制信号线CN、第二控制信号线CNB以及第一电压线VGL等连接，以向各移位寄存器单元提供时钟信号和控制信号和第一电压。例如，时序控制器还可以被配置为提供触发信号STV和复位信号RESET。
需要说明的是，当采用图7或图8所示的栅极驱动电路驱动一显示面板时，可以将该栅极驱动电路设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路中的各级移位寄存器单元的输出端可以配置为依序和该多行栅线连接，以用于输出栅极扫描信号。
例如，图7和图8所示的栅极驱动电路还可以用于对栅线进行双边交替驱动，示例的，偶数级移位寄存器单元设置在显示面板的一侧，其用于驱动偶数行栅线；奇数级移位寄存器单元设置在显示面板的另一侧，其用于驱动奇数行栅线。
在此情况下，参见图7和图8，本公开实施例提供的栅极驱动电路中的时钟信号可以以CKBL、CKBR、CKL、CKR的形式循环，即每相邻四级移位寄存器单元接入的时钟信号为一周期，具体地，如图9所示，CKBL、CKBR、 CKL、CKR的占空比均为25％，且同一时刻时钟信号CKBL、CKBR、CKL、CKR中仅有一个时钟信号为高电平。
需要注意的是，根据不同的配置，该栅极驱动电路还可以包括六条或八条时钟信号线等多条时钟信号线，时钟信号线的条数视具体情况而定，本公开的实施例在此不作限定。
本公开实施例提供一种显示装置，包括如图7或图8所示的栅极驱动电路。具有与前述实施例提供的栅极驱动电路相同的结构和有益效果。由于前述实施例已经对栅极驱动电路的结构和有益效果进行了详细的描述，此处不再赘述。
如图10所示，该显示装置1包括本公开实施例提供的栅极驱动电路200。该显示装置1还包括显示面板400，显示面板400包括由多个子像素单元410构成的阵列。例如，该显示装置1还可以包括数据驱动电路300。数据驱动电路300用于提供数据信号给像素阵列；栅极驱动电路200用于提供驱动信号给像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。数据驱动电路300通过数据线DL与子像素单元410电连接，栅极驱动电路200通过栅线GL与子像素单元410电连接。
需要说明的是，该显示装置具体至少可以包括液晶显示装置和有机发光二极管显示装置，例如该显示装置可以为液晶显示器、液晶电视、数码相框、手机或平板电脑等任何具有显示功能的产品或者部件。
本公开的实施例还提供一种移位寄存器单元的驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元100，例如，在一个示例中，该驱动方法包括如下操作。
输入阶段，在第一输入端INPUT1的第一输入信号的控制下，第一输入子电路10将第一控制信号端CN的第一控制信号输出至上拉控制子电路20；在第二时钟信号端CKB的第二时钟信号的控制下，下拉控制子电路40将第二时钟信号端CKB的第二时钟信号信号输出至第二节点PD；
预充电阶段，在第一输入子电路10输出的第一控制信号的控制下，上拉控制子电路20将第二输入端INPUT2的第二输入信号输出至第一节点PU；上拉控制子电路20还将第二输入端INPUT2的第二输入信号输出至下拉控制子电路40，在第二输入端INPUT2的第二输入信号的控制下，下拉控制子电 路40将第一电压端VGL的第一电压输出至第二节点PD；
输出阶段，在第一节点PU的电平的控制下，输出子电路30将输出信号输出至输出端OUT。
例如，在另一个示例中，移位寄存器单元还包括下拉子电路50，驱动方法还包括复位阶段。
例如，在输入阶段，在第二节点PD的电平的控制下，下拉子电路50将第一电压端VGL的第一电压输出至第一节点PU和输出端OUT；
在复位阶段，在第二时钟信号端CKB的第二时钟信号的控制下，下拉控制子电路40将第二时钟信号输出至第二节点PD；在第二节点PD的电平的控制下，下拉子电路50将第一电压端VGL的第一电压输出至第一节点PD和输出端OUT。
例如，在另一个示例中，采用反向扫描时，该驱动方法还包括：
输入阶段，在第三输入端INPUT3的第三输入信号的控制下，第二输入子电路60输出第二控制信号端CNB的第二控制信号；在第二时钟信号端CKB的第二时钟信号的控制下，下拉控制子电路40将所述第二时钟信号端CKB的第二时钟信号信号输出至所述第二节点；
预充电阶段，第一输入子电路10在第一控制信号的控制下输出第四输入端INPUT4的第四输入信号至控制节点PUCN，在控制节点PUCN的电平的控制下，上拉控制子电路20将第四输入端INPUT4的第四输入信号输出至第一节点PU；上拉控制子电路20还将第四输入端INPUT4的第四输入信号输出至下拉控制子电路40，在第四输入端INPUT4的第四输入信号的控制下，下拉控制子电路40将第一电压端VGL的第一电压输出至第二节点PD；
输出阶段，在第一节点PU的电平的控制下，输出子电路30将输出信号输出至输出端OUT。
需要说明的是，关于该驱动方法的详细描述以及技术效果可以参考本公开的实施例中对于移位寄存器单元100的工作原理的描述，这里不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种移位寄存器单元，包括：第一输入子电路、第一控制子电路、输出子电路和第二控制子电路；其中，
    所述第一输入子电路连接第一输入端、第一控制信号端和所述第一控制子电路，所述第一输入子电路配置为在所述第一输入端的第一输入信号的控制下，将所述第一控制信号端的第一控制信号输出至所述第一控制子电路；
    所述第一控制子电路连接第二输入端、第一节点和所述第二控制子电路，所述第一控制子电路配置为在所述第一输入子电路输出的第一控制信号的控制下，将所述第二输入端的第二输入信号输出至所述第一节点；或者，所述第一控制子电路配置为将所述第二输入信号输出至所述第二控制子电路；
    所述输出子电路连接所述第一节点和输出端，所述输出子电路配置为在所述第一节点的电平的控制下，将输出信号输出至所述输出端；
    所述第二控制子电路连接第二时钟信号端、第二节点、控制节点和第一电压端，所述第二控制子电路配置为在所述第二时钟信号端的第二时钟信号的控制下，将所述第二时钟信号输出至所述第二节点；或者，所述第二控制子电路配置为在所述控制节点的电平的控制下，将所述第一电压端的第一电压输出至所述第二节点。
  2. 根据权利要求1所述的移位寄存器单元，还包括降噪子电路；
    其中，所述降噪子电路连接所述第二节点、所述第一节点、所述第一电压端和所述输出端，所述降噪子电路配置为在所述第二节点的电平的控制下，将所述第一电压端的第一电压输出至所述第一节点和所述输出端。
  3. 根据权利要求1所述的移位寄存器单元，其中，所述第一输入子电路包括：
    第一晶体管，其中，所述第一晶体管的栅极连接所述第一输入端以接收所述第一输入信号，所述第一晶体管的第一极连接所述第一控制信号端以接收所述第一控制信号，所述第一晶体管的第二极作为所述第一输入子电路的输出端连接所述第一控制子电路。
  4. 根据权利要求1所述的移位寄存器单元，其中，所述第一控制子电路包括第二晶体管和第三晶体管；其中，
    所述第二晶体管的栅极连接所述第一输入子电路的输出端，所述第二晶体管的第一极连接所述第二输入端以接收所述第二输入信号，所述第二晶体管的第二极连接所述控制节点；
    所述第三晶体管的栅极和第一极彼此电连接，且分别配置为和所述控制节点连接，所述第三晶体管的第二极连接所述第一节点。
  5. 根据权利要求1所述的移位寄存器单元，其中，所述输出子电路包括第四晶体管和第一电容；其中，
    所述第四晶体管的栅极连接所述第一节点，所述第四晶体管的第一极连接第一时钟信号端以接收第一时钟信号作为所述输出信号，所述第四晶体管的第二极连接所述输出端；
    所述第一电容的第一端连接所述第一节点，所述第一电容的第二端连接所述输出端。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述第二控制子电路包括第五晶体管、第六晶体管和第二电容；其中，
    所述第五晶体管的栅极和第一极彼此电连接，且分别配置为和所述第二时钟信号端连接以接收所述第二时钟信号，所述第五晶体管的第二极连接所述第二节点；
    所述第六晶体管的栅极连接所述控制节点，所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极连接所述第一电压端以接收所述第一电压；
    所述第二电容的第一端连接所述第二节点，所述第二电容的第二端连接所述第一电压端以接收所述第一电压。
  7. 根据权利要求2所述的移位寄存器单元，其中，所述降噪子电路包括第七晶体管和第八晶体管；其中，
    所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的第一极连接所述第一节点，所述第七晶体管的第二极连接所述第一电压端以接收所述第一电压；
    所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一极连接所述输出端，所述第八晶体管的第二极连接所述第一电压端以接收所述第一电压。
  8. 根据权利要求1-7任一所述的移位寄存器单元，还包括第二输入子电路；
    其中，所述第二输入子电路连接第三输入端、第四输入端、第二控制信号端和所述控制节点，所述第二输入子电路配置为在所述第三输入端的第三输入信号以及所述第二控制信号端的第二控制信号的控制下，将所述第四输入端的第四输入信号输出至所述控制节点。
  9. 根据权利要求8所述的移位寄存器单元，其中，所述第二输入子电路包括第九晶体管和第十晶体管；
    其中，所述第九晶体管的栅极连接所述第三输入端以接收所述第三输入信号，所述第九晶体管的第一极连接所述第二控制信号端以接收所述第二控制信号，所述第九晶体管的第二极连接所述第十晶体管的栅极；
    所述第十晶体管的第一极连接所述第四输入端以接收所述第四输入信号，所述第十晶体管的第二极连接所述控制节点。
  10. 一种移位寄存器单元，包括第一晶体管、第二晶体管、第三晶体管、第四晶体管、第五晶体管、第六晶体管、第一电容和第二电容，其中：
    所述第一晶体管的栅极连接第一输入端以接收第一输入信号，所述第一晶体管的第一极连接第一控制信号端以接收第一控制信号，所述第一晶体管的第二极连接所述第二晶体管的栅极；
    所述第二晶体管的第一极连接第二输入端以接收第二输入信号，所述第二晶体管的第二极连接所述第三晶体管的栅极、所述第三晶体管的第一极以及所述第六晶体管的栅极；
    所述第三晶体管的第二极连接第一节点；
    所述第四晶体管的栅极连接所述第一节点，所述第四晶体管的第一极连接第一时钟信号端以接收第一时钟信号，所述第四晶体管的第二极连接输出端；
    所述第一电容的第一端连接所述第一节点，所述第一电容的第二端连接所述输出端；
    所述第五晶体管的栅极和第一极彼此电连接，且分别配置为与第二时钟信号端连接以接收第二时钟信号，所述第五晶体管的第二极连接第二节点；
    所述第六晶体管的第一极连接所述第二节点，所述第六晶体管的第二极 连接第一电压端以接收第一电压；
    所述第二电容的第一端连接所述第二节点，所述第二电容的第二端连接所述第一电压端以接收所述第一电压。
  11. 根据权利要求10所述的移位寄存器单元，还包括第七晶体管和第八晶体管；其中，
    所述第七晶体管的栅极连接所述第二节点，所述第七晶体管的第一极连接所述第一节点，所述第七晶体管的第二极连接所述第一电压端以接收所述第一电压；
    所述第八晶体管的栅极连接所述第二节点，所述第八晶体管的第一极连接所述输出端，所述第八晶体管的第二极连接所述第一电压端以接收所述第一电压。
  12. 根据权利要求11所述的移位寄存器单元，还包括第九晶体管和第十晶体管；其中
    所述第九晶体管的栅极连接第三输入端以接收第三输入信号，所述第九晶体管的第一极连接第二控制信号端以接收第二控制信号，所述第九晶体管的第二极连接所述第一晶体管的第二极、所述第二晶体管的栅极以及所述第十晶体管的栅极；
    所述第十晶体管的第一极连接第四输入端以接收第四输入信号，所述第十晶体管的第二极连接所述第三晶体管的栅极、所述第三晶体管的第一极以及所述第六晶体管的栅极。
  13. 根据权利要求12所述的移位寄存器单元，其中，所述第一晶体管至所述第十晶体管均为N型晶体管或者均为P型晶体管。
  14. 一种如权利要求1-9任一项所述的移位寄存器单元的驱动方法，包括：
    输入阶段，在所述第一输入端的第一输入信号的控制下，所述第一输入子电路将所述第一控制信号端的第一控制信号输出至所述第一控制子电路；在所述第二时钟信号端的第二时钟信号的控制下，所述第二控制子电路将所述第二时钟信号端的第二时钟信号信号输出至所述第二节点；
    预充电阶段，在所述第一输入子电路输出的第一控制信号的控制下，所述第一控制子电路将所述第二输入端的第二输入信号输出至所述第一节点； 所述第一控制子电路还将所述第二输入端的第二输入信号输出至所述第二控制子电路，在所述第二输入端的第二输入信号的控制下，所述第二控制子电路将所述第一电压端的第一电压输出至所述第二节点；
    输出阶段，在所述第一节点的电平的控制下，所述输出子电路将所述输出信号输出至所述输出端。
  15. 根据权利要求14所述驱动方法，所述移位寄存器单元还包括降噪子电路，所述驱动方法还包括复位阶段；其中，
    在所述输入阶段，在所述第二节点的电平的控制下，所述降噪子电路将第一电压端的第一电压输出至所述第一节点和所述输出端；
    在所述复位阶段，在所述第二时钟信号端的第二时钟信号的控制下，所述第二控制子电路将所述第二时钟信号输出至所述第二节点；在所述第二节点的电平的控制下，所述降噪子电路将所述第一电压端的第一电压输出至所述第一节点和所述输出端。
  16. 一种如权利要求8所述的移位寄存器单元的驱动方法，包括：
    输入阶段，在所述第三输入端的第三输入信号的控制下，所述第二输入子电路输出所述第二控制信号端的第二控制信号；在所述第二时钟信号端的第二时钟信号的控制下，所述第二控制子电路将所述第二时钟信号端的第二时钟信号信号输出至所述第二节点；
    预充电阶段，所述第二输入子电路在所述第二控制信号的控制下输出所述第四输入端的第四输入信号至所述控制节点，在所述控制节点的电平的控制下，所述第一控制子电路将所述第四输入端的第四输入信号输出至所述第一节点；所述第一控制子电路还将所述第四输入端的第四输入信号输出至所述第二控制子电路，在所述第四输入端的第四输入信号的控制下，所述第二控制子电路将所述第一电压端的第一电压输出至所述第二节点；
    输出阶段，在所述第一节点的电平的控制下，所述输出子电路将所述输出信号输出至所述输出端。
  17. 一种栅极驱动电路，包括多个级联的如权利要求1-9任一项所述的移位寄存器单元，或者包括多个级联的如权利要求10-13任一所述的移位寄存器单元；其中，
    第一级移位寄存器单元和第二级移位寄存器单元的第一输入端连接第一 信号端；除了所述第一级移位寄存器单元和所述第二级移位寄存器单元以外，第N级移位寄存器单元的第一输入端连接第N-2级移位寄存器单元的输出端；
    所述第一级移位寄存器单元的第二输入端连接第二信号端；除了所述第一级移位寄存器单元以外，所述第N级移位寄存器单元的第二输入端连接第N-1级移位寄存器单元的输出端；
    其中，N为大于等于3的整数。
  18. 根据权利要求17所述的栅极驱动电路，其中，在所述移位寄存器单元包括第二输入子电路，或者包括第九晶体管和第十晶体管的情况下，
    除了最后两级移位寄存器单元以外，所述第N级移位寄存器单元的第三输入端连接第N+2级移位寄存器单元的输出端；
    除了最后一级移位寄存器单元以外，所述第N级移位寄存器单元的第四输入端连接第N+1级移位寄存器单元的输出端；
    其中，所述最后两级移位寄存器单元的第三输入端连接所述第一信号端，所述最后一级移位寄存器单元的第四输入端连接所述第二信号端。
  19. 一种显示装置，包括如权利要求17或18所述的栅极驱动电路。
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