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WO2023050086A1 - 移位寄存器及其驱动方法、栅极驱动电路、显示装置 - Google Patents

移位寄存器及其驱动方法、栅极驱动电路、显示装置 Download PDF

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Publication number
WO2023050086A1
WO2023050086A1 PCT/CN2021/121419 CN2021121419W WO2023050086A1 WO 2023050086 A1 WO2023050086 A1 WO 2023050086A1 CN 2021121419 W CN2021121419 W CN 2021121419W WO 2023050086 A1 WO2023050086 A1 WO 2023050086A1
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WO
WIPO (PCT)
Prior art keywords
transistor
electrically connected
pull
terminal
pole
Prior art date
Application number
PCT/CN2021/121419
Other languages
English (en)
French (fr)
Inventor
闫伟
王珍
秦文文
张寒
王德帅
张健
山岳
杨小艳
张亚东
孙建
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2021/121419 priority Critical patent/WO2023050086A1/zh
Priority to CN202180002732.2A priority patent/CN116547741A/zh
Priority to US17/794,991 priority patent/US20240212772A1/en
Publication of WO2023050086A1 publication Critical patent/WO2023050086A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to but not limited to the field of display technology, and specifically relates to a shift register and a driving method thereof, a gate driving circuit, and a display device.
  • flat panel displays such as Thin Film Transistor-Liquid Crystal Display (TFT-LCD) and Active Matrix Organic Light Emitting Diode (AMOLED), have light weight, Due to the advantages of thin thickness and low power consumption, it is widely used in electronic products such as TVs and mobile phones.
  • TFT-LCD Thin Film Transistor-Liquid Crystal Display
  • AMOLED Active Matrix Organic Light Emitting Diode
  • GOA Gate Driver on Array
  • the present disclosure provides a shift register, including: a pull-up control subcircuit, a pull-down control subcircuit, an output subcircuit, and a noise reduction subcircuit;
  • the pull-up control subcircuit is electrically connected to the first input terminal, the second output terminal, the first signal terminal, the second signal terminal and the pull-up control node, and is configured to control the first input terminal and the second output terminal Next, pull up the control node to provide the signal of the first signal terminal or the second signal terminal;
  • the pull-down control sub-circuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first signal terminal, the second signal terminal, the pull-up control node, the pull-down node, the first power supply terminal and the second power supply terminal respectively , set to provide a signal of the first power supply terminal or the second power supply terminal to the pull-up node under the control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal;
  • the output sub-circuit is electrically connected to the pull-up control node, the first power supply terminal, the third clock signal terminal, the first output terminal, the fourth clock signal terminal and the second output terminal, and is configured to be connected between the pull-up control node and the second output terminal. Under the control of the first power supply terminal, the signal of the third clock signal terminal is provided to the first output terminal, and the signal of the fourth clock signal terminal is provided to the second output terminal;
  • the noise reduction sub-circuit is electrically connected to the pull-up control node, the first output terminal, the second output terminal, the pull-down node and the second power supply terminal respectively, and is configured to pull up the control node, the first power supply terminal under the control of the pull-down node
  • the output terminal and the second output terminal provide the signal of the second power supply terminal.
  • the output subcircuit includes: a first output subcircuit and a second output subcircuit;
  • the first output sub-circuit is electrically connected to the pull-up control node, the first power supply terminal, the third clock signal terminal and the first output terminal respectively, and is set under the control of the first power supply terminal and the pull-up control node, to The first output end provides the signal of the third clock signal end;
  • the second output sub-circuit is electrically connected to the pull-up control node, the first power supply terminal, the fourth clock signal terminal and the second output terminal respectively, and is configured to send to The second output terminal provides the signal of the fourth clock signal terminal.
  • it also includes: a reset subcircuit
  • the reset subcircuit is electrically connected to the reset signal terminal, the pull-up control node and the second power supply terminal respectively, and is configured to provide the signal of the second power supply terminal to the pull-up control node under the control of the reset signal terminal.
  • the pull-up control subcircuit includes: a first transistor and a second transistor;
  • the control pole of the first transistor is electrically connected to the first input terminal, the first pole of the first transistor is electrically connected to the first signal terminal, and the second pole of the first transistor is electrically connected to the pull-up control node;
  • the control pole of the second transistor is electrically connected to the second input terminal, the first pole of the second transistor is electrically connected to the second signal terminal, and the second pole of the second transistor is electrically connected to the pull-up control node.
  • the pull-down control subcircuit includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a first capacitor;
  • the control pole of the third transistor is electrically connected to the first signal terminal, the first pole of the third transistor is electrically connected to the first clock signal terminal, and the second pole of the third transistor is electrically connected to the pull-down control node;
  • the control pole of the fourth transistor is electrically connected to the second signal terminal, the first pole of the fourth transistor is electrically connected to the second clock signal terminal, and the second pole of the fourth transistor is electrically connected to the pull-down control node;
  • the control pole of the fifth transistor is electrically connected to the pull-down control node, the first pole of the fifth transistor is electrically connected to the first power supply terminal, and the second pole of the fifth transistor is electrically connected to the pull-down node;
  • the control electrode of the sixth transistor is electrically connected to the pull-up control node, the first electrode of the sixth transistor is electrically connected to the pull-down node, and the second electrode of the sixth transistor is electrically connected to the second power supply terminal;
  • the first pole of the first capacitor is electrically connected to the pull-down node, and the second pole of the first capacitor is electrically connected to the second power supply terminal.
  • the first output subcircuit includes: a seventh transistor, an eighth transistor, and a second capacitor;
  • the control pole of the seventh transistor is electrically connected to the first power supply terminal, the first pole of the seventh transistor is electrically connected to the pull-up control node, and the second pole of the seventh transistor is electrically connected to the first pull-up node ;
  • the control pole of the eighth transistor is electrically connected to the first pull-up node, the first pole of the eighth transistor is electrically connected to the third clock signal terminal, and the second pole of the eighth transistor is electrically connected to the first output terminal. connect;
  • a first pole of the second capacitor is electrically connected to the first pull-up node, and a second pole of the second capacitor is electrically connected to the first output terminal.
  • the second output subcircuit includes: a ninth transistor, a tenth transistor, and a third capacitor;
  • the control pole of the ninth transistor is electrically connected to the first power supply terminal, the first pole of the ninth transistor is electrically connected to the pull-up control node, and the second pole of the ninth transistor is electrically connected to the second pull-up node ;
  • the control pole of the tenth transistor is electrically connected to the second pull-up node, the first pole of the tenth transistor is electrically connected to the fourth clock signal terminal, and the second pole of the tenth transistor is electrically connected to the second output terminal. connect;
  • a first pole of the third capacitor is electrically connected to the second pull-up node, and a second pole of the third capacitor is electrically connected to the second output terminal.
  • the noise reduction sub-circuit includes: an eleventh transistor, a twelfth transistor, and a thirteenth transistor;
  • the control pole of the eleventh transistor is electrically connected to the pull-down node, the first pole of the eleventh transistor is electrically connected to the pull-up control node, and the second pole of the eleventh transistor is electrically connected to the second power supply terminal ;
  • the control pole of the twelfth transistor is electrically connected to the pull-down node, the first pole of the twelfth transistor is electrically connected to the first output terminal, and the second pole of the twelfth transistor is electrically connected to the second power supply terminal ;
  • the control pole of the thirteenth transistor is electrically connected to the pull-down node, the first pole of the thirteenth transistor is electrically connected to the second output terminal, and the second pole of the thirteenth transistor is electrically connected to the second power supply terminal .
  • the reset subcircuit includes: a fourteenth transistor
  • the control pole of the fourteenth transistor is electrically connected to the reset signal terminal, the first pole of the fourteenth transistor is electrically connected to the pull-up control node, and the second pole of the fourteenth transistor is electrically connected to the second power supply terminal. connect.
  • a reset subcircuit is also included, the pull-up control subcircuit includes: a first transistor and a second transistor; the pull-down control subcircuit includes: a third transistor, a fourth transistor, and a fifth transistor , the sixth transistor and the first capacitor; the output sub-circuit includes: the seventh transistor, the eighth transistor, the second capacitor, the ninth transistor, the tenth transistor and the third capacitor; the noise reduction sub-circuit includes: the tenth A transistor, a twelfth transistor, and a thirteenth transistor; the reset subcircuit includes: a fourteenth transistor;
  • the control pole of the first transistor is electrically connected to the first input terminal, the first pole of the first transistor is electrically connected to the first signal terminal, and the second pole of the first transistor is electrically connected to the pull-up control node;
  • the control pole of the second transistor is electrically connected to the second input terminal, the first pole of the second transistor is electrically connected to the second signal terminal, and the second pole of the second transistor is electrically connected to the pull-up control node;
  • the control pole of the third transistor is electrically connected to the first signal terminal, the first pole of the third transistor is electrically connected to the first clock signal terminal, and the second pole of the third transistor is electrically connected to the pull-down control node;
  • the control pole of the fourth transistor is electrically connected to the second signal terminal, the first pole of the fourth transistor is electrically connected to the second clock signal terminal, and the second pole of the fourth transistor is electrically connected to the pull-down control node;
  • the control pole of the fifth transistor is electrically connected to the pull-down control node, the first pole of the fifth transistor is electrically connected to the first power supply terminal, and the second pole of the fifth transistor is electrically connected to the pull-down node;
  • the control electrode of the sixth transistor is electrically connected to the pull-up control node, the first electrode of the sixth transistor is electrically connected to the pull-down node, and the second electrode of the sixth transistor is electrically connected to the second power supply terminal;
  • the first pole of the first capacitor is electrically connected to the pull-down node, and the second pole of the first capacitor is electrically connected to the second power supply terminal;
  • the control pole of the seventh transistor is electrically connected to the first power supply terminal, the first pole of the seventh transistor is electrically connected to the pull-up control node, and the second pole of the seventh transistor is electrically connected to the first pull-up node ;
  • the control pole of the eighth transistor is electrically connected to the first pull-up node, the first pole of the eighth transistor is electrically connected to the third clock signal terminal, and the second pole of the eighth transistor is electrically connected to the first output terminal. connect;
  • the first pole of the second capacitor is electrically connected to the first pull-up node, and the second pole of the second capacitor is electrically connected to the first output terminal;
  • the control pole of the ninth transistor is electrically connected to the first power supply terminal, the first pole of the ninth transistor is electrically connected to the pull-up control node, and the second pole of the ninth transistor is electrically connected to the second pull-up node ;
  • the control pole of the tenth transistor is electrically connected to the second pull-up node, the first pole of the tenth transistor is electrically connected to the fourth clock signal terminal, and the second pole of the tenth transistor is electrically connected to the second output terminal. connect;
  • the first pole of the third capacitor is electrically connected to the second pull-up node, and the second pole of the third capacitor is electrically connected to the second output terminal;
  • the control pole of the eleventh transistor is electrically connected to the pull-down node, the first pole of the eleventh transistor is electrically connected to the pull-up control node, and the second pole of the eleventh transistor is electrically connected to the second power supply terminal ;
  • the control pole of the twelfth transistor is electrically connected to the pull-down node, the first pole of the twelfth transistor is electrically connected to the first output terminal, and the second pole of the twelfth transistor is electrically connected to the second power supply terminal ;
  • the control pole of the thirteenth transistor is electrically connected to the pull-down node, the first pole of the thirteenth transistor is electrically connected to the second output terminal, and the second pole of the thirteenth transistor is electrically connected to the second power supply terminal ;
  • the control pole of the fourteenth transistor is electrically connected to the reset signal terminal, the first pole of the fourteenth transistor is electrically connected to the pull-up control node, and the second pole of the fourteenth transistor is electrically connected to the second power supply terminal. connect.
  • the present disclosure also provides a gate drive circuit, comprising a plurality of the above-mentioned shift registers cascaded;
  • the first input end of the i+1th stage shift register is electrically connected to the first output end of the i stage shift register, and the second input end of the i+1th stage shift register is connected to the i+2th stage shift register
  • the second output terminal is electrically connected.
  • it also includes: an initial signal line, a first clock line, a second clock line, a third clock line, a fourth clock line, a fifth clock line, a sixth clock line, a reset signal line, a a power line, a second power line, a first signal line and a second signal line;
  • the reset signal terminals of all the shift registers are connected to the reset signal line, the first power supply terminals of all the shift registers are connected to the first power supply line, the second power supply terminals of all the shift registers are connected to the second power supply line, and all the shift registers
  • the first signal terminals of the shift registers are connected to the first signal lines, and the second signal terminals of all the shift registers are connected to the second signal lines;
  • the first input end of the first stage shift register is connected to the initial signal line, the first clock signal end of the 3i-2 stage shift register is connected to the sixth clock line, and the second clock of the 3i-2 stage shift register
  • the signal end is connected to the first clock line, the third clock signal end of the 3i-2 shift register is connected to the third clock line, and the fourth clock signal end of the 3i-2 shift register is connected to the fourth clock line
  • the first clock signal end of the 3i-1 stage shift register is connected to the second clock line
  • the second clock signal end of the 3i-1 stage shift register is connected to the third clock line
  • the 3i-1 stage shift register
  • the third clock signal end of the register is connected to the fifth clock line
  • the fourth clock signal end of the 3i-1 stage shift register is connected to the sixth clock line
  • the first clock signal end of the 3i stage shift register is connected to the fourth
  • the clock line is connected, the second clock signal end of the 3i-level shift register is connected to the fifth clock line, the third clock signal end of the 3i-
  • the present disclosure also provides a display device, including: the above-mentioned gate driving circuit and a plurality of scanning signal lines; the scanning signal lines extend along the first direction, and the plurality of scanning signal lines are arranged along the second direction , the first direction and the second direction intersect;
  • the jth stage shift register in the gate drive circuit is connected to the 2j-1th scan signal line and the 2jth scan signal line, 1 ⁇ j ⁇ N, N is the shift register included in the gate drive circuit quantity.
  • the length of the gate driving circuit along the first direction is about 0.35 mm to 0.37 mm.
  • the present disclosure also provides a method for driving a shift register, wherein the method is configured to drive the above-mentioned shift register, and the method includes:
  • the pull-up control subcircuit Under the control of the first input terminal and the second output terminal, the pull-up control subcircuit provides the signal of the first signal terminal or the second signal terminal to the pull-up control node;
  • the pull-down control subcircuit Under the control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal, the pull-down control subcircuit provides a signal of the first power supply terminal or the second power supply terminal to the pull-down node;
  • the output subcircuit Under the control of the pull-up control node and the first power supply terminal, the output subcircuit provides the signal of the third clock signal terminal to the first output terminal, and provides the signal of the fourth clock signal terminal to the second output terminal;
  • the noise reduction sub-circuit Under the control of the pull-down node, the noise reduction sub-circuit provides the signal of the second power supply terminal to the pull-up control node, the first output terminal and the second output terminal.
  • it further includes: under the control of the reset signal terminal, the reset subcircuit provides the signal of the second power supply terminal to the pull-up control node.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure
  • Fig. 2 is a schematic structural diagram of a shift register provided by an exemplary embodiment
  • Fig. 3 is an equivalent circuit diagram of a pull-up control subcircuit provided by an exemplary embodiment
  • FIG. 4 is an equivalent circuit diagram of a pull-down control subcircuit provided by an exemplary embodiment
  • FIG. 5 is an equivalent circuit diagram of an output subcircuit provided by an exemplary embodiment
  • Fig. 6 is an equivalent circuit diagram of a noise reduction sub-circuit provided by an exemplary embodiment
  • FIG. 7 is an equivalent circuit diagram of a reset subcircuit provided by an exemplary embodiment
  • FIG. 8 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment
  • FIG. 9 is a working timing diagram 1 of a shift register provided by an exemplary embodiment
  • FIG. 10 is a second working timing diagram of a shift register provided by an exemplary embodiment
  • FIG. 11 is a flowchart of a driving method of a shift register provided by an embodiment of the present disclosure.
  • FIG. 12 is a schematic structural diagram of a gate drive circuit provided by an embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • connection should be interpreted in a broad sense.
  • it may be a fixed connection, or a detachable connection, or an integral connection; it may be a mechanical connection, or an electrical connection; it may be a direct connection, or an indirect connection through an intermediate piece, or an internal communication between two components.
  • a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode .
  • a channel region refers to a region through which current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the functions of the "source electrode” and “drain electrode” may be interchanged. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged with each other.
  • electrically connected includes the case where constituent elements are connected together through an element having some kind of electrical function.
  • the "element having some kind of electrical action” is not particularly limited as long as it can transmit and receive electrical signals between connected components.
  • Examples of “elements having some kind of electrical function” include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • a GOA circuit in a display device includes a plurality of shift registers.
  • the GOA circuit includes many devices and occupies a large area, so that the display device cannot realize a narrow frame and consumes a large amount of power.
  • FIG. 1 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure.
  • the shift register provided by the embodiment of the present disclosure may include: a pull-up control subcircuit, a pull-down control subcircuit, an output subcircuit and a noise reduction subcircuit.
  • the pull-up control subcircuit is electrically connected to the first input terminal INPUT1, the second output terminal OUTPUT2, the first signal terminal CN, the second signal terminal CNB and the pull-up control node PUCN, and is set to be connected to the first input terminal INPUT1.
  • the pull-up control node PUCN provides the signal of the first signal terminal CN or the second signal terminal CNB.
  • the pull-down control sub-circuit is respectively connected to the first clock signal terminal CK1, the second clock signal terminal CK2, the first signal terminal CN, the second signal terminal CNB, the pull-up control node PUCN, the pull-down node PD, the first power supply terminal VGH and the second
  • the two power supply terminals VGL are electrically connected, and are set to provide power to the pull-up node PD under the control of the pull-up control node PUCN, the first signal terminal CN, the second signal terminal CNB, the first clock signal terminal CK1 and the second clock signal terminal CK2.
  • the output sub-circuit is electrically connected to the pull-up control node PUCN, the first power supply terminal VGH, the third clock signal terminal CK3, the first output terminal OUTPUT1, the fourth clock signal terminal CK4 and the second output terminal OUTPUT2, and is set to be on Under the control of the pull control node PUCN and the first power supply terminal VGH, the signal of the third clock signal terminal CK3 is provided to the first output terminal OUTPUT1, and the signal of the fourth clock signal terminal CK4 is provided to the second output terminal OUTPUT2.
  • the noise reduction sub-circuit is electrically connected to the pull-up control node PUCN, the first output terminal OUTPUT1, the second output terminal OUTPUT2, the pull-down node PD, and the second power supply terminal VGL, and is set to be controlled by the pull-up node PD.
  • the node PUCN, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 provide the signal of the second power supply terminal VGL.
  • the first output terminal OUTPUT1 and the second output terminal OUTPUT2 of the shift register respectively output two different driving signals.
  • the time when the first output terminal OUTPUT1 outputs the active level signal does not coincide with the time when the second output terminal OUTPUT2 outputs the active level signal.
  • the active level signal refers to a signal that can turn on the transistor.
  • the input signal of the first input terminal INPUT1 is a pulse signal
  • the input signal of the second input terminal INPUT2 is a pulse signal
  • the input signal of the reset signal terminal RESET is a pulse signal
  • the first power supply terminal VGH continuously provides a high-level signal
  • the second power supply terminal VGL continuously provides a low-level signal
  • the input signals of the first clock signal terminal CK1 , the second clock signal terminal CK2 , the third clock signal terminal CK3 and the fourth clock signal terminal CK4 are clock signals.
  • the time when the input signal of the third clock signal terminal CK3 is an active level signal does not coincide with the time when the input signal of the fourth clock signal terminal CK4 is an active level signal.
  • the modes of the gate driving circuit where the shift register is located may include: a forward scanning mode and a reverse scanning mode.
  • the output of the shift register at this stage occurs after the output of the shift register at the previous stage; when the gate drive circuit is in the reverse scan mode, the output of the shift register at this stage Occurs after the output of the shift register of the next stage.
  • the time when the input signal of the first signal terminal CN of the shift register of this stage is an active level signal and the time when the input signal of the first clock signal terminal CK1 is an active level signal coincidentally, the time when the input signal of the second signal terminal CNB of the current shift register is a valid level signal does not coincide with the time when the input signal of the second clock signal terminal CK2 is a valid level signal.
  • the invalid level signal refers to a signal that can turn off the transistor.
  • the noise reduction sub-circuit in the present disclosure can reduce the noise in the shift register, and improve the working stability, reliability and display effect of the display device.
  • the shift register includes: including: a pull-up control subcircuit, a pull-down control subcircuit, an output subcircuit, and a noise reduction subcircuit; the pull-up control subcircuit is connected to the first input terminal and the second output terminal respectively , the first signal terminal, the second signal terminal and the pull-up control node are electrically connected, and are set to provide the pull-up control node with the signal of the first signal terminal or the second signal terminal under the control of the first input terminal and the second output terminal; pull-down The control subcircuit is electrically connected to the first clock signal terminal, the second clock signal terminal, the first signal terminal, the second signal terminal, the pull-up control node, the pull-down node, the first power supply terminal and the second power supply terminal, and is configured as Under the control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal, the signal of the first power supply terminal or the second power supply terminal is provided to the pull-down
  • the output subcircuit may include: a first output subcircuit and a second output subcircuit.
  • the first output sub-circuit is electrically connected to the pull-up control node PUCN, the first power supply terminal VGH, the third clock signal terminal CK3 and the first output terminal OUTPUT1 respectively, and is set as the first power supply terminal VGH and the pull-up control node Under the control of PUCN, the signal of the third clock signal terminal CK3 is provided to the first output terminal OUTPUT1.
  • the second output sub-circuit is electrically connected to the pull-up control node PUCN, the first power supply terminal VGH, the fourth clock signal terminal CK4 and the second output terminal OUTPUT2 respectively, and is set to be connected between the first power supply terminal VGH and the pull-up control node PUCN. Under control, the signal of the fourth clock signal terminal CK4 is provided to the second output terminal OUTPUT2.
  • Fig. 2 is a schematic structural diagram of a shift register provided by an exemplary embodiment.
  • the shift register may further include: a reset subcircuit.
  • the reset subcircuit is electrically connected to the reset signal terminal RESET, the pull-up control node PUCN and the second power supply terminal VGL respectively, and is set to provide the pull-up control node PUCN with the second power supply terminal VGL under the control of the reset signal terminal RESET. Signal.
  • the reset subcircuit in the present disclosure can reset the shift register, reduce the noise in the shift register, and improve the working stability, reliability and display effect of the display device.
  • Fig. 3 is an equivalent circuit diagram of a pull-up control sub-circuit provided by an exemplary embodiment.
  • the pull-up control subcircuit includes: a first transistor T1 and a second transistor T2 .
  • control electrode of the first transistor T1 is electrically connected to the first input terminal INPUT1, the first electrode of the first transistor T1 is electrically connected to the first signal terminal CN, and the second electrode of the first transistor T1 It is electrically connected to the pull-up control node PUCN;
  • control pole of the second transistor T2 is electrically connected to the second input terminal INPUT2, the first pole of the second transistor T2 is electrically connected to the second signal terminal CNB, and the second pole of the second transistor T2 It is electrically connected with the pull-up control node PUCN.
  • FIG. 3 shows an exemplary structure of the pull-up control subcircuit, and the present disclosure is not limited thereto.
  • Fig. 4 is an equivalent circuit diagram of a pull-down control sub-circuit provided by an exemplary embodiment.
  • the pull-down control subcircuit may include: a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 and a first capacitor C1 .
  • the control electrode of the third transistor T3 is electrically connected to the first signal terminal CN, the first electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK1, and the second electrode of the third transistor T3 pole is electrically connected to the pull-down control node PDCN;
  • the control pole of the fourth transistor T4 is electrically connected to the second signal terminal CNB, the first pole of the fourth transistor T4 is electrically connected to the second clock signal terminal CK2, and the second pole of the fourth transistor T4 pole is electrically connected to the pull-down control node PDCN;
  • the control pole of the fifth transistor T5 is electrically connected to the pull-down control node PDCN, the first pole of the fifth transistor T5 is electrically connected to the first power supply terminal VGH, and the second pole of the fifth transistor T5 is electrically connected to the first power supply terminal VGH.
  • the pull-down node PD is electrically connected; the control pole of the sixth transistor T6 is electrically connected to the pull-up control node PUCN, the first pole of the sixth transistor T6 is electrically connected to the pull-down node PD, and the second pole of the sixth transistor T6 is connected to the second power terminal VGL is electrically connected; the first pole of the first capacitor C1 is electrically connected to the pull-down node PD, and the second pole of the first capacitor C1 is electrically connected to the second power supply terminal VGL.
  • the sixth transistor T6 in the present disclosure is controlled by the pull-up control node PUCN.
  • the signal of the pull-up control node PUCN is an active level signal
  • the sixth transistor T6 is turned on, and the signal of the pull-down node PD is controlled by the second power supply terminal VGL. Pulling the low-level signal low can avoid the formation of a current path in the shift register, and can reduce the power consumption of the display device.
  • FIG. 4 shows an exemplary structure of the pull-up control subcircuit, and the present disclosure is not limited thereto.
  • Fig. 5 is an equivalent circuit diagram of an output sub-circuit provided by an exemplary embodiment.
  • the first output subcircuit of the output subcircuits may include: a seventh transistor T7 , an eighth transistor T8 and a second capacitor C2 .
  • the second output sub-circuit may include: a ninth transistor T9, a tenth transistor T10 and a third capacitor C3.
  • the control electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, the first electrode of the seventh transistor T7 is electrically connected to the pull-up control node PUCN, and the second electrode of the seventh transistor T7 It is electrically connected to the first pull-up node PU1; the control pole of the eighth transistor T8 is electrically connected to the first pull-up node PU1, the first pole of the eighth transistor T8 is electrically connected to the third clock signal terminal CK3, and the eighth transistor T8 The second pole is electrically connected to the first output terminal OUTPUT1; the first pole of the second capacitor C2 is electrically connected to the first pull-up node PU1, and the second pole of the second capacitor C2 is electrically connected to the first output terminal OUTPUT1.
  • the control pole of the ninth transistor T9 is electrically connected to the first power supply terminal VGH, the first pole of the ninth transistor T9 is electrically connected to the pull-up control node PUCN, and the second pole of the ninth transistor T9 is electrically connected to the second pull-up node PU2 ;
  • the control pole of the tenth transistor T10 is electrically connected to the second pull-up node PU2, the first pole of the tenth transistor T10 is electrically connected to the fourth clock signal terminal CK4, and the second pole of the tenth transistor T10 is electrically connected to the second output terminal OUTPUT2 Electrically connected;
  • the first pole of the third capacitor C3 is electrically connected to the second pull-up node PU2, and the second pole of the third capacitor C3 is electrically connected to the second output terminal OUTPUT2.
  • FIG. 5 shows an exemplary structure of the output sub-circuit, and the disclosure is not limited thereto.
  • Fig. 6 is an equivalent circuit diagram of a noise reduction sub-circuit provided by an exemplary embodiment.
  • the noise reduction sub-circuit may include: an eleventh transistor T11 , a twelfth transistor T12 and a thirteenth transistor T13 .
  • the control electrode of the eleventh transistor T11 is electrically connected to the pull-down node PD, the first electrode of the eleventh transistor T11 is electrically connected to the pull-up control node PUCN, and the second electrode of the eleventh transistor T11 pole is electrically connected to the second power supply terminal VGL;
  • the control pole of the twelfth transistor T12 is electrically connected to the pull-down node PD, the first pole of the twelfth transistor T12 is electrically connected to the first output terminal OUTPUT1, and the control pole of the twelfth transistor T12 is electrically connected to the first output terminal OUTPUT1.
  • the two poles are electrically connected to the second power supply terminal VGL; the control pole of the thirteenth transistor T13 is electrically connected to the pull-down node PD, the first pole of the thirteenth transistor T13 is electrically connected to the second output terminal OUTPUT2, and the control pole of the thirteenth transistor T13 is electrically connected to the second output terminal OUTPUT2.
  • the second pole is electrically connected to the second power supply terminal VGL.
  • FIG. 6 an exemplary structure of the noise reduction sub-circuit is shown in FIG. 6 , and the present disclosure is not limited thereto.
  • Fig. 7 is an equivalent circuit diagram of a reset subcircuit provided by an exemplary embodiment. As shown in FIG. 7, in an exemplary embodiment, the reset subcircuit may include: a fourteenth transistor T14.
  • control electrode of the fourteenth transistor T14 is electrically connected to the reset signal terminal RESET, the first electrode of the fourteenth transistor T14 is electrically connected to the pull-up control node PUCN, and the second electrode of the fourteenth transistor T14 The pole is electrically connected to the second power supply terminal VGL.
  • FIG. 7 shows an exemplary structure of the reset subcircuit, and the present disclosure is not limited thereto.
  • Fig. 8 is an equivalent circuit diagram of a shift register provided by an exemplary embodiment.
  • the shift register may further include a reset subcircuit
  • the pull-up control subcircuit includes: a first transistor T1 and a second transistor T2
  • the pull-down control subcircuit includes: a third Transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6 and first capacitor
  • the output sub-circuit includes: seventh transistor T7, eighth transistor T8, second capacitor, ninth transistor T9, tenth transistor T10 and the third capacitor
  • the noise reduction sub-circuit includes: the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13
  • the reset sub-circuit includes: the fourteenth transistor T14.
  • the control electrode of the first transistor T1 is electrically connected to the first input terminal INPUT1, the first electrode of the first transistor T1 is electrically connected to the first signal terminal CN, and the second electrode of the first transistor T1 It is electrically connected to the pull-up control node PUCN;
  • the control pole of the second transistor T2 is electrically connected to the second input terminal INPUT2, the first pole of the second transistor T2 is electrically connected to the second signal terminal CNB, and the second pole of the second transistor T2 It is electrically connected to the pull-up control node PUCN;
  • the control pole of the third transistor T3 is electrically connected to the first signal terminal CN, the first pole of the third transistor T3 is electrically connected to the first clock signal terminal CK1, and the second pole of the third transistor T3 pole is electrically connected to the pull-down control node PDCN;
  • the control pole of the fourth transistor T4 is electrically connected to the second signal terminal CNB, the first pole of the fourth transistor T4 is electrically connected to the second clock
  • the pull-down node PD is electrically connected; the control pole of the sixth transistor T6 is electrically connected to the pull-up control node PUCN, the first pole of the sixth transistor T6 is electrically connected to the pull-down node PD, and the second pole of the sixth transistor T6 is connected to the second power terminal VGL is electrically connected; the first electrode of the first capacitor is electrically connected to the pull-down node PD, the second electrode of the first capacitor is electrically connected to the second power supply terminal VGL; the control electrode of the seventh transistor T7 is electrically connected to the first power supply terminal VGH, The first pole of the seventh transistor T7 is electrically connected to the pull-up control node PUCN, the second pole of the seventh transistor T7 is electrically connected to the first pull-up node PU1; the control pole of the eighth transistor T8 is electrically connected to the first pull-up node PU1 connection, the first pole of the eighth transistor T8 is electrically connected to the third clock signal terminal CK3, the second pole of the eighth transistor T
  • the two power supply terminals VGL are electrically connected; the control pole of the twelfth transistor T12 is electrically connected to the pull-down node PD, the first pole of the twelfth transistor T12 is electrically connected to the first output terminal OUTPUT1, and the second pole of the twelfth transistor T12 is electrically connected to the first output terminal OUTPUT1.
  • the second power supply terminal VGL is electrically connected; the control pole of the thirteenth transistor T13 is electrically connected to the pull-down node PD, the first pole of the thirteenth transistor T13 is electrically connected to the second output terminal OUTPUT2, and the second pole of the thirteenth transistor T13 It is electrically connected to the second power supply terminal VGL; the control pole of the fourteenth transistor T14 is electrically connected to the reset signal terminal RESET, the first pole of the fourteenth transistor T14 is electrically connected to the pull-up control node PUCN, and the fourth pole of the fourteenth transistor T14
  • the diodes are electrically connected to the second power supply terminal VGL.
  • the first transistor T1 to the fourteenth transistor T14 may be P-type transistors, or may be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display device, and improve the yield rate of the product. In some possible implementation manners, the first transistor T1 to the fourteenth transistor T14 may include P-type transistors and N-type transistors.
  • FIG. 9 is the working sequence diagram 1 of the shift register provided by an exemplary embodiment
  • FIG. 10 is the shift register provided by an exemplary embodiment. Timing diagram 2 of the bit register.
  • the shift register provided by an exemplary embodiment includes 14 transistor units (T1 to T14), 3 capacitors (C1, C2 and C3), and 9 signal input terminals (INPUT1, INPUT2, CN, CNB, RESET, CK1, CK2, CK3 and CK4), 2 signal output terminals (OUTPUT1 and OUTPUT2) and 2 power supply terminals (VGH and VGL).
  • FIG. 9 illustrates the working process of the shift register as an example when the gate drive circuit scans forward.
  • FIG. 10 illustrates the working process of the shift register as an example when the gate drive circuit scans in reverse.
  • the first power supply terminal VGH continuously provides a high-level signal
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on
  • the second power supply terminal VGL continuously provides a low-level signal.
  • the pull-up control node PUCN When the gate drive circuit is in the forward scanning mode, the time when the input signal of the second signal terminal CNB of the shift register of this stage is an active level signal and the time when the input signal of the second clock signal terminal CK2 is an active level signal No coincidence, at this time, the pull-up control node PUCN will not be pulled high by the high-level signal of the second clock signal terminal CK2, and will not affect the output of the shift register of the current stage.
  • the working process of the shift register may include:
  • the first stage t1 that is, the reset stage, the input signals of the reset signal terminal RESET, the first signal terminal CN and the first clock signal terminal CK1 in the signal input terminal are high level signals, the first input terminal INPUT1, the third clock signal The input signals of the terminal CK3 and the fourth clock signal terminal CK4 are low level signals.
  • the input signal of the reset signal terminal RESET is a high-level signal
  • the fourteenth transistor T14 is turned on, and the low-level signal of the second power supply terminal VGL is written into the pull-up control node PUCN to reset the pull-up control node PUCN.
  • the six-transistor T6 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the pull-down node PD, the input signal of the first signal terminal CN is a high-level signal, and the high-level signal of the first clock signal terminal CK1 is written into the pull-down node.
  • the input signals of the first input terminal INPUT1 and the first signal terminal CN in the signal input terminals are high-level signals
  • the first clock signal terminal CK1 the third clock signal terminal CK3, the fourth
  • the input signals of the clock signal terminal CK4 and the reset signal terminal RESET are low-level signals.
  • the input signal of the first input terminal INPUT1 is a high-level signal
  • the first transistor T1 is turned on
  • the high-level signal of the first signal terminal CN is written into the pull-up control node PUCN
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the high-level signal of the pull-up control node PUCN is written into the first pull-up node PU1 and the second pull-up node PU2, while charging the second capacitor C1 and the third capacitor C3, the eighth transistor T8 and the tenth transistor T10 is turned on, the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1, and the low-level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the first signal terminal CN is a high-level signal
  • the third transistor T3 is turned on
  • the low-level signal of the first clock signal terminal CK1 is written into the pull-down control node PDCN
  • the fifth transistor T5 is turned off
  • the first power supply The high-level signal of the terminal VGH cannot be written into the pull-down node PD
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on, and the potential of the pull-down node PD is controlled by the low-level signal of the second power supply terminal VLG Pulling low
  • the eleventh transistor T11 , the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and at this stage, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 output low-level signals.
  • the input signals of the first input terminal INPUT1, the first signal terminal CN, the first clock signal terminal CK1, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the reset signal terminal RESET among the signal input terminals is a low-level signal.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the first transistor T1 is turned off
  • the pull-up control node PUCN maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on
  • the pull-up The high level signal of the control node PUCN is written into the first pull-up node PU1 and the second pull-up node PU2, while charging the second capacitor C2 and the third capacitor C3, the eighth transistor T8 and the tenth transistor T10 are turned on
  • the second The low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the low-level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the first signal terminal CN is a low-level signal
  • the third transistor T3 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the eighth transistor T8 and the sixth transistor T6 are turned on
  • the pull-down node PD The potential is pulled down by the low-level signal of the second power supply terminal VLG, and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the first output terminal OUTPUT1 and The second output terminal OUTPUT2 still outputs a low level signal.
  • the input signal of the third clock signal terminal CK3 in the signal input terminal is a high-level signal
  • the input signals of the fourth clock signal terminal CK4 and the reset signal terminal RESET are low level signals.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the first transistor T1 is turned off
  • the pull-up control node PUCN maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the third clock signal terminal CK3 is a high-level signal
  • the first pull-up node PU1 rises under the action of the signal level bootstrap of the second capacitor C2
  • the input signal of the fourth clock signal terminal CK4 is a low-level signal level signal
  • the second pull-up node PU2 maintains the high-level signal of the previous stage
  • the eighth transistor T8 and the tenth transistor T10 are turned on
  • the high-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the low level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the first signal terminal CN is a low-level signal
  • the third transistor T3 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled down and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of the first output terminal OUTPUT1 is A high-level signal
  • the output signal of the second output terminal OUTPUT2 is a low-level signal.
  • the input signal of the fourth clock signal terminal CK4 in the signal input terminal is a high-level signal
  • the input signals of the third clock signal terminal CK3 and the reset signal terminal RESET are low level signals.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the first transistor T1 is turned off
  • the pull-up control node PUCN still maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the third clock signal terminal CK3 is a low-level signal
  • the first pull-up node PU1 restores to the high-level signal of the first stage
  • the input signal of the fourth clock signal terminal CK4 is a high-level signal
  • the second pull-up node PU1 The level of the signal at the pulling node PU2 rises under the action of the bootstrap of the third capacitor C3, the eighth transistor T8 and the tenth transistor T10 are turned on, and the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1, the high level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the first signal terminal CN is a low-level signal
  • the third transistor T3 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled down and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of the first output terminal OUTPUT1 is low level signal
  • the output signal of the second output terminal OUTPUT2 is a high level signal.
  • the input signals of the first input terminal INPUT1, the first signal terminal CN, the first clock signal terminal CK1, the third clock signal terminal CK3, and the fourth clock signal terminal CK4 among the signal input terminals and the reset signal terminal RESET is a low-level signal.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the first transistor T1 is turned off
  • the pull-up control node PUCN still maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the third clock signal terminal CK3 is a low-level signal
  • the first pull-up node PU1 restores to the high-level signal of the first stage
  • the input signal of the fourth clock signal terminal CK4 is a low-level signal
  • the second pull-up node PU1 restores to the high-level signal of the first stage.
  • the pull node PU2 returns to the high-level signal of the first stage
  • the eighth transistor T8 and the tenth transistor T10 are turned on
  • the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the fourth clock signal terminal The low level signal of CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the first signal terminal CN is a low-level signal
  • the third transistor T3 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled low and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of terminal OUTPUT2 is a low level signal.
  • the input signals of the first signal terminal CN and the first clock signal terminal CK1 in the signal input terminals are high-level signals, and the first input terminal INPUT1, the third clock signal terminal CK3, the The input signals of the four clock signal terminal CK4 and the reset signal terminal RESET are low level signals.
  • the input signal of the first signal terminal CN is a high-level signal
  • the third transistor T3 is turned on
  • the high-level signal of the first clock signal terminal CK1 is written into the pull-down control node PDCN
  • the fifth transistor T5 is turned on
  • the first power supply terminal The high-level signal of VGH is written into the pull-down node PD
  • the eleventh transistor T11 is turned on
  • the low-level signal of the second power supply terminal VGL is written into the pull-up control node PDCN.
  • the sixth transistor T6 is turned off, and the second power supply
  • the low-level signal at the terminal VGL cannot be written into the pull-down node PD
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on, the potentials of the first pull-up node PU1 and the second pull-up node PU2 are pulled down
  • the eighth transistor T8 and the tenth transistor T10 is turned off
  • the twelfth transistor T12 is turned on
  • the signal of the first output terminal OUTPUT1 is pulled down by the low level signal of the second power supply terminal VGL
  • the thirteenth transistor T13 is turned on
  • the signal of the second output terminal OUTPUT2 The signal is pulled low by the low level signal of the second power supply terminal VGL.
  • the output signals of the first output terminal OUTPUT1 and the second output terminal OUTPUT2 are low-level signals.
  • the input signals of the first signal terminal CN, the first clock signal terminal CK1, the first input terminal INPUT1, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the reset signal terminal RESET among the signal input terminals is a low-level signal.
  • the input signal of the first signal terminal CN is a low-level signal
  • the third transistor T3 is turned off
  • the first capacitor C1 starts to discharge
  • the pull-down control node PDCN maintains the high-level signal of the previous stage
  • the fifth transistor T5 is turned on
  • the first The high-level signal of the power supply terminal VGH is written into the pull-down node PD
  • the eleventh transistor T11 is turned on
  • the low-level signal of the second power supply terminal VGL is written into the pull-up control node PDCN
  • the sixth transistor T6 is turned off
  • the low-level signal of VGL cannot be written into the pull-down node PD
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on
  • the potentials of the first pull-up node PU1 and the second pull-up node PU2 are pulled down
  • the eighth transistor T8 and the The tenth transistor T110 is turned off
  • the twelfth transistor T12 is turned on
  • the pull-up control node PUCN When the gate drive circuit is in the reverse scanning mode, the time when the input signal of the first signal terminal CN of the shift register of this stage is an active level signal and the time when the input signal of the first clock signal terminal CK1 is an active level signal No coincidence, at this time, the pull-up control node PUCN will not be pulled high by the high-level signal of the first clock signal terminal CK1, and will not affect the output of the shift register of the current stage.
  • the working process of the shift register can include:
  • the first stage t1 that is, the reset stage, the input signals of the reset signal terminal RESET, the second signal terminal CNB and the second clock signal terminal CK2 in the signal input terminal are high level signals, the first input terminal INPUT1, the third clock signal The input signals of the terminal CK3 and the fourth clock signal terminal CK4 are low level signals.
  • the input signal of the reset signal terminal RESET is a high-level signal
  • the fourteenth transistor T14 is turned on, and the low-level signal of the second power supply terminal VGL is written into the pull-up control node PUCN to reset the pull-up control node PUCN.
  • the six transistor T6 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the pull-down node PD, the input signal of the second signal terminal CNB is a high-level signal, and the high-level signal of the second clock signal terminal CK2 is written into the pull-down node
  • the control node PDCN the tenth transistor T10 is turned on, the high level signal of the first power supply terminal VGH is written into the pull-down node PD, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are turned on, so as to control the upper Pull the control node, the first output terminal and the second output terminal to reset.
  • the input signals of the first input terminal INPUT1 and the second signal terminal CNB in the signal input terminals are high-level signals
  • the second clock signal terminal CK2 the third clock signal terminal CK3, the fourth
  • the input signals of the clock signal terminal CK4 and the reset signal terminal RESET are low-level signals.
  • the input signal of the first input terminal INPUT1 is a high-level signal
  • the second transistor T2 is turned on
  • the high-level signal of the second signal terminal CNB is written into the pull-up control node PUCN
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the high-level signal of the pull-up control node PUCN is written into the first pull-up node PU1 and the second pull-up node PU2, while charging the second capacitor C1 and the third capacitor C3, the eighth transistor T8 and the tenth transistor T10 is turned on, the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1, and the low-level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the second signal terminal CNB is a high-level signal
  • the fourth transistor T4 is turned on
  • the low-level signal of the second clock signal terminal CK2 is written into the pull-down control node PDCN
  • the fifth transistor T5 is turned off
  • the first power supply The high-level signal of the terminal VGH cannot be written into the pull-down node PD
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on, and the potential of the pull-down node PD is controlled by the low-level signal of the second power supply terminal VLG Pulling low
  • the eleventh transistor T11 , the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and at this stage, the first output terminal OUTPUT1 and the second output terminal OUTPUT2 output low-level signals.
  • the input signals of the first input terminal INPUT1, the second signal terminal CNB, the second clock signal terminal CK2, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the reset signal terminal RESET among the signal input terminals is a low-level signal.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the second transistor T2 is turned off
  • the pull-up control node PUCN maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on
  • the pull-up The high level signal of the control node PUCN is written into the first pull-up node PU1 and the second pull-up node PU2, while charging the second capacitor C2 and the third capacitor C3, the eighth transistor T8 and the tenth transistor T10 are turned on
  • the second The low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the low-level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the second signal terminal CNB is a low-level signal
  • the fourth transistor T4 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the eighth transistor T8 and the sixth transistor T6 are turned on
  • the pull-down node PD The potential is pulled down by the low-level signal of the second power supply terminal VLG, and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the first output terminal OUTPUT1 and The second output terminal OUTPUT2 still outputs a low level signal.
  • the input signal of the fourth clock signal terminal CK4 in the signal input terminal is a high level signal
  • the input signals of the third clock signal terminal CK3 and the reset signal terminal RESET are low level signals.
  • the input signal of the first input terminal INPUT1 is a low-level signal
  • the second transistor T2 is turned off
  • the pull-up control node PUCN maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the fourth clock signal terminal CK4 is a high-level signal
  • the second pull-up node PU2 rises under the action of the signal level bootstrap of the third capacitor C3
  • the input signal of the third clock signal terminal CK3 is a low-level signal level signal
  • the first pull-up node PU1 maintains the high-level signal of the previous stage
  • the eighth transistor T8 and the tenth transistor T10 are turned on
  • the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the draft level signal of the fourth clock signal terminal CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the second signal terminal CNB is a low-level signal
  • the fourth transistor T4 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled down and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of the first output terminal OUTPUT1 is low level signal
  • the output signal of the second output terminal OUTPUT2 is a high level signal.
  • the input signal of the third clock signal terminal CK3 in the signal input terminal is a high-level signal
  • the input signals of the fourth clock signal terminal CK4 and the reset signal terminal RESET are low level signals.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the second transistor T2 is turned off
  • the pull-up control node PUCN still maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the third clock signal terminal CK3 is a high-level signal
  • the level of the signal of the first pull-up node PU1 rises under the action of the bootstrap of the second capacitor C2
  • the input signal of the fourth clock signal terminal CK4 is low Level signal
  • the signal of the second pull-up node PU2 returns to the high level signal of the first stage
  • the eighth transistor T8 and the tenth transistor T10 are turned on, and the high level signal of the third clock signal terminal CK3 is written into the first
  • the output terminal OUTPUT1 and the low level signal of the fourth clock signal terminal CK4 are written into the second output terminal OUTPUT2.
  • the input signal of the second signal terminal CNB is a low-level signal
  • the fourth transistor T4 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled down and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of the first output terminal OUTPUT1 is A high-level signal
  • the output signal of the second output terminal OUTPUT2 is a low-level signal.
  • the input signals of the first input terminal INPUT1, the second signal terminal CNB, the second clock signal terminal CK2, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the reset signal terminal RESET among the signal input terminals is a low-level signal.
  • the input signal at the first input terminal INPUT1 is a low-level signal
  • the second transistor T2 is turned off
  • the pull-up control node PUCN still maintains the high-level signal of the previous stage
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on.
  • the input signal of the third clock signal terminal CK3 is a low-level signal
  • the first pull-up node PU1 restores to the high-level signal of the first stage
  • the input signal of the fourth clock signal terminal CK4 is a low-level signal
  • the second pull-up node PU1 restores to the high-level signal of the first stage.
  • the pull node PU2 returns to the high-level signal of the first stage
  • the eighth transistor T8 and the tenth transistor T10 are turned on
  • the low-level signal of the third clock signal terminal CK3 is written into the first output terminal OUTPUT1
  • the fourth clock signal terminal The low level signal of CK4 is written into the second output terminal OUTPUT2.
  • the input signal of the second signal terminal CNB is a low-level signal
  • the fourth transistor T4 is turned off
  • the signal of the pull-up control node PUCN is a high-level signal
  • the sixth transistor T6 is turned on
  • the potential of the pull-down node PD is controlled by the second
  • the low-level signal of the power supply terminal VLG continues to be pulled low and remains low, and the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are cut off.
  • the output signal of terminal OUTPUT2 is a low level signal.
  • the input signals of the second signal terminal CNB and the second clock signal terminal CK2 in the signal input terminal are high-level signals, and the first input terminal INPUT1, the third clock signal terminal CK3, the second The input signals of the four clock signal terminal CK4 and the reset signal terminal RESET are low level signals.
  • the input signal of the second signal terminal CNB is a high-level signal
  • the fourth transistor T4 is turned on
  • the high-level signal of the second clock signal terminal CK2 is written into the pull-down control node PDCN
  • the fifth transistor T5 is turned on
  • the first power supply terminal The high-level signal of VGH is written into the pull-down node PD
  • the eleventh transistor T11 is turned on
  • the low-level signal of the second power supply terminal VGL is written into the pull-up control node PDCN.
  • the sixth transistor T6 is turned off, and the second power supply
  • the low-level signal at the terminal VGL cannot be written into the pull-down node PD
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on, the potentials of the first pull-up node PU1 and the second pull-up node PU2 are pulled down
  • the eighth transistor T8 and the tenth transistor T10 is turned off
  • the twelfth transistor T12 is turned on
  • the signal of the first output terminal OUTPUT1 is pulled down by the low level signal of the second power supply terminal VGL
  • the thirteenth transistor T13 is turned on
  • the signal of the second output terminal OUTPUT2 The signal is pulled low by the low level signal of the second power supply terminal VGL.
  • the output signals of the first output terminal OUTPUT1 and the second output terminal OUTPUT2 are low-level signals.
  • the input signals of the second signal terminal CNB, the second clock signal terminal CK2, the first input terminal INPUT1, the third clock signal terminal CK3, the fourth clock signal terminal CK4 and the reset signal terminal RESET among the signal input terminals is a low-level signal.
  • the input signal of the second signal terminal CNB is a low-level signal
  • the fourth transistor T4 is turned off
  • the first capacitor C1 starts to discharge
  • the pull-down control node PDCN maintains the high-level signal of the previous stage
  • the fifth transistor T5 is turned on
  • the first The high-level signal of the power supply terminal VGH is written into the pull-down node PD
  • the eleventh transistor T11 is turned on
  • the low-level signal of the second power supply terminal VGL is written into the pull-up control node PDCN
  • the sixth transistor T6 is turned off
  • the low-level signal of VGL cannot be written into the pull-down node PD
  • the seventh transistor T7 and the ninth transistor T9 are continuously turned on
  • the potentials of the first pull-up node PU1 and the second pull-up node PU2 are pulled down
  • the eighth transistor T8 and the The tenth transistor T110 is turned off
  • the twelfth transistor T12 is turned on
  • the shift register provided by the present disclosure includes 14 transistors and 3 capacitors and can output two gate drive signals through the first output terminal and the second output terminal, which reduces the number of transistors and capacitors in the gate drive circuit and saves
  • the wiring space reduces the area occupied by the gate drive circuit, which can realize a narrow frame of the display device and reduce power consumption.
  • the sixth transistor when the signal of the pull-up control node is a high-level signal, the sixth transistor is turned on, and the potential of the pull-down node PD is pulled down, which can avoid the existence of a current path in the shift register and avoid static power consumption generated by the circuit path .
  • the power consumption of the shift register provided by the embodiment of the present disclosure is 20% lower than that of the shift register which only outputs one gate driving signal.
  • FIG. 11 is a flowchart of a driving method of a shift register provided by an embodiment of the present disclosure. As shown in FIG. 11, the driving method of the shift register provided by the embodiment of the present disclosure is set to drive the shift register, and the driving method of the shift register provided by the embodiment of the present disclosure may include:
  • Step S1 under the control of the first input terminal and the second output terminal, the pull-up control subcircuit provides the signal of the first signal terminal or the second signal terminal to the pull-up control node.
  • Step S2 under the control of the pull-up control node, the first signal terminal, the second signal terminal, the first clock signal terminal and the second clock signal terminal, the pull-down control subcircuit provides the pull-down node with the power of the first power supply terminal or the second power supply terminal Signal.
  • Step S3 under the control of the pull-up control node and the first power supply terminal, the output subcircuit provides the signal of the third clock signal terminal to the first output terminal, and provides the signal of the fourth clock signal terminal to the second output terminal.
  • Step S4 under the control of the pull-down node, the noise reduction sub-circuit provides the signal of the second power supply terminal to the pull-up control node, the first output terminal and the second output terminal.
  • the shift register is the shift register provided by any one of the foregoing embodiments, and its implementation principle and implementation effect are similar, so details are not repeated here.
  • the driving method of the shift register may further include: under the control of the reset signal terminal, the reset subcircuit provides the signal of the second power supply terminal to the pull-up control node.
  • FIG. 12 is a schematic structural diagram of a gate driving circuit provided by an embodiment of the present disclosure.
  • the gate driving circuit of the embodiment of the present disclosure includes a plurality of cascaded shift registers.
  • the first input terminal INPUT1 of the shift register of the i+1st stage is electrically connected to the first output terminal OUTPUT1 of the shift register of the i+1st stage
  • the second input terminal INPUT2 of the shift register of the i+1st stage is connected to the first output terminal OUTPUT1 of the i+1st stage shift register.
  • the second output terminal OUTPUT2 of the 2-stage shift register is electrically connected.
  • the shift register is the shift register provided by any one of the foregoing embodiments, and its implementation principle and implementation effect are similar, so details are not repeated here.
  • the gate drive circuit may further include: an initial signal line STV, a first clock line CLK1, a second clock line CLK2, a third clock line CLK3, a fourth clock line CLK4, fifth clock line CLK5, sixth clock line CLK6, reset signal line RST, first power line Vgh, second power line Vgl, first signal line CNL, and second signal line CNBL.
  • the reset signal terminals RESET of all the shift registers are connected to the reset signal line RST
  • the first power supply terminals VGH of all the shift registers are connected to the first power supply line Vgh
  • the second power supply terminals of all the shift registers are connected to the first power supply line Vgh.
  • the power terminal VGL is connected to the second power line Vgl
  • the first signal terminals CN of all the shift registers are connected to the first signal line CNL
  • the second signal terminals CNB of all the shift registers are connected to the second signal line CNBL.
  • the first input terminal INPUT1 of the first-stage shift register GOA(1) is connected to the initial signal line STV.
  • the first clock signal terminal CK1 of the 3i-2 stage shift register GOA (3i-2) is connected to the sixth clock line CLK6, and the 3i-2 stage shift register GOA (3i- 2)
  • the second clock signal terminal CK2 is connected to the first clock line CLK1
  • the third clock signal terminal CK3 of the 3i-2 stage shift register GOA (3i-2) is connected to the third clock line CLK3, the 3i-2
  • the fourth clock signal terminal CK4 of the stage shift register GOA (3i-2) is connected to the fourth clock line CLK4
  • the first clock signal terminal CK1 of the 3i-1 stage shift register GOA (3i-1) is connected to the second clock signal terminal CK4.
  • the line CLK2 is connected, the second clock signal terminal CK2 of the 3i-1 stage shift register GOA (3i-1) is connected with the third clock line CLK3, and the third clock signal terminal CK2 of the 3i-1 stage shift register GOA (3i-1)
  • the clock signal terminal CK3 is connected with the fifth clock line CLK5, the fourth clock signal terminal CK4 of the 3i-1 stage shift register GOA (3i-1) is connected with the sixth clock line CLK6, and the 3i stage shift register GOA (3i ) is connected to the fourth clock line CLK4, the second clock signal end CK2 of the 3i-stage shift register GOA (3i) is connected to the fifth clock line CLK5, and the 3i-stage shift register GOA
  • the third clock signal terminal CK3 of (3i) is connected to the first clock line CLK1, and the fourth clock signal terminal CK4 of the 3i-stage shift register device GOA (3i) is connected to the second clock line CLK2.
  • the first clock signal terminal CK1 of the first-stage shift register GOA(1) is connected to the sixth clock line CLK6, and the second clock signal terminal CK2 of the first-stage shift register GOA(1) is connected to the first clock line CLK6.
  • Line CLK1 is connected
  • the third clock signal terminal CK3 of the first-stage shift register GOA (1) is connected to the third clock line CLK3
  • the fourth clock signal terminal CK4 of the first-stage shift register GOA (1) is connected to the fourth clock signal terminal CK3.
  • Line CLK4 is connected
  • the first clock signal terminal CK1 of the second-stage shift register GOA (2) is connected to the second clock line CLK2
  • the second clock signal terminal CK2 of the second-stage shift register GOA (2) is connected to the third clock signal terminal CK2.
  • Line CLK3 is connected, the third clock signal terminal CK3 of the second-stage shift register GOA (2) is connected to the fifth clock line CLK5, and the fourth clock signal terminal CK4 of the second-stage shift register GOA (2) is connected to the sixth clock signal terminal CK4.
  • Line CLK6 is connected, the first clock signal terminal CK1 of the third-stage shift register GOA (3) is connected to the fourth clock line CLK4, and the second clock signal terminal CK2 of the third-stage shift register GOA (3) is connected to the fifth clock signal terminal CK2.
  • Line CLK5 is connected, the third clock signal terminal CK3 of the third-stage shift register GOA (3) is connected to the first clock line CLK1, and the fourth clock signal terminal CK4 of the third-stage shift register GOA (3) is connected to the second clock signal terminal CK4.
  • Line CLK2 connects
  • the first input terminal INPUT1 of the shift register GOA(i+1) of the i+1 stage is electrically connected to the second output terminal OUTPUT2 of the shift register GOA(i) of the i stage
  • the The second input terminal INPUT2 of the i+1-th stage shift register GOA(i+1) is electrically connected to the first output terminal OUTPUT1 of the i+2-th stage shift register GOA(i+2).
  • the first input terminal INPUT1 of the first-stage shift register GOA (1) is connected to the initial signal terminal STV
  • the first input terminal INPUT1 of the second-stage shift register GOA (2) is connected to the first-stage shift register GOA ( 1) is electrically connected to the second output terminal OUTPUT2
  • the second input terminal INPUT2 of the second-stage shift register GOA (2) is electrically connected to the first output terminal OUTPUT1 of the third-stage shift register GOA (3), and so on.
  • FIG. 13 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a display device, including: a gate drive circuit 10 and a plurality of scanning signal lines (not shown in the figure); the scanning signal lines extend along a first direction, The multiple scanning signal lines are arranged along the second direction, and the first direction intersects with the second direction.
  • the gate driving circuit is electrically connected to a plurality of scanning signal lines.
  • the display device may be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the gate driving circuit is the gate driving circuit provided by any one of the above-mentioned embodiments, and the realization principle and the realization effect are similar, and will not be repeated here.
  • the length L1 of the gate driving circuit 10 along the first direction is about 0.35 mm to 0.37 mm.
  • the length L1 of the gate drive circuit 10 along the first direction may be 0.36 millimeters
  • the shift register at the jth stage in the gate driving circuit is connected to the 2j-1th scanning signal line and the 2jth scanning signal line, 1 ⁇ j ⁇ N, where N is the gate driving The number of shift registers included in the circuit.
  • a display device includes: a display area and a non-display area.
  • the gate driving circuit 10 is disposed in the non-display area.
  • the length of the non-display area along the first direction may be 0.6 mm to 0.8 mm.
  • the length of the non-display area along the first direction may be 0.7 mm.
  • the non-display area further includes: a ground signal line 20 located on the side of the gate drive circuit close to the display area, and the length L2 of the ground signal line 20 along the first direction can be 0.01 mm to 0.03 mm.
  • the length L2 of the ground signal line 20 along the first direction may be 0.02 mm.
  • the distance L4 between the side of the ground signal line away from the display area and the edge of the non-display area may be 0.15 mm to 0.25 mm.
  • the distance L4 between the side of the ground signal line away from the display area and the edge of the non-display area may be 0.2 millimeters.
  • the distance L5 between the side of the ground signal line close to the display area and the side of the gate driving circuit away from the display area may be 0.01 mm to 0.03 mm.
  • the distance L5 between the side of the ground signal line close to the display area and the side of the gate driving circuit away from the display area may be 0.02 millimeters.
  • the non-display area may further include: a dummy pixel area 30 .
  • the length L3 of the dummy pixel area 30 along the first direction may be 0.02 mm to 0.04 mm.
  • the length L3 of the dummy pixel region 30 along the first direction may be 0.03 mm.
  • the distance L6 between the side of the gate driving circuit 20 close to the display area and the dummy pixel area may be 0.01 mm to 0.03 mm.
  • the distance L6 between the side of the gate driving circuit 20 close to the display area and the dummy pixel area may be 0.02 mm.

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Abstract

一种移位寄存器及其驱动方法、栅极驱动电路、显示装置，其中，移位寄存器包括：上拉控制子电路，设置为在第一输入端（INPUT1）和第二输入端（INPUT2）的控制下，向上拉控制节点（PUCN）提供第一信号端（CN）或第二信号端（CNB）的信号；下拉控制子电路，设置为在上拉控制节点（PUCN）、第一信号端（CN）、第二信号端（CNB）、第一时钟信号端（CK1）和第二时钟信号端（CK2）的控制下，向下拉节点（PD）提供第一电源端（VGH）或第二电源端（VGL）的信号；输出子电路，设置为在上拉控制节点（PUCN）和第一电源端（VGH）的控制下，向第一输出端（OUTPUT1）提供第三时钟信号端（CK3）的信号，向第二输出端（OUTPUT2）提供第四时钟信号端（CK4）的信号；降噪子电路，设置为在下拉节点（PD）的控制下，向上拉控制节点（PUCN）、第一输出端（OUTPUT1）和第二输出端（OUTPUT2）提供第二电源端（VGL）的信号。

Description

移位寄存器及其驱动方法、栅极驱动电路、显示装置 技术领域
本公开涉及但不限于显示技术领域，具体涉及一种移位寄存器及其驱动方法、栅极驱动电路、显示装置。
背景技术
近年来，平板显示器，如薄膜晶体管液晶显示面板(Thin Film Transistor-Liquid Crystal Display，TFT-LCD)和有源矩阵有机发光二极管显示面板(Active Matrix Organic Light Emitting Diode，AMOLED)，由于具有重量轻，厚度薄以及低功耗等优点，因而被广泛应用于电视、手机等电子产品中。
随着科技的进步，高分辨率、窄边框的显示面板成为发展的趋势，为此出现了阵列基板栅极驱动(Gate Driver on Array，GOA)技术，GOA技术是指将用于驱动栅线的GOA电路设置在显示面板中阵列基板的有效显示区域两侧的技术。
发明概述
以下是对本公开详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
第一方面，本公开提供了一种移位寄存器，包括：上拉控制子电路、下拉控制子电路、输出子电路和降噪子电路；
所述上拉控制子电路，分别与第一输入端、第二输出端、第一信号端、第二信号端和上拉控制节点电连接，设置为在第一输入端和第二输出端的控制下，向上拉控制节点提供第一信号端或第二信号端的信号；
所述下拉控制子电路，分别与第一时钟信号端、第二时钟信号端、第一信号端、第二信号端、上拉控制节点、下拉节点、第一电源端和第二电源端电连接，设置为在上拉控制节点、第一信号端、第二信号端、第一时钟信号 端和第二时钟信号端的控制下，向下拉节点提供第一电源端或第二电源端的信号；
所述输出子电路，分别与上拉控制节点、第一电源端、第三时钟信号端、第一输出端、第四时钟信号端和第二输出端电连接，设置为在上拉控制节点和第一电源端的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号；
所述降噪子电路，分别与上拉控制节点、第一输出端、第二输出端、下拉节点和第二电源端电连接，设置为在下拉节点的控制下，向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。
在一些可能的实现方式中，所述输出子电路包括：第一输出子电路和第二输出子电路；
所述第一输出子电路，分别与上拉控制节点、第一电源端、第三时钟信号端和第一输出端电连接，设置在为第一电源端和上拉控制节点的控制下，向第一输出端提供第三时钟信号端的信号；
所述第二输出子电路，分别与上拉控制节点、第一电源端、第四时钟信号端和第二输出端电连接，设置为在第一电源端和上拉控制节点的控制下，向第二输出端提供第四时钟信号端的信号。
在一些可能的实现方式中，还包括：复位子电路；
所述复位子电路，分别与复位信号端、上拉控制节点和第二电源端电连接，设置为在复位信号端的控制下，向上拉控制节点提供第二电源端的信号。
在一些可能的实现方式中，所述上拉控制子电路包括：第一晶体管和第二晶体管；
所述第一晶体管的控制极与第一输入端电连接，所述第一晶体管的第一极与第一信号端电连接，所述第一晶体管的第二极与上拉控制节点电连接；
所述第二晶体管的控制极与第二输入端电连接，所述第二晶体管的第一极与第二信号端电连接，所述第二晶体管的第二极与上拉控制节点电连接。
在一些可能的实现方式中，所述下拉控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；
所述第三晶体管的控制极与第一信号端电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与下拉控制节点电连接；
所述第四晶体管的控制极与第二信号端电连接，所述第四晶体管的第一极与第二时钟信号端电连接，所述第四晶体管的第二极与下拉控制节点电连接；
所述第五晶体管的控制极与下拉控制节点电连接，所述第五晶体管的第一极与第一电源端电连接，所述第五晶体管的第二极与下拉节点电连接；
所述第六晶体管的控制极与上拉控制节点电连接，所述第六晶体管的第一极与下拉节点电连接，所述第六晶体管的第二极与第二电源端电连接；
所述第一电容的第一极与下拉节点电连接，所述第一电容的第二极与第二电源端电连接。
在一些可能的实现方式中，所述第一输出子电路包括：第七晶体管、第八晶体管和第二电容；
所述第七晶体管的控制极与第一电源端电连接，所述第七晶体管的第一极与上拉控制节点电连接，所述第七晶体管的第二极与第一上拉节点电连接；
所述第八晶体管的控制极与第一上拉节点电连接，所述第八晶体管的第一极与第三时钟信号端电连接，所述第八晶体管的第二极与第一输出端电连接；
所述第二电容的第一极与第一上拉节点电连接，所述第二电容的第二极与第一输出端电连接。
在一些可能的实现方式中，所述第二输出子电路包括：第九晶体管、第十晶体管和第三电容；
所述第九晶体管的控制极与第一电源端电连接，所述第九晶体管的第一极与上拉控制节点电连接，所述第九晶体管的第二极与第二上拉节点电连接；
所述第十晶体管的控制极与第二上拉节点电连接，所述第十晶体管的第一极与第四时钟信号端电连接，所述第十晶体管的第二极与第二输出端电连接；
所述第三电容的第一极与第二上拉节点电连接，所述第三电容的第二极与第二输出端电连接。
在一些可能的实现方式中，所述降噪子电路包括：第十一晶体管、第十二晶体管和第十三晶体管；
所述第十一晶体管的控制极与下拉节点电连接，所述第十一晶体管的第一极与上拉控制节点电连接，所述第十一晶体管的第二极与第二电源端电连接；
所述第十二晶体管的控制极与下拉节点电连接，所述第十二晶体管的第一极与第一输出端电连接，所述第十二晶体管的第二极与第二电源端电连接；
所述第十三晶体管的控制极与下拉节点电连接，所述第十三晶体管的第一极与第二输出端电连接，所述第十三晶体管的第二极与第二电源端电连接。
在一些可能的实现方式中，所述复位子电路包括：第十四晶体管；
所述第十四晶体管的控制极与复位信号端电连接，所述第十四晶体管的第一极与上拉控制节点电连接，所述第十四晶体管的第二极与第二电源端电连接。
在一些可能的实现方式中，还包括复位子电路，所述上拉控制子电路包括：第一晶体管和第二晶体管；所述下拉控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；所述输出子电路包括：第七晶体管、第八晶体管、第二电容、第九晶体管、第十晶体管和第三电容；所述降噪子电路包括：第十一晶体管、第十二晶体管和第十三晶体管；所述复位子电路包括：第十四晶体管；
所述第一晶体管的控制极与第一输入端电连接，所述第一晶体管的第一极与第一信号端电连接，所述第一晶体管的第二极与上拉控制节点电连接；
所述第二晶体管的控制极与第二输入端电连接，所述第二晶体管的第一极与第二信号端电连接，所述第二晶体管的第二极与上拉控制节点电连接；
所述第三晶体管的控制极与第一信号端电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与下拉控制节点电连接；
所述第四晶体管的控制极与第二信号端电连接，所述第四晶体管的第一极与第二时钟信号端电连接，所述第四晶体管的第二极与下拉控制节点电连接；
所述第五晶体管的控制极与下拉控制节点电连接，所述第五晶体管的第一极与第一电源端电连接，所述第五晶体管的第二极与下拉节点电连接；
所述第六晶体管的控制极与上拉控制节点电连接，所述第六晶体管的第一极与下拉节点电连接，所述第六晶体管的第二极与第二电源端电连接；
所述第一电容的第一极与下拉节点电连接，所述第一电容的第二极与第二电源端电连接；
所述第七晶体管的控制极与第一电源端电连接，所述第七晶体管的第一极与上拉控制节点电连接，所述第七晶体管的第二极与第一上拉节点电连接；
所述第八晶体管的控制极与第一上拉节点电连接，所述第八晶体管的第一极与第三时钟信号端电连接，所述第八晶体管的第二极与第一输出端电连接；
所述第二电容的第一极与第一上拉节点电连接，所述第二电容的第二极与第一输出端电连接；
所述第九晶体管的控制极与第一电源端电连接，所述第九晶体管的第一极与上拉控制节点电连接，所述第九晶体管的第二极与第二上拉节点电连接；
所述第十晶体管的控制极与第二上拉节点电连接，所述第十晶体管的第一极与第四时钟信号端电连接，所述第十晶体管的第二极与第二输出端电连接；
所述第三电容的第一极与第二上拉节点电连接，所述第三电容的第二极与第二输出端电连接；
所述第十一晶体管的控制极与下拉节点电连接，所述第十一晶体管的第一极与上拉控制节点电连接，所述第十一晶体管的第二极与第二电源端电连接；
所述第十二晶体管的控制极与下拉节点电连接，所述第十二晶体管的第一极与第一输出端电连接，所述第十二晶体管的第二极与第二电源端电连接；
所述第十三晶体管的控制极与下拉节点电连接，所述第十三晶体管的第一极与第二输出端电连接，所述第十三晶体管的第二极与第二电源端电连接；
所述第十四晶体管的控制极与复位信号端电连接，所述第十四晶体管的第一极与上拉控制节点电连接，所述第十四晶体管的第二极与第二电源端电连接。
第二方面，本公开还提供了一种栅极驱动电路，包括多个级联的上述移位寄存器；
第i+1级移位寄存器的第一输入端与第i级移位寄存器的第一输出端电连接，第i+1级移位寄存器的第二输入端与第i+2级移位寄存器的第二输出端电连接。
在一些可能的实现方式中，还包括：初始信号线、第一时钟线、第二时钟线、第三时钟线、第四时钟线、第五时钟线、第六时钟线、复位信号线、第一电源线、第二电源线、第一信号线和第二信号线；
所有移位寄存器的复位信号端与复位信号线连接，所有移位寄存器的第一电源端与第一电源线连接，所有移位寄存器的第二电源端与第二电源线连接，所有移位寄存器的第一信号端与第一信号线连接，所有移位寄存器的第二信号端与第二信号线连接；
第一级移位寄存器的第一输入端与初始信号线连接，第3i-2级移位寄存器的第一时钟信号端与第六时钟线连接，第3i-2级移位寄存器的第二时钟信号端与第一时钟线连接，第3i-2级移位寄存器的第三时钟信号端与第三时钟线连接，第3i-2级移位寄存器的第四时钟信号端与第四时钟线连接，第3i-1级移位寄存器的第一时钟信号端与第二时钟线连接，第3i-1级移位寄存器的第二时钟信号端与第三时钟线连接，第3i-1级移位寄存器的第三时钟信号端与第五时钟线连接，第3i-1级移位寄存器的第四时钟信号端与第六时钟线连接，第3i级移位寄存器的第一时钟信号端与第四时钟线连接，第3i级移位寄存器的第二时钟信号端与第五时钟线连接，第3i级移位寄存器的第三时钟信号端与第一时钟线连接，第3i级移位寄存器的第四时钟信号端与第二时钟线连接。
第三方面，本公开还提供了一种显示装置，包括：上述栅极驱动电路和 多条扫描信号线；所述扫描信号线沿第一方向延伸，多条扫描信号线沿第二方向排布，所述第一方向和所述第二方向相交；
所述栅极驱动电路中的第j级移位寄存器与第2j-1条扫描信号线和第2j条扫描信号线连接，1≤j≤N，N为栅极驱动电路中包括的移位寄存器的数量。
在一些可能的实现方式中，所述栅极驱动电路沿第一方向的长度约为0.35毫米至0.37毫米。
第四方面，本公开还提供了一种移位寄存器的驱动方法，其中，设置为驱动上述移位寄存器，所述方法包括：
在第一输入端和第二输出端的控制下，上拉控制子电路向上拉控制节点提供第一信号端或第二信号端的信号；
在上拉控制节点、第一信号端、第二信号端、第一时钟信号端和第二时钟信号端的控制下，下拉控制子电路向下拉节点提供第一电源端或第二电源端的信号；
在上拉控制节点和第一电源端的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号；
在下拉节点的控制下，降噪子电路向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。
在一些可能的实现方式中，还包括：在复位信号端的控制下，复位子电路向上拉控制节点提供第二电源端的信号。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图概述
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为本公开实施例提供的移位寄存器的结构示意图；
图2为一种示例性实施例提供的移位寄存器的结构示意图；
图3为一种示例性实施例提供的上拉控制子电路的等效电路图；
图4为一种示例性实施例提供的下拉控制子电路的等效电路图；
图5为一种示例性实施例提供的输出子电路的等效电路图；
图6为一种示例性实施例提供的降噪子电路的等效电路图；
图7为一种示例性实施例提供的复位子电路的等效电路图；
图8为一种示例性实施例提供的移位寄存器的等效电路图；
图9为一种示例性实施例提供的移位寄存器的工作时序图一；
图10为一种示例性实施例提供的移位寄存器的工作时序图二；
图11为本公开实施例提供的移位寄存器的驱动方法的流程图；
图12为本公开实施例提供的栅极驱动电路的结构示意图；
图13为本公开实施例提供的显示装置的结构示意图。
详述
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。为了保持本公开实施例的以下说明清楚且简明，本公开省略了部分已知功能和已知部件的详细说明。本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计
在附图中，有时为了明确起见，夸大表示了各构成要素的大小、层的厚度或区域。因此，本公开的一个方式并不一定限定于该尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的 混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。注意，在本说明书中，沟道区域是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的 数值。
一种显示装置中的GOA电路包括多个移位寄存器。GOA电路包括的器件较多，且占用的面积较大，使得显示装置无法实现窄边框，且功耗较大。
图1为本公开实施例提供的移位寄存器的结构示意图。如图1所示，本公开实施例提供的移位寄存器可以包括：上拉控制子电路、下拉控制子电路、输出子电路和降噪子电路。其中，上拉控制子电路，分别与第一输入端INPUT1、第二输出端OUTPUT2、第一信号端CN、第二信号端CNB和上拉控制节点PUCN电连接，设置为在第一输入端INPUT1和第二输出端OUTPUT2的控制下，向上拉控制节点PUCN提供第一信号端CN或第二信号端CNB的信号。下拉控制子电路，分别与第一时钟信号端CK1、第二时钟信号端CK2、第一信号端CN、第二信号端CNB、上拉控制节点PUCN、下拉节点PD、第一电源端VGH和第二电源端VGL电连接，设置为在上拉控制节点PUCN、第一信号端CN、第二信号端CNB、第一时钟信号端CK1和第二时钟信号端CK2的控制下，向下拉节点PD提供第一电源端VGH或第二电源端VGL的信号。输出子电路，分别与上拉控制节点PUCN、第一电源端VGH、第三时钟信号端CK3、第一输出端OUTPUT1、第四时钟信号端CK4和第二输出端OUTPUT2电连接，设置为在上拉控制节点PUCN和第一电源端VGH的控制下，向第一输出端OUTPUT1提供第三时钟信号端CK3的信号，向第二输出端OUTPUT2提供第四时钟信号端CK4的信号。降噪子电路，分别与上拉控制节点PUCN、第一输出端OUTPUT1、第二输出端OUTPUT2、下拉节点PD和第二电源端VGL电连接，设置为在下拉节点PD的控制下，向上拉控制节点PUCN、第一输出端OUTPUT1和第二输出端OUTPUT2提供第二电源端VGL的信号。
在一种示例性实施例中，移位寄存器的第一输出端OUTPUT1和第二输出端OUTPUT2分别输出两个不同的驱动信号。第一输出端OUTPUT1输出有效电平信号的时间与第二输出端OUTPUT2输出有效电平信号的时间不重合。其中，有效电平信号指的可以使得晶体管导通的信号。
在一种示例性实施例中，第一输入端INPUT1的输入信号是脉冲信号，第二输入端INPUT2的输入信号是脉冲信号，复位信号端RESET的输入信号 是脉冲信号。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第二电源端VGL持续提供低电平信号。
第一时钟信号端CK1、第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4的输入信号为时钟信号。第三时钟信号端CK3的输入信号为有效电平信号的时间和第四时钟信号端CK4的输入信号为有效电平信号的时间不重合。
在一种示例性实施例中，移位寄存器所在的栅极驱动电路的模式可以包括：正向扫描模式和反向扫描模式。当栅极驱动电路为正向扫描模式时，本级移位寄存器的输出发生在上一级移位寄存器的输出之后，当栅极驱动电路为反向扫描模式时，本级移位寄存器的输出发生在下一级移位寄存器的输出之后。当栅极驱动电路为正向扫描模式时，本级移位寄存器的第一信号端CN的输入信号为有效电平信号的时间与第一时钟信号端CK1的输入信号为有效电平信号的时间重合，本级移位寄存器的第二信号端CNB的输入信号为有效电平信号的时间与第二时钟信号端CK2的输入信号为有效电平信号的时间不重合。当栅极驱动电路为反向扫描模式时，本级移位寄存器的第一信号端CN的输入信号为有效电平信号的时间与第一时钟信号端CK1的输入信号为有效电平信号的时间不重合，本级移位寄存器的第二信号端CNB的输入信号为有效电平信号的时间与第二时钟信号端CK2的输入信号为有效电平信号的时间重合。其中，无效电平信号指的可以使得晶体管截止的信号。
本公开中的降噪子电路可以降低移位寄存器中的噪声，提高显示装置的工作稳定性、使用可靠性和显示效果。
本公开实施例提供的移位寄存器包括：包括：上拉控制子电路、下拉控制子电路、输出子电路和降噪子电路；上拉控制子电路，分别与第一输入端、第二输出端、第一信号端、第二信号端和上拉控制节点电连接，设置为在第一输入端和第二输出端的控制下，向上拉控制节点提供第一信号端或第二信号端的信号；下拉控制子电路，分别与第一时钟信号端、第二时钟信号端、第一信号端、第二信号端、上拉控制节点、下拉节点、第一电源端和第二电源端电连接，设置为在上拉控制节点、第一信号端、第二信号端、第一时钟 信号端和第二时钟信号端的控制下，向下拉节点提供第一电源端或第二电源端的信号；输出子电路，分别与上拉控制节点、第一电源端、第三时钟信号端、第一输出端、第四时钟信号端和第二输出端电连接，设置为在上拉控制节点和第一电源端的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号；降噪子电路，分别与上拉控制节点、第一输出端、第二输出端、下拉节点和第二电源端电连接，设置为在下拉节点的控制下，向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。本公开通过一个移位寄存器输出两个驱动信号，可以实现显示装置的窄边框，并降低功耗。
在一种示例性实施例中，输出子电路可以包括：第一输出子电路和第二输出子电路。其中，第一输出子电路，分别与上拉控制节点PUCN、第一电源端VGH、第三时钟信号端CK3和第一输出端OUTPUT1电连接，设置在为第一电源端VGH和上拉控制节点PUCN的控制下，向第一输出端OUTPUT1提供第三时钟信号端CK3的信号。第二输出子电路，分别与上拉控制节点PUCN、第一电源端VGH、第四时钟信号端CK4和第二输出端OUTPUT2电连接，设置为在第一电源端VGH和上拉控制节点PUCN的控制下，向第二输出端OUTPUT2提供第四时钟信号端CK4的信号。
图2为一种示例性实施例提供的移位寄存器的结构示意图。如图2所示，一种示例性实施例中，移位寄存器还可以包括：复位子电路。其中，复位子电路，分别与复位信号端RESET、上拉控制节点PUCN和第二电源端VGL电连接，设置为在复位信号端RESET的控制下，向上拉控制节点PUCN提供第二电源端VGL的信号。
本公开中的复位子电路可以对移位寄存器进行复位，可以降低移位寄存器中的噪声，提高显示装置的工作稳定性、使用可靠性和显示效果。
图3为一种示例性实施例提供的上拉控制子电路的等效电路图。如图3所示，一种示例性实施例中，上拉控制子电路包括：第一晶体管T1和第二晶体管T2。
在一种示例性实施例中，第一晶体管T1的控制极与第一输入端INPUT1电连接，第一晶体管T1的第一极与第一信号端CN电连接，第一晶体管T1 的第二极与上拉控制节点PUCN电连接；第二晶体管T2的控制极与第二输入端INPUT2电连接，第二晶体管T2的第一极与第二信号端CNB电连接，第二晶体管T2的第二极与上拉控制节点PUCN电连接。
在本实施例中，图3中示出了上拉控制子电路的示例性结构，本公开并不以此为限。
图4为一种示例性实施例提供的下拉控制子电路的等效电路图。如图4所示，一种示例性实施例中，下拉控制子电路可以包括：第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第一电容C1。
在一种示例性实施例中，第三晶体管T3的控制极与第一信号端CN电连接，第三晶体管T3的第一极与第一时钟信号端CK1电连接，第三晶体管T3的第二极与下拉控制节点PDCN电连接；第四晶体管T4的控制极与第二信号端CNB电连接，第四晶体管T4的第一极与第二时钟信号端CK2电连接，第四晶体管T4的第二极与下拉控制节点PDCN电连接；第五晶体管T5的控制极与下拉控制节点PDCN电连接，第五晶体管T5的第一极与第一电源端VGH电连接，第五晶体管T5的第二极与下拉节点PD电连接；第六晶体管T6的控制极与上拉控制节点PUCN电连接，第六晶体管T6的第一极与下拉节点PD电连接，第六晶体管T6的第二极与第二电源端VGL电连接；第一电容C1的第一极与下拉节点PD电连接，第一电容C1的第二极与第二电源端VGL电连接。
本公开中的第六晶体管T6由上拉控制节点PUCN控制，当上拉控制节点PUCN的信号为有效电平信号时，第六晶体管T6导通，下拉节点PD的信号被第二电源端VGL的低电平信号拉低，可以避免移位寄存器中形成电流通路，可以减少显示装置的功耗。
在本实施例中，图4中示出了上拉控制子电路的示例性结构，本公开并不以此为限。
图5为一种示例性实施例提供的输出子电路的等效电路图。如图5所示，一种示例性实施例中，输出子电路中的第一输出子电路可以包括：第七晶体管T7、第八晶体管T8和第二电容C2。第二输出子电路可以包括：第九晶体管T9、第十晶体管T10和第三电容C3。
在一种示例性实施例中，第七晶体管T7的控制极与第一电源端VGH电连接，第七晶体管T7的第一极与上拉控制节点PUCN电连接，第七晶体管T7的第二极与第一上拉节点PU1电连接；第八晶体管T8的控制极与第一上拉节点PU1电连接，第八晶体管T8的第一极与第三时钟信号端CK3电连接，第八晶体管T8的第二极与第一输出端OUTPUT1电连接；第二电容C2的第一极与第一上拉节点PU1电连接，第二电容C2的第二极与第一输出端OUTPUT1电连接。第九晶体管T9的控制极与第一电源端VGH电连接，第九晶体管T9的第一极与上拉控制节点PUCN电连接，第九晶体管T9的第二极与第二上拉节点PU2电连接；第十晶体管T10的控制极与第二上拉节点PU2电连接，第十晶体管T10的第一极与第四时钟信号端CK4电连接，第十晶体管T10的第二极与第二输出端OUTPUT2电连接；第三电容C3的第一极与第二上拉节点PU2电连接，第三电容C3的第二极与第二输出端OUTPUT2电连接。
在本实施例中，图5中示出了输出子电路的示例性结构，本公开并不以此为限。
图6为一种示例性实施例提供的降噪子电路的等效电路图。如图6所示，一种示例性实施例中，降噪子电路可以包括：第十一晶体管T11、第十二晶体管T12和第十三晶体管T13。
在一种示例性实施例中，第十一晶体管T11的控制极与下拉节点PD电连接，第十一晶体管T11的第一极与上拉控制节点PUCN电连接，第十一晶体管T11的第二极与第二电源端VGL电连接；第十二晶体管T12的控制极与下拉节点PD电连接，第十二晶体管T12的第一极与第一输出端OUTPUT1电连接，第十二晶体管T12的第二极与第二电源端VGL电连接；第十三晶体管T13的控制极与下拉节点PD电连接，第十三晶体管T13的第一极与第二输出端OUTPUT2电连接，第十三晶体管T13的第二极与第二电源端VGL电连接。
在本实施例中，图6中示出了降噪子电路的示例性结构，本公开并不以此为限。
图7为一种示例性实施例提供的复位子电路的等效电路图。如图7所示， 一种示例性实施例中，复位子电路可以包括：第十四晶体管T14。
一种示例性实施例中，第十四晶体管T14的控制极与复位信号端RESET电连接，第十四晶体管T14的第一极与上拉控制节点PUCN电连接，第十四晶体管T14的第二极与第二电源端VGL电连接。
在本实施例中，图7中示出了复位子电路的示例性结构，本公开并不以此为限。
图8为一种示例性实施例提供的移位寄存器的等效电路图。如图8所示，在一种示例性实施例中，移位寄存器还可以包括复位子电路，上拉控制子电路包括：第一晶体管T1和第二晶体管T2；下拉控制子电路包括：第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6和第一电容；输出子电路包括：第七晶体管T7、第八晶体管T8、第二电容、第九晶体管T9、第十晶体管T10和第三电容；降噪子电路包括：第十一晶体管T11、第十二晶体管T12和第十三晶体管T13；复位子电路包括：第十四晶体管T14。
在一种示例性实施例中，第一晶体管T1的控制极与第一输入端INPUT1电连接，第一晶体管T1的第一极与第一信号端CN电连接，第一晶体管T1的第二极与上拉控制节点PUCN电连接；第二晶体管T2的控制极与第二输入端INPUT2电连接，第二晶体管T2的第一极与第二信号端CNB电连接，第二晶体管T2的第二极与上拉控制节点PUCN电连接；第三晶体管T3的控制极与第一信号端CN电连接，第三晶体管T3的第一极与第一时钟信号端CK1电连接，第三晶体管T3的第二极与下拉控制节点PDCN电连接；第四晶体管T4的控制极与第二信号端CNB电连接，第四晶体管T4的第一极与第二时钟信号端CK2电连接，第四晶体管T4的第二极与下拉控制节点PDCN电连接；第五晶体管T5的控制极与下拉控制节点PDCN电连接，第五晶体管T5的第一极与第一电源端VGH电连接，第五晶体管T5的第二极与下拉节点PD电连接；第六晶体管T6的控制极与上拉控制节点PUCN电连接，第六晶体管T6的第一极与下拉节点PD电连接，第六晶体管T6的第二极与第二电源端VGL电连接；第一电容的第一极与下拉节点PD电连接，第一电容的第二极与第二电源端VGL电连接；第七晶体管T7的控制极与第一电源端VGH电连接，第七晶体管T7的第一极与上拉控制节点PUCN电连接，第 七晶体管T7的第二极与第一上拉节点PU1电连接；第八晶体管T8的控制极与第一上拉节点PU1电连接，第八晶体管T8的第一极与第三时钟信号端CK3电连接，第八晶体管T8的第二极与第一输出端OUTPUT1电连接；第二电容的第一极与第一上拉节点PU1电连接，第二电容的第二极与第一输出端OUTPUT1电连接；第九晶体管T9的控制极与第一电源端VGH电连接，第九晶体管T9的第一极与上拉控制节点PUCN电连接，第九晶体管T9的第二极与第二上拉节点PU2电连接；第十晶体管T10的控制极与第二上拉节点PU2电连接，第十晶体管T10的第一极与第四时钟信号端CK4电连接，第十晶体管T10的第二极与第二输出端OUTPUT2电连接；第三电容的第一极与第二上拉节点PU2电连接，第三电容的第二极与第二输出端OUTPUT2电连接；第十一晶体管T11的控制极与下拉节点PD电连接，第十一晶体管T11的第一极与上拉控制节点PUCN电连接，第十一晶体管T11的第二极与第二电源端VGL电连接；第十二晶体管T12的控制极与下拉节点PD电连接，第十二晶体管T12的第一极与第一输出端OUTPUT1电连接，第十二晶体管T12的第二极与第二电源端VGL电连接；第十三晶体管T13的控制极与下拉节点PD电连接，第十三晶体管T13的第一极与第二输出端OUTPUT2电连接，第十三晶体管T13的第二极与第二电源端VGL电连接；第十四晶体管T14的控制极与复位信号端RESET电连接，第十四晶体管T14的第一极与上拉控制节点PUCN电连接，第十四晶体管T14的第二极与第二电源端VGL电连接。
在一种示例性实施例中，第一晶体管T1到第十四晶体管T14可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示装置的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1到第十四晶体管T14可以包括P型晶体管和N型晶体管。
下面通过移位寄存器的工作过程说明一种示例性实施例提供的技术方案。
以移位寄存器中的晶体管T1至T14均为N型晶体管为例，图9为一种示例性实施例提供的移位寄存器的工作时序图一；图10为一种示例性实施例提供的移位寄存器的工作时序图二。如图8至图10，一种示例性实施例提供 的移位寄存器包括14个晶体管单元(T1至T14)、3个电容(C1、C2和C3)、9个信号输入端(INPUT1、INPUT2、CN、CNB、RESET、CK1、CK2、CK3和CK4)、2个信号输出端(OUTPUT1和OUTPUT2)和2个电源端(VGH和VGL)。图9是以栅极驱动电路正向扫描时，移位寄存器的工作过程为例进行说明的。图10是以栅极驱动电路反向扫描时，移位寄存器的工作过程为例进行说明的。
在一种示例性实施例中，第一电源端VGH持续提供高电平信号，第七晶体管T7和第九晶体管T9持续导通；第二电源端VGL持续提供低电平信号。
当栅极驱动电路为正向扫描模式时，本级移位寄存器的第二信号端CNB的输入信号为有效电平信号的时间与第二时钟信号端CK2的输入信号为有效电平信号的时间不重合，此时，上拉控制节点PUCN不会被第二时钟信号端CK2的高电平信号拉高，不会影响本级移位寄存器的输出。
当栅极驱动电路正向扫描时，如图8和图9所示，移位寄存器的工作过程可以包括：
第一阶段t1，即复位阶段，信号输入端中的复位信号端RESET、第一信号端CN和第一时钟信号端CK1的输入信号为高电平信号，第一输入端INPUT1、第三时钟信号端CK3和第四时钟信号端CK4的输入信号为低电平信号。复位信号端RESET的输入信号为高电平信号，第十四晶体管T14导通，第二电源端VGL的低电平信号写入上拉控制节点PUCN，以对上拉控制节点PUCN进行复位，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第一信号端CN的输入信号为高电平信号，第一时钟信号端CK1的高电平信号写入下拉控制节点PDCN，第十晶体管T10导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13导通，以对上拉控制节点、第一输出端和第二输出端进行复位。
第二阶段t2，即输入阶段，信号输入端中的第一输入端INPUT1和第一信号端CN的输入信号为高电平信号，第一时钟信号端CK1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信 号。第一输入端INPUT1为输入信号为高电平信号，第一晶体管T1导通，第一信号端CN的高电平信号写入上拉控制节点PUCN，第七晶体管T7和第九晶体管T9持续导通，上拉控制节点PUCN的高电平信号写入第一上拉节点PU1和第二上拉节点PU2，同时向第二电容C1和第三电容C3充电，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第一信号端CN的输入信号为高电平信号，第三晶体管T3导通，第一时钟信号端CK1的低电平信号写入下拉控制节点PDCN，第五晶体管T5截止，第一电源端VGH的高电平信号无法写入下拉节点PD，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号拉低，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2输出低电平信号。
第三阶段t3，信号输入端中的第一输入端INPUT1、第一信号端CN、第一时钟信号端CK1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第一晶体管T1截止，上拉控制节点PUCN保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，上拉控制节点PUCN的高电平信号写入第一上拉节点PU1和第二上拉节点PU2，同时向第二电容C2和第三电容C3充电，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第一信号端CN的输入信号为低电平信号，第三晶体管T3截止，上拉控制节点PUCN的信号为高电平信号，第八晶体管T8第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2仍输出低电平信号。
第四阶段t4，即第一输出阶段，信号输入端中的第三时钟信号端CK3的输入信号为高电平信号，第一输入端INPUT1、第一信号端CN、第一时钟 信号端CK1、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第一晶体管T1截止，上拉控制节点PUCN保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第三时钟信号端CK3的输入信号为高电平信号，第一上拉节点PU1在第二电容C2的信号的电平自举的作用下升高，第四时钟信号端CK4的输入信号为低电平信号，第二上拉节点PU2维持上一阶段的高电平信号，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的高电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第一信号端CN的输入信号为低电平信号，第三晶体管T3截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1的输出信号为高电平信号，第二输出端OUTPUT2的输出信号为低电平信号。
第五阶段t5，即第二输出阶段，信号输入端中的第四时钟信号端CK4的输入信号为高电平信号，第一输入端INPUT1、第一信号端CN、第一时钟信号端CK1、第三时钟信号端CK3和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第一晶体管T1截止，上拉控制节点PUCN仍保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第三时钟信号端CK3的输入信号为低电平信号，第一上拉节点PU1恢复为第一阶段的高电平信号，第四时钟信号端CK4的输入信号为高电平信号，第二上拉节点PU2的信号的电平在第三电容C3自举的作用下升高，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的高电平信号写入第二输出端OUTPUT2。另外，第一信号端CN的输入信号为低电平信号，第三晶体管T3截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1的输出信号为低电平信号，第二输出端OUTPUT2的输出信号为高电平信号。
第六阶段t6，信号输入端中的第一输入端INPUT1、第一信号端CN、第一时钟信号端CK1、第三时钟信号端CK3、第四时钟信号端CK4的输入信号和复位信号端RESET为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第一晶体管T1截止，上拉控制节点PUCN仍保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第三时钟信号端CK3的输入信号为低电平信号，第一上拉节点PU1恢复为第一阶段的高电平信号，第四时钟信号端CK4的输入信号为低电平信号，第二上拉节点PU2恢复为第一阶段的高电平信号，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第一信号端CN的输入信号为低电平信号，第三晶体管T3截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
第七阶段t7，即降噪阶段，信号输入端中的第一信号端CN和第一时钟信号端CK1的输入信号为高电平信号，第一输入端INPUT1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一信号端CN的输入信号为高电平信号，第三晶体管T3导通，第一时钟信号端CK1的高电平信号写入下拉控制节点PDCN，第五晶体管T5导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11导通，第二电源端VGL的低电平信号写入上拉控制节点PDCN，此时，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第七晶体管T7和第九晶体管T9持续导通，第一上拉节点PU1和第二上拉节点PU2的电位被拉低，第八晶体管T8和第十晶体管T10截止，第十二晶体管T12导通，第一输出端OUTPUT1的信号被第二电源端VGL的低电平信号拉低，第十三晶体管T13导通，第二输出端OUTPUT2的信号被第二电源端VGL的低电平信号拉低。本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
第八阶段t8，信号输入端中的第一信号端CN、第一时钟信号端CK1、第一输入端INPUT1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一信号端CN的输入信号为低电平信号，第三晶体管T3截止，第一电容C1开始放电，下拉控制节点PDCN保持上一阶段的高电平信号，第五晶体管T5导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11导通，第二电源端VGL的低电平信号写入上拉控制节点PDCN，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第七晶体管T7和第九晶体管T9持续导通，第一上拉节点PU1和第二上拉节点PU2的电位被拉低，第八晶体管T8和第十晶体管T110截止，第十二晶体管T12导通，第一输出端OUTPUT1的信号被第二电源端VGL的低电平信号拉低，第十三晶体管T13导通，第二输出端OUTPUT2的信号被第二电源端VGL的低电平信号拉低。本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
当栅极驱动电路为反向扫描模式时，本级移位寄存器的第一信号端CN的输入信号为有效电平信号的时间与第一时钟信号端CK1的输入信号为有效电平信号的时间不重合，此时，上拉控制节点PUCN不会被第一时钟信号端CK1的高电平信号拉高，不会影响本级移位寄存器的输出。
当栅极驱动电路反向扫描时，如图8和图10所示，移位寄存器的工作过程可以包括：
第一阶段t1，即复位阶段，信号输入端中的复位信号端RESET、第二信号端CNB和第二时钟信号端CK2的输入信号为高电平信号，第一输入端INPUT1、第三时钟信号端CK3和第四时钟信号端CK4的输入信号为低电平信号。复位信号端RESET的输入信号为高电平信号，第十四晶体管T14导通，第二电源端VGL的低电平信号写入上拉控制节点PUCN，以对上拉控制节点PUCN进行复位，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第二信号端CNB的输入信号为高电平信号，第二时钟信号端CK2的高电平信号写入下拉控制节点PDCN，第十晶体管T10导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13导通，以对上拉控制节点、第一输出端和 第二输出端进行复位。
第二阶段t2，即输入阶段，信号输入端中的第一输入端INPUT1和第二信号端CNB的输入信号为高电平信号，第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为高电平信号，第二晶体管T2导通，第二信号端CNB的高电平信号写入上拉控制节点PUCN，第七晶体管T7和第九晶体管T9持续导通，上拉控制节点PUCN的高电平信号写入第一上拉节点PU1和第二上拉节点PU2，同时向第二电容C1和第三电容C3充电，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第二信号端CNB的输入信号为高电平信号，第四晶体管T4导通，第二时钟信号端CK2的低电平信号写入下拉控制节点PDCN，第五晶体管T5截止，第一电源端VGH的高电平信号无法写入下拉节点PD，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号拉低，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2输出低电平信号。
第三阶段t3，信号输入端中的第一输入端INPUT1、第二信号端CNB、第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第二晶体管T2截止，上拉控制节点PUCN保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，上拉控制节点PUCN的高电平信号写入第一上拉节点PU1和第二上拉节点PU2，同时向第二电容C2和第三电容C3充电，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第二信号端CNB的输入信号为低电平信号，第四晶体管T4截止，上拉控制节点PUCN的信号为高电平信号，第八晶体管T8第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号拉低，仍保持为低电平，第十一晶体管T11、第十二 晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2仍输出低电平信号。
第四阶段t4，即第一输出阶段，信号输入端中的第四时钟信号端CK4的输入信号为高电平信号，第一输入端INPUT1、第二信号端CNB、第二时钟信号端CK2、第三时钟信号端CK3和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第二晶体管T2截止，上拉控制节点PUCN保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第四时钟信号端CK4的输入信号为高电平信号，第二上拉节点PU2在第三电容C3的信号的电平自举的作用下升高，第三时钟信号端CK3的输入信号为低电平信号，第一上拉节点PU1维持上一阶段的高电平信号，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的稿电平信号写入第二输出端OUTPUT2。另外，第二信号端CNB的输入信号为低电平信号，第四晶体管T4截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1的输出信号为低电平信号，第二输出端OUTPUT2的输出信号为高电平信号。
第五阶段t5，即第二输出阶段，信号输入端中的第三时钟信号端CK3的输入信号为高电平信号，第一输入端INPUT1、第二信号端CNB、第二时钟信号端CK2、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第二晶体管T2截止，上拉控制节点PUCN仍保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第三时钟信号端CK3的输入信号为高电平信号，第一上拉节点PU1的信号的电平在第二电容C2自举的作用下升高，第四时钟信号端CK4的输入信号为低电平信号，第二上拉节点PU2的信号恢复为第一阶段的高电平信号，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的高电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第二信号端CNB 的输入信号为低电平信号，第四晶体管T4截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1的输出信号为高电平信号，第二输出端OUTPUT2的输出信号为低电平信号。
第六阶段t6，信号输入端中的第一输入端INPUT1、第二信号端CNB、第二时钟信号端CK2、第三时钟信号端CK3、第四时钟信号端CK4的输入信号和复位信号端RESET为低电平信号。第一输入端INPUT1为输入信号为低电平信号，第二晶体管T2截止，上拉控制节点PUCN仍保持上一阶段的高电平信号，第七晶体管T7和第九晶体管T9持续导通，由于第三时钟信号端CK3的输入信号为低电平信号，第一上拉节点PU1恢复为第一阶段的高电平信号，第四时钟信号端CK4的输入信号为低电平信号，第二上拉节点PU2恢复为第一阶段的高电平信号，第八晶体管T8和第十晶体管T10导通，第三时钟信号端CK3的低电平信号写入第一输出端OUTPUT1，第四时钟信号端CK4的低电平信号写入第二输出端OUTPUT2。另外，第二信号端CNB的输入信号为低电平信号，第四晶体管T4截止，上拉控制节点PUCN的信号为高电平信号，第六晶体管T6导通，下拉节点PD的电位被第二电源端VLG的低电平信号持续拉低，仍保持为低电平，第十一晶体管T11、第十二晶体管T12和第十三晶体管T13截止，本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
第七阶段t7，即降噪阶段，信号输入端中的第二信号端CNB和第二时钟信号端CK2的输入信号为高电平信号，第一输入端INPUT1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第二信号端CNB的输入信号为高电平信号，第四晶体管T4导通，第二时钟信号端CK2的高电平信号写入下拉控制节点PDCN，第五晶体管T5导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11导通，第二电源端VGL的低电平信号写入上拉控制节点PDCN，此时，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第七晶体管T7和第九晶体管T9持续导通，第一上拉节点PU1和第二上拉节点 PU2的电位被拉低，第八晶体管T8和第十晶体管T10截止，第十二晶体管T12导通，第一输出端OUTPUT1的信号被第二电源端VGL的低电平信号拉低，第十三晶体管T13导通，第二输出端OUTPUT2的信号被第二电源端VGL的低电平信号拉低。本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
第八阶段t8，信号输入端中的第二信号端CNB、第二时钟信号端CK2、第一输入端INPUT1、第三时钟信号端CK3、第四时钟信号端CK4和复位信号端RESET的输入信号为低电平信号。第二信号端CNB的输入信号为低电平信号，第四晶体管T4截止，第一电容C1开始放电，下拉控制节点PDCN保持上一阶段的高电平信号，第五晶体管T5导通，第一电源端VGH的高电平信号写入下拉节点PD，第十一晶体管T11导通，第二电源端VGL的低电平信号写入上拉控制节点PDCN，第六晶体管T6截止，第二电源端VGL的低电平信号无法写入下拉节点PD，第七晶体管T7和第九晶体管T9持续导通，第一上拉节点PU1和第二上拉节点PU2的电位被拉低，第八晶体管T8和第十晶体管T110截止，第十二晶体管T12导通，第一输出端OUTPUT1的信号被第二电源端VGL的低电平信号拉低，第十三晶体管T13导通，第二输出端OUTPUT2的信号被第二电源端VGL的低电平信号拉低。本阶段，第一输出端OUTPUT1和第二输出端OUTPUT2的输出信号为低电平信号。
本公开提供的移位寄存器包括14个晶体管和3个电容可以通过第一输出端和第二输出端输出两个栅极驱动信号，减少了栅极驱动电路中的晶体管和电容的数量，节省了布线空间，减少了栅极驱动电路所占用的面积，可以实现显示装置的窄边框，并降低功耗。本公开中在上拉控制节点的信号为高电平信号时，第六晶体管导通，拉低下拉节点PD的电位，可以避免移位寄存器中存在电流通路，并避免电路通路产生的静态功耗。本公开实施例提供的移位寄存器的功耗比只输出一个栅极驱动信号的移位寄存器的功耗降低20％。
图11为本公开实施例提供的移位寄存器的驱动方法的流程图。如图11所示，本公开实施例提供的移位寄存器的驱动方法，设置为驱动移位寄存器，本公开实施例提供的移位寄存器的驱动方法可以包括：
步骤S1、在第一输入端和第二输出端的控制下，上拉控制子电路向上拉 控制节点提供第一信号端或第二信号端的信号。
步骤S2、在上拉控制节点、第一信号端、第二信号端、第一时钟信号端和第二时钟信号端的控制下，下拉控制子电路向下拉节点提供第一电源端或第二电源端的信号。
步骤S3、在上拉控制节点和第一电源端的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号。
步骤S4、在下拉节点的控制下，降噪子电路向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。
移位寄存器为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，移位寄存器的驱动方法还可以包括：在复位信号端的控制下，复位子电路向上拉控制节点提供第二电源端的信号。
图12为本公开实施例提供的栅极驱动电路的结构示意图。如图12所示，本公开实施例的栅极驱动电路，包括多个级联的移位寄存器。其中，第i+1级移位寄存器的第一输入端INPUT1与第i级移位寄存器的第一输出端OUTPUT1电连接，第i+1级移位寄存器的第二输入端INPUT2与第i+2级移位寄存器的第二输出端OUTPUT2电连接。
移位寄存器为前述任一个实施例提供的移位寄存器，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，如图12所示，栅极驱动电路还可以包括：初始信号线STV、第一时钟线CLK1、第二时钟线CLK2、第三时钟线CLK3、第四时钟线CLK4、第五时钟线CLK5、第六时钟线CLK6、复位信号线RST、第一电源线Vgh、第二电源线Vgl、第一信号线CNL和第二信号线CNBL。
在一种示例性实施例中，所有移位寄存器的复位信号端RESET与复位信号线RST连接，所有移位寄存器的第一电源端VGH与第一电源线Vgh连接，所有移位寄存器的第二电源端VGL与第二电源线Vgl连接，所有移位寄存器的第一信号端CN与第一信号线CNL连接，所有移位寄存器的第二信号端CNB与第二信号线CNBL连接。
在一种示例性实施例中，第一级移位寄存器GOA(1)的第一输入端INPUT1与初始信号线STV连接。
在一种示例性实施例中，第3i-2级移位寄存器GOA(3i-2)的第一时钟信号端CK1与第六时钟线CLK6连接，第3i-2级移位寄存器GOA(3i-2)的第二时钟信号端CK2与第一时钟线CLK1连接，第3i-2级移位寄存器GOA(3i-2)的第三时钟信号端CK3与第三时钟线CLK3连接，第3i-2级移位寄存器GOA(3i-2)的第四时钟信号端CK4与第四时钟线CLK4连接，第3i-1级移位寄存器GOA(3i-1)的第一时钟信号端CK1与第二时钟线CLK2连接，第3i-1级移位寄存器GOA(3i-1)的第二时钟信号端CK2与第三时钟线CLK3连接，第3i-1级移位寄存器GOA(3i-1)的第三时钟信号端CK3与第五时钟线CLK5连接，第3i-1级移位寄存器GOA(3i-1)的第四时钟信号端CK4与第六时钟线CLK6连接，第3i级移位寄存器GOA(3i)的第一时钟信号端CK1与第四时钟线CLK4连接，第3i级移位寄存器器GOA(3i)的第二时钟信号端CK2与第五时钟线CLK5连接，第3i级移位寄存器器GOA(3i)的第三时钟信号端CK3与第一时钟线CLK1连接，第3i级移位寄存器器GOA(3i)的第四时钟信号端CK4与第二时钟线CLK2连接。示例性地，第一级移位寄存器GOA(1)的第一时钟信号端CK1与第六时钟线CLK6连接，第一级移位寄存器GOA(1)的第二时钟信号端CK2与第一时钟线CLK1连接，第一级移位寄存器GOA(1)的第三时钟信号端CK3与第三时钟线CLK3连接，第一级移位寄存器GOA(1)的第四时钟信号端CK4与第四时钟线CLK4连接，第二级移位寄存器GOA(2)的第一时钟信号端CK1与第二时钟线CLK2连接，第二级移位寄存器GOA(2)的第二时钟信号端CK2与第三时钟线CLK3连接，第二级移位寄存器GOA(2)的第三时钟信号端CK3与第五时钟线CLK5连接，第二级移位寄存器GOA(2)的第四时钟信号端CK4与第六时钟线CLK6连接，第三级移位寄存器GOA(3)的第一时钟信号端CK1与第四时钟线CLK4连接，第三级移位寄存器GOA(3)的第二时钟信号端CK2与第五时钟线CLK5连接，第三级移位寄存器GOA(3)的第三时钟信号端CK3与第一时钟线CLK1连接，第三级移位寄存器GOA(3)的第四时钟信号端CK4与第二时钟线CLK2连接
在一种示例性实施例中，第i+1级移位寄存器GOA(i+1)的第一输入端INPUT1与第i级移位寄存器GOA(i)的第二输出端OUTPUT2电连接，第i+1级移位寄存器GOA(i+1)的第二输入端INPUT2与第i+2级移位寄存器GOA(i+2)的第一输出端OUTPUT1电连接。例如，第一级移位寄存器GOA(1)的第一输入端INPUT1与初始信号端STV连接，第二级移位寄存器GOA(2)的第一输入端INPUT1与第一级移位寄存器GOA(1)的第二输出端OUTPUT2电连接，第二级移位寄存器GOA(2)的第二输入端INPUT2与第三级移位寄存器GOA(3)的第一输出端OUTPUT1电连接，依次类推。
图13为本公开实施例提供的显示装置的结构示意图。如图13所示，本公开实施例提供的还提供了一种显示装置，包括：栅极驱动电路10和多条扫描信号线(图中未示出)；扫描信号线沿第一方向延伸，多条扫描信号线沿第二方向排布，第一方向和第二方向相交。栅极驱动电路与多条扫描信号线电连接。
在一种示例性实施例中，显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
栅极驱动电路为前述任一个实施例提供的栅极驱动电路，实现原理和实现效果类似，在此不再赘述。
在一种示例性实施例中，栅极驱动电路10沿第一方向的长度L1约为0.35毫米至0.37毫米。示例性地，栅极驱动电路10沿第一方向的长度L1可以为0.36毫米
在一种示例性实施例中，栅极驱动电路中的第j级移位寄存器与第2j-1条扫描信号线和第2j条扫描信号线连接，1≤j≤N，N为栅极驱动电路中包括的移位寄存器的数量。
在一种示例性实施例中，显示装置包括：显示区和非显示区。栅极驱动电路10设置在非显示区。
在一种示例性实施例中，非显示区沿第一方向的长度可以为0.6毫米至0.8毫米。示例性地，非显示区沿第一方向的长度可以为0.7毫米。
在一种示例性实施例中，如图13所示，非显示区还包括：位于栅极驱动 电路靠近显示区一侧的接地信号线20，接地信号线20沿第一方向的长度L2可以为0.01毫米至0.03毫米。示例性地，接地信号线20沿第一方向的长度L2可以为0.02毫米。
在一种示例性实施例中，接地信号线远离显示区的一侧与非显示区的边缘之间的距离L4可以为0.15毫米至0.25毫米。示例性地，接地信号线远离显示区的一侧与非显示区的边缘之间的距离L4可以为0.2毫米。
在一种示例性实施例中，接地信号线靠近显示区的一侧与栅极驱动电路远离显示区的一侧之间的距离L5可以为0.01毫米至0.03毫米。示例性地，接地信号线靠近显示区的一侧与栅极驱动电路远离显示区的一侧之间的距离L5可以为0.02毫米。
在一种示例性实施例中，如图13所示，非显示区还可以包括：虚拟像素区域30。虚拟像素区域30沿第一方向的长度L3可以为0.02毫米至0.04毫米。示例性地，虚拟像素区域30沿第一方向的长度L3可以为0.03毫米。
在一种示例性实施例中，栅极驱动电路20靠近显示区的一侧与虚拟像素区域之间的距离L6可以为0.01毫米至0.03毫米。示例性地，栅极驱动电路20靠近显示区的一侧与虚拟像素区域之间的距离L6可以为0.02毫米。
本公开中的附图只涉及本公开实施例涉及到的结构，其他结构可参考通常设计。
为了清晰起见，在用于描述本公开的实施例的附图中，层或微结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或面板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种移位寄存器，包括：上拉控制子电路、下拉控制子电路、输出子电路和降噪子电路；
    所述上拉控制子电路，分别与第一输入端、第二输出端、第一信号端、第二信号端和上拉控制节点电连接，设置为在第一输入端和第二输出端的控制下，向上拉控制节点提供第一信号端或第二信号端的信号；
    所述下拉控制子电路，分别与第一时钟信号端、第二时钟信号端、第一信号端、第二信号端、上拉控制节点、下拉节点、第一电源端和第二电源端电连接，设置为在上拉控制节点、第一信号端、第二信号端、第一时钟信号端和第二时钟信号端的控制下，向下拉节点提供第一电源端或第二电源端的信号；
    所述输出子电路，分别与上拉控制节点、第一电源端、第三时钟信号端、第一输出端、第四时钟信号端和第二输出端电连接，设置为在上拉控制节点和第一电源端的控制下，向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号；
    所述降噪子电路，分别与上拉控制节点、第一输出端、第二输出端、下拉节点和第二电源端电连接，设置为在下拉节点的控制下，向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。
  2. 根据权利要求1所述的移位寄存器，其中，所述输出子电路包括：第一输出子电路和第二输出子电路；
    所述第一输出子电路，分别与上拉控制节点、第一电源端、第三时钟信号端和第一输出端电连接，设置在为第一电源端和上拉控制节点的控制下，向第一输出端提供第三时钟信号端的信号；
    所述第二输出子电路，分别与上拉控制节点、第一电源端、第四时钟信号端和第二输出端电连接，设置为在第一电源端和上拉控制节点的控制下，向第二输出端提供第四时钟信号端的信号。
  3. 根据权利要求1或2所述的移位寄存器，还包括：复位子电路；
    所述复位子电路，分别与复位信号端、上拉控制节点和第二电源端电连 接，设置为在复位信号端的控制下，向上拉控制节点提供第二电源端的信号。
  4. 根据权利要求1所述的移位寄存器，其中，所述上拉控制子电路包括：第一晶体管和第二晶体管；
    所述第一晶体管的控制极与第一输入端电连接，所述第一晶体管的第一极与第一信号端电连接，所述第一晶体管的第二极与上拉控制节点电连接；
    所述第二晶体管的控制极与第二输入端电连接，所述第二晶体管的第一极与第二信号端电连接，所述第二晶体管的第二极与上拉控制节点电连接。
  5. 根据权利要求1所述的移位寄存器，其中，所述下拉控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；
    所述第三晶体管的控制极与第一信号端电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与下拉控制节点电连接；
    所述第四晶体管的控制极与第二信号端电连接，所述第四晶体管的第一极与第二时钟信号端电连接，所述第四晶体管的第二极与下拉控制节点电连接；
    所述第五晶体管的控制极与下拉控制节点电连接，所述第五晶体管的第一极与第一电源端电连接，所述第五晶体管的第二极与下拉节点电连接；
    所述第六晶体管的控制极与上拉控制节点电连接，所述第六晶体管的第一极与下拉节点电连接，所述第六晶体管的第二极与第二电源端电连接；
    所述第一电容的第一极与下拉节点电连接，所述第一电容的第二极与第二电源端电连接。
  6. 根据权利要求2所述的移位寄存器，其中，所述第一输出子电路包括：第七晶体管、第八晶体管和第二电容；
    所述第七晶体管的控制极与第一电源端电连接，所述第七晶体管的第一极与上拉控制节点电连接，所述第七晶体管的第二极与第一上拉节点电连接；
    所述第八晶体管的控制极与第一上拉节点电连接，所述第八晶体管的第一极与第三时钟信号端电连接，所述第八晶体管的第二极与第一输出端电连接；
    所述第二电容的第一极与第一上拉节点电连接，所述第二电容的第二极与第一输出端电连接。
  7. 根据权利要求2所述的移位寄存器，其中，所述第二输出子电路包括：第九晶体管、第十晶体管和第三电容；
    所述第九晶体管的控制极与第一电源端电连接，所述第九晶体管的第一极与上拉控制节点电连接，所述第九晶体管的第二极与第二上拉节点电连接；
    所述第十晶体管的控制极与第二上拉节点电连接，所述第十晶体管的第一极与第四时钟信号端电连接，所述第十晶体管的第二极与第二输出端电连接；
    所述第三电容的第一极与第二上拉节点电连接，所述第三电容的第二极与第二输出端电连接。
  8. 根据权利要求1所述的移位寄存器，其中，所述降噪子电路包括：第十一晶体管、第十二晶体管和第十三晶体管；
    所述第十一晶体管的控制极与下拉节点电连接，所述第十一晶体管的第一极与上拉控制节点电连接，所述第十一晶体管的第二极与第二电源端电连接；
    所述第十二晶体管的控制极与下拉节点电连接，所述第十二晶体管的第一极与第一输出端电连接，所述第十二晶体管的第二极与第二电源端电连接；
    所述第十三晶体管的控制极与下拉节点电连接，所述第十三晶体管的第一极与第二输出端电连接，所述第十三晶体管的第二极与第二电源端电连接。
  9. 根据权利要求3所述的移位寄存器，其中，所述复位子电路包括：第十四晶体管；
    所述第十四晶体管的控制极与复位信号端电连接，所述第十四晶体管的第一极与上拉控制节点电连接，所述第十四晶体管的第二极与第二电源端电连接。
  10. 根据权利要求1所述的移位寄存器，还包括复位子电路，所述上拉控制子电路包括：第一晶体管和第二晶体管；所述下拉控制子电路包括：第三晶体管、第四晶体管、第五晶体管、第六晶体管和第一电容；所述输出子 电路包括：第七晶体管、第八晶体管、第二电容、第九晶体管、第十晶体管和第三电容；所述降噪子电路包括：第十一晶体管、第十二晶体管和第十三晶体管；所述复位子电路包括：第十四晶体管；
    所述第一晶体管的控制极与第一输入端电连接，所述第一晶体管的第一极与第一信号端电连接，所述第一晶体管的第二极与上拉控制节点电连接；
    所述第二晶体管的控制极与第二输入端电连接，所述第二晶体管的第一极与第二信号端电连接，所述第二晶体管的第二极与上拉控制节点电连接；
    所述第三晶体管的控制极与第一信号端电连接，所述第三晶体管的第一极与第一时钟信号端电连接，所述第三晶体管的第二极与下拉控制节点电连接；
    所述第四晶体管的控制极与第二信号端电连接，所述第四晶体管的第一极与第二时钟信号端电连接，所述第四晶体管的第二极与下拉控制节点电连接；
    所述第五晶体管的控制极与下拉控制节点电连接，所述第五晶体管的第一极与第一电源端电连接，所述第五晶体管的第二极与下拉节点电连接；
    所述第六晶体管的控制极与上拉控制节点电连接，所述第六晶体管的第一极与下拉节点电连接，所述第六晶体管的第二极与第二电源端电连接；
    所述第一电容的第一极与下拉节点电连接，所述第一电容的第二极与第二电源端电连接；
    所述第七晶体管的控制极与第一电源端电连接，所述第七晶体管的第一极与上拉控制节点电连接，所述第七晶体管的第二极与第一上拉节点电连接；
    所述第八晶体管的控制极与第一上拉节点电连接，所述第八晶体管的第一极与第三时钟信号端电连接，所述第八晶体管的第二极与第一输出端电连接；
    所述第二电容的第一极与第一上拉节点电连接，所述第二电容的第二极与第一输出端电连接；
    所述第九晶体管的控制极与第一电源端电连接，所述第九晶体管的第一极与上拉控制节点电连接，所述第九晶体管的第二极与第二上拉节点电连接；
    所述第十晶体管的控制极与第二上拉节点电连接，所述第十晶体管的第一极与第四时钟信号端电连接，所述第十晶体管的第二极与第二输出端电连接；
    所述第三电容的第一极与第二上拉节点电连接，所述第三电容的第二极与第二输出端电连接；
    所述第十一晶体管的控制极与下拉节点电连接，所述第十一晶体管的第一极与上拉控制节点电连接，所述第十一晶体管的第二极与第二电源端电连接；
    所述第十二晶体管的控制极与下拉节点电连接，所述第十二晶体管的第一极与第一输出端电连接，所述第十二晶体管的第二极与第二电源端电连接；
    所述第十三晶体管的控制极与下拉节点电连接，所述第十三晶体管的第一极与第二输出端电连接，所述第十三晶体管的第二极与第二电源端电连接；
    所述第十四晶体管的控制极与复位信号端电连接，所述第十四晶体管的第一极与上拉控制节点电连接，所述第十四晶体管的第二极与第二电源端电连接。
  11. 一种栅极驱动电路，包括多个级联的如权利要求1至10任一项所述的移位寄存器；
    第i+1级移位寄存器的第一输入端与第i级移位寄存器的第一输出端电连接，第i+1级移位寄存器的第二输入端与第i+2级移位寄存器的第二输出端电连接。
  12. 根据权利要求11所述的栅极驱动电路，还包括：初始信号线、第一时钟线、第二时钟线、第三时钟线、第四时钟线、第五时钟线、第六时钟线、复位信号线、第一电源线、第二电源线、第一信号线和第二信号线；
    所有移位寄存器的复位信号端与复位信号线连接，所有移位寄存器的第一电源端与第一电源线连接，所有移位寄存器的第二电源端与第二电源线连接，所有移位寄存器的第一信号端与第一信号线连接，所有移位寄存器的第二信号端与第二信号线连接；
    第一级移位寄存器的第一输入端与初始信号线连接，第3i-2级移位寄存 器的第一时钟信号端与第六时钟线连接，第3i-2级移位寄存器的第二时钟信号端与第一时钟线连接，第3i-2级移位寄存器的第三时钟信号端与第三时钟线连接，第3i-2级移位寄存器的第四时钟信号端与第四时钟线连接，第3i-1级移位寄存器的第一时钟信号端与第二时钟线连接，第3i-1级移位寄存器的第二时钟信号端与第三时钟线连接，第3i-1级移位寄存器的第三时钟信号端与第五时钟线连接，第3i-1级移位寄存器的第四时钟信号端与第六时钟线连接，第3i级移位寄存器的第一时钟信号端与第四时钟线连接，第3i级移位寄存器的第二时钟信号端与第五时钟线连接，第3i级移位寄存器的第三时钟信号端与第一时钟线连接，第3i级移位寄存器的第四时钟信号端与第二时钟线连接。
  13. 一种显示装置，包括：如权利要求11或12所述的栅极驱动电路和多条扫描信号线；所述扫描信号线沿第一方向延伸，多条扫描信号线沿第二方向排布，所述第一方向和所述第二方向相交；
    所述栅极驱动电路中的第j级移位寄存器与第2j-1条扫描信号线和第2j条扫描信号线连接，1≤j≤N，N为栅极驱动电路中包括的移位寄存器的数量。
  14. 根据权利要求13所述的装置，其中，所述栅极驱动电路沿第一方向的长度约为0.35毫米至0.37毫米。
  15. 一种移位寄存器的驱动方法，设置为驱动如权利要求1至10任一项所述的移位寄存器，所述方法包括：
    在第一输入端和第二输出端的控制下，上拉控制子电路向上拉控制节点提供第一信号端或第二信号端的信号；
    在上拉控制节点、第一信号端、第二信号端、第一时钟信号端和第二时钟信号端的控制下，下拉控制子电路向下拉节点提供第一电源端或第二电源端的信号；
    在上拉控制节点和第一电源端的控制下，输出子电路向第一输出端提供第三时钟信号端的信号，向第二输出端提供第四时钟信号端的信号；
    在下拉节点的控制下，降噪子电路向上拉控制节点、第一输出端和第二输出端提供第二电源端的信号。
  16. 根据权利要求15所述的方法，还包括：在复位信号端的控制下，复位子电路向上拉控制节点提供第二电源端的信号。
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