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WO2021022554A1 - 移位寄存器单元及驱动方法、栅极驱动电路和显示装置 - Google Patents

移位寄存器单元及驱动方法、栅极驱动电路和显示装置 Download PDF

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Publication number
WO2021022554A1
WO2021022554A1 PCT/CN2019/099801 CN2019099801W WO2021022554A1 WO 2021022554 A1 WO2021022554 A1 WO 2021022554A1 CN 2019099801 W CN2019099801 W CN 2019099801W WO 2021022554 A1 WO2021022554 A1 WO 2021022554A1
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WO
WIPO (PCT)
Prior art keywords
node
transistor
terminal
circuit
output
Prior art date
Application number
PCT/CN2019/099801
Other languages
English (en)
French (fr)
Inventor
冯雪欢
李永谦
Original Assignee
京东方科技集团股份有限公司
合肥京东方卓印科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 合肥京东方卓印科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US16/957,161 priority Critical patent/US11244595B2/en
Priority to CN201980001296.XA priority patent/CN112639947B/zh
Priority to CN202210028284.XA priority patent/CN114300029A/zh
Priority to PCT/CN2019/099801 priority patent/WO2021022554A1/zh
Publication of WO2021022554A1 publication Critical patent/WO2021022554A1/zh
Priority to US17/555,695 priority patent/US11688318B2/en
Priority to US18/313,576 priority patent/US12057046B2/en
Priority to US18/754,789 priority patent/US20240346973A1/en

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/061—Details of flat display driving waveforms for resetting or blanking
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only

Definitions

  • the embodiments of the present disclosure relate to a shift register unit and a driving method, a gate driving circuit, and a display device.
  • a pixel array of a liquid crystal display panel or an Organic Light Emitting Diode (OLED) display panel usually includes multiple rows of gate lines and multiple columns of data lines interlaced with the multiple rows of gate lines.
  • the gate line can be driven by a gate drive circuit.
  • the gate drive circuit is usually integrated in a gate drive chip (Gate IC).
  • At least one embodiment of the present disclosure provides a shift register unit including an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit.
  • the input circuit is connected to the input terminal and is configured to control the level of the first node in response to the input signal input from the input terminal;
  • the first control circuit is connected to the input terminal, the first node and The second node is connected and is configured to control the level of the second node in response to the input signal input by the input terminal and the level of the first node;
  • the blanking control circuit is The first node and the second node are connected, and are configured to control the level of the first node and the second node under the control of a selection control signal, a first clock signal, and the level of the first node.
  • the level of the node is controlled; the first output circuit includes a first output terminal, and the first output circuit is configured to output the first output terminal at the first output terminal under the control of the level of the first node An output signal; the second output circuit includes a second output terminal, and the second output circuit is configured to output a second output signal at the second output terminal under the control of the level of the second node .
  • the blanking control circuit includes a first control sub-circuit, a second control sub-circuit, and a third control sub-circuit; the first control sub-circuit and The first node is connected to the first blanking node, and is configured to control the level of the first blanking node under the control of the selection control signal and the level of the first node;
  • the second control sub-circuit is connected to the first blanking node and the second blanking node, and is configured to control the power of the second blanking node under the control of the level of the first blanking node.
  • the third control sub-circuit is connected to the second blanking node, the first node and the second node, and is configured to control the first clock signal under the control of the The levels of the first node and the second node are controlled.
  • the first control sub-circuit includes a first transistor and a first capacitor
  • the second control sub-circuit includes a second transistor
  • the third control The sub-circuit includes a third transistor and a fourth transistor; the gate of the first transistor is connected to the selection control terminal to receive the selection control signal, the first electrode of the first transistor is connected to the first node, so The second electrode of the first transistor is connected to the first blanking node; the first electrode of the first capacitor is connected to the first blanking node, and the second electrode of the first capacitor is connected to a first voltage
  • the gate of the second transistor is connected to the first blanking node, and the first electrode of the second transistor is connected to the first clock signal terminal to receive the first clock signal.
  • the second pole of the second transistor is connected to the second blanking node; the gate of the third transistor is connected to the first clock signal terminal to receive the first clock signal, and the third The first pole of the transistor is connected to the second blanking node, the second pole of the third transistor is connected to the first node; the gate of the fourth transistor is connected to the first clock signal terminal to Receiving the first clock signal, the first pole of the fourth transistor is connected to the second blanking node, and the second pole of the fourth transistor is connected to the second node.
  • the first output terminal includes a shift output terminal and at least one scan signal output terminal.
  • the first output circuit includes a fifth transistor, a Six transistors and a second capacitor; the gate of the fifth transistor is connected to the first node, and the first electrode of the fifth transistor is connected to the second clock signal terminal to receive a second clock signal and serve as the first An output signal, the second electrode of the fifth transistor is connected to the shift output terminal; the gate of the sixth transistor is connected to the first node, and the first electrode of the sixth transistor is connected to the third
  • the clock signal terminal is connected to receive the third clock signal as the first output signal, the second pole of the sixth transistor is connected to the scan signal output terminal; the first pole of the second capacitor is connected to the first output signal.
  • a node is connected, the second pole of the second capacitor is connected to the second pole of the fifth transistor or the sixth transistor; the second clock signal and the third clock signal have the same timing in the display period .
  • the second output circuit includes a seventh transistor and a third capacitor; the gate of the seventh transistor is connected to the second node, and the The first pole of the seventh transistor is connected to the fourth clock signal terminal to receive the fourth clock signal as the second output signal, and the second pole of the seventh transistor is connected to the second output terminal; The first pole of the three capacitor is connected to the second node, and the second pole of the third capacitor is connected to the second output terminal.
  • the input circuit includes an eighth transistor; the gate of the eighth transistor is connected to the input terminal to receive the input signal, and the first The first pole and the second voltage terminal of the eight transistor are connected to receive the second voltage, and the second pole of the eighth transistor is connected with the first node.
  • the first control circuit includes a ninth transistor; the gate of the ninth transistor is connected to the input terminal to receive the input signal, so The first electrode of the ninth transistor is connected to the first node, and the second electrode of the ninth transistor is connected to the second node.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a second control circuit and a third control circuit; the second control circuit is connected to the first node and the third node, and is configured to Under the control of the level of the first node, the level of the third node is controlled; the third control circuit is connected to the second node and the fourth node, and is configured to be at the second node Under the control of the level of, the level of the fourth node is controlled.
  • the second control circuit includes a tenth transistor and an eleventh transistor
  • the third control circuit includes a twelfth transistor and a thirteenth transistor
  • the gate of the tenth transistor is connected to the first electrode and is connected to the second voltage terminal to receive the second voltage, and the second electrode of the tenth transistor is connected to the third node
  • the eleventh transistor The gate of the eleventh transistor is connected to the first node, the first electrode of the eleventh transistor is connected to the third node, and the second electrode of the eleventh transistor is connected to the first voltage terminal to receive the first voltage
  • the gate of the twelfth transistor is connected to the first pole, and is connected to the second voltage terminal to receive the second voltage, and the second pole of the twelfth transistor is connected to the fourth node
  • the gate of the thirteenth transistor is connected to the second node, the first electrode of the thirteenth transistor is connected to the fourth node, and the second electrode of the thirteenth transistor is connected to the A voltage
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first node noise reduction circuit and a second node noise reduction circuit; the first node noise reduction circuit is connected to the first node and the third node. Node connected, and configured to reduce noise to the first node under the control of the level of the third node; the second node noise reduction circuit is connected to the second node and the fourth node, And it is configured to perform noise reduction on the second node under the control of the level of the fourth node.
  • the first node noise reduction circuit includes a fourteenth transistor
  • the second node noise reduction circuit includes a fifteenth transistor
  • the gate of the transistor is connected to the third node, the first electrode of the fourteenth transistor is connected to the first node, and the second electrode of the fourteenth transistor is connected to the first voltage terminal to receive the first Voltage;
  • the gate of the fifteenth transistor is connected to the fourth node, the first electrode of the fifteenth transistor is connected to the second node, and the second electrode of the fifteenth transistor is connected to the The first voltage terminal is connected to receive the first voltage.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first output noise reduction circuit and a second output noise reduction circuit; the first output noise reduction circuit is connected to the third node and the first output noise reduction circuit.
  • the output terminal is connected, and is configured to reduce noise on the first output terminal under the control of the level of the third node;
  • the second output noise reduction circuit is connected to the fourth node and the second output Terminal connected and configured to reduce noise on the second output terminal under the control of the level of the fourth node.
  • the first output noise reduction circuit when the first output terminal includes a shift output terminal and a scan signal output terminal, the first output noise reduction circuit includes a tenth Six transistors and a seventeenth transistor, the second output noise reduction circuit includes an eighteenth transistor; the gate of the sixteenth transistor is connected to the third node, and the first pole of the sixteenth transistor is connected to the The shift output terminal is connected, the second electrode of the sixteenth transistor is connected to the first voltage terminal to receive the first voltage; the gate of the seventeenth transistor is connected to the third node, and the The first pole of the seventeenth transistor is connected to the scan signal output terminal, the second pole and the third voltage terminal of the seventeenth transistor are connected to receive a third voltage; the gate of the eighteenth transistor is connected to the The fourth node is connected, the first pole of the eighteenth transistor is connected to the second output terminal, and the second pole of the eighteenth transistor is connected to the third voltage terminal to receive the third voltage.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first reset circuit and a second reset circuit; the first reset circuit is connected to the first node and the first reset terminal, and is configured to respond The first reset signal provided at the first reset terminal resets the first node; the second reset circuit is connected to the second node and the first reset terminal, and is configured to respond to the The first reset signal resets the second node.
  • the first reset circuit includes a nineteenth transistor
  • the second reset circuit includes a twentieth transistor
  • the gate of the nineteenth transistor Connected to the first reset terminal to receive the first reset signal
  • the first electrode of the nineteenth transistor is connected to the first node
  • the second electrode of the nineteenth transistor is connected to the first voltage terminal Connected to receive a first voltage
  • the gate of the twentieth transistor is connected to the first reset terminal to receive the first reset signal
  • the first pole of the twentieth transistor is connected to the second node
  • the second electrode of the twentieth transistor is connected to the first voltage terminal to receive the first voltage.
  • the shift register unit provided by at least one embodiment of the present disclosure further includes a first overall reset circuit and a second overall reset circuit; the first overall reset circuit is connected to the first node and the second reset terminal, and Is configured to reset the first node in response to a second reset signal provided by the second reset terminal; the second overall reset circuit is connected to the second node and the second reset terminal, and is configured to In response to the second reset signal, the second node is reset.
  • the first overall reset circuit includes a twenty-first transistor
  • the second overall reset circuit includes a twenty-second transistor
  • the gate of a transistor is connected to the second reset terminal to receive the second reset signal, the first electrode of the twenty-first transistor is connected to the first node, and the second terminal of the twenty-first transistor is connected
  • the second electrode is connected to the first voltage terminal to receive the first voltage
  • the gate of the twenty-second transistor is connected to the second reset terminal to receive the second reset signal
  • the first electrode is connected to the second node
  • the second electrode of the twenty-second transistor is connected to the first voltage terminal to receive the first voltage.
  • At least one embodiment of the present disclosure provides a gate driving circuit including the shift register unit provided in any embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display device including the gate drive circuit provided by any embodiment of the present disclosure and a plurality of sub-pixel units arranged in an array; each shift register in the gate drive circuit The first output terminal and the second output terminal in the unit are respectively electrically connected to sub-pixel units located in different rows.
  • At least one embodiment of the present disclosure provides a driving method of a shift register unit, including a display period and a blanking period for one frame; in the display period, the input circuit responds to the input signal input from the input terminal The first node is charged, the first control circuit charges the second node in response to the input signal and the level of the first node, and the blanking control circuit is at the first node Under the control of the level of the blanking control circuit, the first blanking node of the blanking control circuit is charged; under the control of the level of the first node, the first output circuit outputs at the first output terminal For the first output signal, the second output circuit outputs the second output signal at the second output terminal under the control of the level of the second node; in the blanking phase, the The blanking control circuit charges the first node and the second node under the control of the selection control signal, the first clock signal, and the level of the first blanking node; An output circuit outputs the first output signal at the first output terminal under the control of the level of the first node,
  • FIG. 1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a blanking control circuit provided by at least one embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of yet another shift register unit provided by at least one embodiment of the present disclosure.
  • FIG. 5 is a circuit diagram of a specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 6 is a circuit diagram of another specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 7 is a circuit diagram of another specific implementation example of the shift register unit shown in FIG. 4;
  • FIG. 8 is a schematic diagram of a gate driving circuit provided by at least one embodiment of the present disclosure.
  • FIG. 9 is a signal timing diagram corresponding to the operation of the gate driving circuit shown in FIG. 8 provided by at least one embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of a display device provided by at least one embodiment of the present disclosure.
  • the gate driving circuit composed of shift register units needs to provide driving signals for scanning transistors and sensing transistors to the sub-pixel units in the display panel, for example, for the display period of one frame.
  • a sensing driving signal for the sensing transistor is provided in a blanking period of one frame.
  • the sensing driving signal output by the gate driving circuit is sequentially scanned row by row.
  • the sensing driving signal for the sub-pixel unit of the first row in the display panel is output during the blanking period of the first frame.
  • Detect driving signal output the sensing driving signal for the second row of sub-pixel units in the display panel during the blanking period of the second frame, and so on, output the frequency of the sensing driving signal corresponding to one row of sub-pixel units in each frame Line-by-line sequential output, which completes the line-by-line sequential compensation of the display panel.
  • the gate driving circuit drives multiple rows of sub-pixel units in a display panel, if external compensation is to be achieved, the gate driving circuit is required not only to output scan driving signals for the display period, but also The sensing driving signal for the blanking period is output.
  • a shift register unit which includes an input circuit, a first control circuit, a blanking control circuit, a first output circuit, and a second output circuit.
  • the input circuit is connected to the input terminal and is configured to control the level of the first node in response to the input signal input from the input terminal;
  • the first control circuit is connected to the input terminal, the first node, and the second node, and is configured to respond to The input signal input from the input terminal and the level of the first node control the level of the second node;
  • the blanking control circuit is connected to the first node and the second node, and is configured to select the control signal, the first clock signal And the level of the first node, the level of the first node and the level of the second node are controlled;
  • the first output circuit includes a first output terminal, and the first output circuit is configured to Under the control of the level, the first output signal is output at the first output terminal;
  • the second output circuit includes a second output terminal, and the second output circuit is
  • Some embodiments of the present disclosure also provide a gate driving circuit, a display device, and a driving method corresponding to the above-mentioned shift register unit.
  • the shift register unit provided by the above-mentioned embodiment of the present disclosure realizes the control of the level of the first node and the level of the second node by sharing a blanking control circuit, so that the level of the first node and the level of the second node Under the control of the shift register unit, the function of outputting two rows of driving signals through the first shift register unit is realized, which can greatly reduce the number of transistors and the number of capacitors, reduce the frame size of the display device using the shift register unit, reduce costs, and improve The PPI of the display device.
  • random compensation refers to an external compensation method that is different from line-by-line sequential compensation.
  • the random output corresponding to any line in the display panel.
  • the definition of "one frame”, “every frame” or “a certain frame” includes sequential display periods and blanking periods, for example, in the display period
  • the drive circuit outputs a drive signal, which can drive multiple rows of sub-pixel units in the display panel from the first row to the last row to complete the scanning and display of a complete image.
  • the gate drive circuit outputs the drive signal during the blanking period.
  • the driving signal can be used to drive the sensing transistors in a certain row of sub-pixel units in the display panel to complete the external compensation of the row of sub-pixel units.
  • FIG. 1 is a schematic diagram of a shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 10 may include an input circuit 110, a first control circuit 120, a blanking control circuit 130, a first output circuit 141, and a second output circuit 142.
  • a gate driving circuit By cascading a plurality of the shift register units 10, a gate driving circuit can be obtained.
  • the gate driving circuit is used to drive the display panel and sequentially provide scanning signals for the plurality of gate lines of the display panel to display one frame on the display panel. The period of the screen is progressive or interlaced.
  • the input circuit 110 is connected to the input terminal STU, and is configured to control the level of the first node Q1 in response to an input signal input from the input terminal STU.
  • the input circuit 110 is connected to the input terminal STU, the second voltage terminal VDD, and the first node Q1, and is configured to be turned on under the control of the input signal provided by the input terminal STU, so that the second voltage terminal VDD and The first node Q1 is connected, so that the second voltage provided by the second voltage terminal VDD is input to the first node Q1, and the potential of the first node Q1 is charged to the working potential (for example, the transistor connected to the first node Q1 can be Turn-on potential).
  • the input circuit 110 may be connected to the input terminal STU and the first node Q1, and configured to be turned on under the control of the input signal provided by the input terminal STU, so that the input terminal STU is connected to the first node Q1,
  • the input signal provided by the input terminal STU is input to the first node Q1, and the potential of the first node Q1 is pulled up to the working potential.
  • the second voltage terminal VDD can also be replaced by a clock signal terminal that provides a clock signal, as long as it is satisfied that the first node Q1 can be charged at the corresponding stage, which is not limited in the embodiment of the present disclosure.
  • the first control circuit 120 is connected to the input terminal STU, the first node Q1, and the second node Q2, and is configured to respond to the input signal input from the input terminal STU and the level of the first node Q1, to the level of the second node Q2 Take control.
  • the first control circuit 120 is connected to the input terminal STU, the first node Q1 and the second node Q2, and is configured to be turned on under the control of the input signal provided by the input terminal STU, so that the second node Q2 and The first node Q1 is connected so that the potential of the second node Q2 is consistent with the potential of the first node Q1, that is, the potential of the second node Q2 is charged to the working potential through the first node Q1.
  • the blanking control circuit 130 is connected to the first node Q1 and the second node Q2, and is configured to control the level of the first node Q1 and the first node Q1 under the control of the selection control signal, the first clock signal, and the level of the first node Q1.
  • the level of the second node Q2 is controlled.
  • the blanking control circuit 130 is connected to the selection control terminal OE, the first clock signal terminal CLKA, the first voltage terminal VGL1, the first node Q1, and the second node Q2, and is configured to be at the selection control terminal OE.
  • the level of the first node Q1 is stored under the control of the provided selection control signal, and in the blanking period of one frame, the first clock signal provided at the first clock signal terminal CLKA and the level of the first node Q1 stored Under control, the first clock signal provided by the first clock signal terminal CLKA is provided to the first node Q1 and the second node Q2, so that the potential of the first node Q1 and the potential of the second node Q2 are charged to the working potential.
  • the level of the first node Q1 and the level of the second node Q2 can be controlled at the same time through the common blanking control circuit 130, and there is no need to separately control through separate circuits, thereby saving
  • the number of transistors in the shift register unit reduces the frame size of the display device using the shift register unit and reduces the cost;
  • the input terminal of the blanking control circuit 130 is connected to the first node Q1 instead of The blanking input terminal for controlling the blanking period, that is, the display period and the blanking period can share one input circuit 110, thereby greatly simplifying the circuit design of the shift register unit.
  • the first output circuit 141 includes a first output terminal OUT1, and the first output circuit 141 is configured to output a first output signal at the first output terminal OUT1 under the control of the level of the first node Q1.
  • the first output circuit 141 is connected to the first node Q1, the first output terminal OUT1, and the second clock signal terminal CLKD, and is configured to be turned on under the control of the level of the first node Q1, so that the The second clock signal provided by the second clock signal terminal CLKD is output as the first output signal to the first output terminal OUT1.
  • the first output terminal OUT1 includes a shift output terminal and at least one scan signal output terminal, thereby outputting an output signal such as a second clock signal provided by the second clock signal terminal CLKD to the shift output terminal and Scan the signal output terminal to improve the driving capability of the shift register unit 10.
  • at least one scan signal output terminal includes one scan signal output terminal GOUT1.
  • the shift output terminal CR is used to provide an input signal for the next stage shift register unit 10 and a reset signal for the previous stage shift register unit, and the scan signal output terminal GOUT1 is used for the pixels of a row of pixel units in the display panel.
  • the circuit provides driving signals (for example, scanning driving signals or sensing driving signals).
  • the shift output terminal CR and the scan signal output terminal GOUT1 may output the same output signal, or may output different output signals. It should be noted that in other examples, when multiple scan signal output terminals are included, each scan signal output terminal can also output different output signals.
  • the specific settings depend on actual conditions, and the embodiments of the present disclosure do not make this limit.
  • some shift register units 10 can be connected to a trigger signal line to receive the input signal STU provided by the trigger signal line; or, some shift register units 10 (for example, In addition to the shift register units of the previous stages and the shift register units of each stage, the shift signal CR output by the shift register units 10 of other stages can also be received as the input signal STU.
  • the shift output terminal can only output the first output signal during the display period of one frame to meet the cascade needs (of course, it can also be output during the blanking period, as long as the blanking period is not caused.
  • the scan signal output terminal needs to output the scan drive signal in the display period of one frame, and also needs to blank out for one frame.
  • the sensing driving signal is output in the period. Therefore, in order to avoid the phenomenon that the sensing driving signal output in the blanking period is output at the shift output terminal and causing display disorder, a third clock signal terminal CLKE1 (as shown in FIG. 3) may also be included. .
  • the third clock signal terminal CLKE1 controls the output of the scan signal output terminal GOUT1
  • the second clock signal terminal CLKD controls the output of the shift output terminal CR, that is, the output of the scan signal output terminal GOUT1 and the output of the shift output terminal CR.
  • the signals are provided through different clock signal terminals to prevent the sensing drive signal output during the blanking period from being output at the shift output terminal.
  • the waveform of the third clock signal provided by the third clock signal terminal CLKE1 and the waveform of the second clock signal provided by the second clock signal terminal CLKD are exactly the same in the display period, and may be the same or different in the blanking period.
  • the second output circuit 142 includes a second output terminal GOUT2, and the second output circuit 142 is configured to output a second output signal at the second output terminal GOUT2 under the control of the level of the second node Q2.
  • the second output circuit 142 is connected to the second node Q2, the second output terminal GOUT2, and the fourth clock signal terminal CLKE2, and is configured to be turned on under the control of the level of the second node Q2, so that the first The fourth clock signal provided by the four-clock signal terminal CLKE2 is output as the second output signal to the second output terminal GOUT2.
  • the scan signal output terminal GOUT1 and the second output terminal GOUT2 in the first output terminal OUT1 are connected to different gate lines.
  • the scanning signal output terminal GOUT1 of the first output terminal OUT1 is connected to the gate line of the Nth (N is an integer greater than 1) row
  • the second output terminal GPUT2 is connected to the gate line of the N+1th row.
  • the first output signal is used as a scan driving signal or a sensing driving signal transmitted by the gate line of the Nth row to drive the pixel circuit connected to the gate line of the Nth row.
  • the second output signal is used as a scan driving signal or a sensing driving signal transmitted by the gate line of the N+1th row to drive the pixel circuit connected to the gate line of the N+1th row. Therefore, the mobile device provided by the embodiment of the present disclosure
  • the bit register unit can output two rows of driving signals.
  • the shift register unit provided by the above-mentioned embodiment of the present disclosure realizes the control of the level of the first node Q1 and the level of the second node Q2 by sharing a blanking control circuit, so as to realize the output of two rows through the one-stage shift register unit
  • the function of the driving signal greatly reduces the number of transistors and the number of capacitors, reduces the frame size of the display device using the shift register unit, reduces the cost, and improves the PPI of the display device.
  • Fig. 2 is a schematic diagram of an exemplary blanking control circuit provided by at least one embodiment of the present disclosure.
  • the blanking control circuit 130 includes a first control sub-circuit 131, a second control sub-circuit 132 and a third control sub-circuit 133.
  • the first control sub-circuit 131 is connected to the first node Q1 and the first blanking node H1, and is configured to control the level of the first blanking node H1 under the control of the selection control signal and the level of the first node Q1 control.
  • the first control sub-circuit 131 is connected to the first node Q1, the selection control terminal OE, the first blanking node H1, and the first voltage terminal VGL1, and is configured to conduct under the control of the selection control signal provided by the selection control terminal OE.
  • the first node Q1 is connected to the first blanking node H1, so that the level of the first node Q1 is written into the first blanking node H1.
  • the second control sub-circuit 132 is connected to the first blanking node H1 and the second blanking node H2, and is configured to control the level of the second blanking node H2 under the control of the level of the first blanking node H1. control.
  • the second control sub-circuit 132 is connected to the first clock signal terminal CLKA, the first blanking node H1 and the second blanking node H2, and is configured to be turned on under the control of the level of the first blanking node H1,
  • the first clock signal terminal CLKA is connected to the second blanking node H2, so that the first clock signal is written into the second blanking node H2.
  • the third control sub-circuit 133 is connected to the second blanking node H2, the first node Q1 and the second node Q2, and is configured to control the levels of the first node Q1 and the second node Q2 under the control of the first clock signal. Take control.
  • the third control sub-circuit 133 is connected to the first clock signal terminal CLKA, the second blanking node H2, the first node Q1, and the second node Q2, and is configured as the first clock signal provided at the first clock signal terminal CLKA It is turned on under the control of, so that the first node Q1 and the second node Q2 are connected to the second blanking node H2, thereby writing the level of the second blanking node H2 to the first node Q1 and the second node Q2.
  • the third control sub-circuit 133 can simultaneously control the first node Q1 and the second node Q2 during the blanking period.
  • Level realizes the sharing of the blanking control circuit in the shift register unit driving the adjacent two rows of pixel circuits, thereby reducing the number of transistors in the shift register unit, and is beneficial to reducing the display device using the shift register unit Border size.
  • FIG. 3 is a schematic diagram of another shift register unit provided by at least one embodiment of the present disclosure.
  • the shift register unit 10 further includes a second control circuit 151 and a third control circuit 152; in other examples, the shift register unit 10 further includes a A node noise reduction circuit 161 and a second node noise reduction circuit 162; in other examples, the shift register unit 10 further includes a first output noise reduction circuit 171 and a second output noise reduction circuit 172; in other examples
  • the shift register unit 10 further includes a first reset circuit 181 and a second reset circuit 182. It should be noted that the other circuit structures of the shift register unit 10 shown in FIG. 3 are basically the same as those of the shift register unit 10 shown in FIG.
  • the second control circuit 151 is connected to the first node Q1 and the third node Q3, and is configured to control the level of the third node Q3 under the control of the level of the first node Q1.
  • the second control circuit 151 is configured to receive the second voltage VDD and the first voltage VGL1.
  • the second control circuit 151 may pull the third node Q3 to a low level by using the first voltage VGL1 at a low level.
  • the second control circuit 151 may use the second voltage VDD (for example, a high level) to charge the third node Q3 to pull the third node Q3 up to high Level.
  • the third control circuit 152 is connected to the second node Q2 and the fourth node Q4, and is configured to control the level of the fourth node Q4 under the control of the level of the second node Q2.
  • the third control circuit 152 is configured to receive the second voltage VDD and the first voltage VGL1.
  • the third control circuit 152 may pull the fourth node Q4 to a low level by using the first voltage VGL1 of a low level.
  • the third control circuit 152 may use the second voltage VDD (for example, a high level) to charge the fourth node Q4 to pull the fourth node Q4 up to high Level.
  • the first node noise reduction circuit 161 is connected to the first node Q1 and the third node Q3, and is configured to reduce noise on the first node Q1 under the control of the level of the third node Q3.
  • the first node noise reduction circuit 161 when the first node noise reduction circuit 161 is connected to the first voltage terminal VGL1, the first node Q1, and the third node Q3 and is configured to be turned on under the control of the level of the third node Q3,
  • the first node Q1 is connected to the first voltage terminal VGL1, so that the first node Q1 can be pulled down (for example, discharged) by the first voltage VGL1 to achieve noise reduction.
  • the second node noise reduction circuit 162 is connected to the second node Q2 and the fourth node Q4, and is configured to perform noise reduction on the second node Q2 under the control of the level of the fourth node Q4.
  • the second node noise reduction circuit 162 when the second node noise reduction circuit 162 is connected to the first voltage terminal VGL1, the second node Q2, and the fourth node Q4, and is configured to be turned on under the control of the level of the fourth node Q4,
  • the second node Q2 is connected to the first voltage terminal VGL1, so that the first voltage VGL1 can be used to pull down (for example, discharge) the second node Q2 to achieve noise reduction.
  • the first output noise reduction circuit 171 is connected to the third node Q3 and the first output terminal OUT1 (for example, including the shift output terminal CR and the scan signal output terminal GOUT1), and is configured to be controlled by the level of the third node Q3 , Reduce noise on the first output terminal OUT1.
  • the first output noise reduction circuit 171 is connected to the third voltage terminal VGL2, the third node Q3, and the first output terminal OUT1, and is configured to be turned on under the control of the level of the third node Q3.
  • the first output terminal OUT1 and the third voltage terminal VGL2 are connected, so that the third voltage VGL2 can be used to pull down (for example, discharge) the first output terminal OUT1 to achieve noise reduction.
  • the second output noise reduction circuit 172 is connected to the fourth node Q4 and the second output terminal GOUT2, and is configured to reduce noise on the second output terminal GOUT2 under the control of the level of the fourth node Q4.
  • the second output noise reduction circuit 172 is connected to the third voltage terminal VGL2, the fourth node Q4, and the second output terminal GOUT2, and is configured to be turned on under the control of the level of the fourth node Q4.
  • the second output terminal GOUT2 and the third voltage terminal VGL2 are connected, so that the second output terminal GOUT2 can be pulled down (for example, discharged) by the third voltage VGL2, so as to achieve noise reduction.
  • the first voltage VGL1 can also be used to pull-down reset the first output terminal OUT1 and the second output terminal GOUT2, which is not limited in the present disclosure.
  • the third voltage VGL2 is, for example, a low level. The following embodiments are the same as this, and will not be repeated. In the embodiment of the present disclosure, the third voltage VGL2 may be the same as or different from the first voltage VGL1.
  • the first reset circuit 181 is connected to the first node Q1 and the first reset terminal STD, and is configured to reset the first node Q1 in response to the first reset signal provided by the first reset terminal STD. For example, in some examples, in the display period of one frame, the first reset circuit 181 is turned on in response to the first reset signal STD, so that the first node Q1 can be pulled down and reset by the first voltage VGL1. For example, when a plurality of shift register units 10 are cascaded to form a gate driving circuit, the shift register unit 10 of a certain stage may receive the shift signal CR output by the shift register unit 10 of the other stage as the display reset signal STD.
  • the second reset circuit 182 is connected to the second node Q2 and the first reset terminal STD, and is configured to reset the second node Q2 in response to the first reset signal.
  • the working principle of the second reset circuit 182 is similar to the working principle of the first reset circuit 181, and will not be repeated here.
  • the shift register unit 10 further includes a first overall reset circuit 191 and a second overall reset circuit 192. It should be noted that other circuit structures of the shift register unit 10 shown in FIG. 4 are basically the same as those of the shift register unit 10 shown in FIG. 3, and the repetitions will not be repeated.
  • the first overall reset circuit 191 is connected to the first node Q1 and the second reset terminal TRST, and is configured to reset the first node Q1 in response to the second reset signal provided by the second reset terminal TRST.
  • the first total reset circuit 191 in the shift register units 10 of each stage Turning on in response to the second reset signal TRST, so that the fourth voltage terminal VGL1 is connected to the first node Q1, so that the low-level fourth voltage VGL1 can be used to pull down and reset the first node Q1, thereby realizing gate driving Global reset of circuit 20.
  • the second total reset circuit 192 is connected to the second node Q2 and the second reset terminal TRST, and is configured to reset the second node Q2 in response to the second reset signal.
  • the working principle of the second overall reset circuit 192 is similar to the working principle of the first overall reset circuit 191, and will not be repeated here.
  • the shift register unit 10 shown in FIG. 4 may be implemented as the circuit structure shown in FIG. 5.
  • the shift register unit 10 includes: a first transistor M1 to a twenty-second transistor M22, a first capacitor C1, a second capacitor C2, and a third capacitor C3.
  • the transistors shown in FIG. 5 are all N-type transistors for illustration, and the embodiments of the present disclosure do not limit this.
  • at least part of the transistors in the shift register unit 10 may also be P-type transistors. .
  • the input circuit 110 includes an eighth transistor M8.
  • the gate of the eighth transistor M8 is connected to the input terminal STU to receive the input signal
  • the first electrode of the eighth transistor M8 is connected to the second voltage terminal VDD to receive the second voltage
  • the second electrode of the eighth transistor M8 is connected to the first node Q1 connection.
  • the gate and the first electrode of the eighth transistor M8 are electrically connected to each other and are configured to receive the input signal STU, so that when the input signal STU is at a high level, the high voltage
  • the flat input signal STU charges the first node Q1.
  • the first output circuit 141 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.
  • the gate of the fifth transistor M5 is connected to the first node Q1, and the first electrode of the fifth transistor M5 is connected to the second clock signal terminal CLKD to receive the second clock signal as the first output signal.
  • the second terminal of the fifth transistor M5 The pole is connected to the shift output terminal CR.
  • the gate of the sixth transistor M6 is connected to the first node Q1, the first pole of the sixth transistor M6 is connected to the third clock signal terminal CLKE1 to receive the third clock signal as the first output signal, and the second terminal of the sixth transistor M6 The pole is connected to the scan signal output terminal GOUT1.
  • the second clock signal CLKD and the third clock signal CLKE1 have the same timing in the display period.
  • the timing of the third clock signal and the second clock signal in the blanking period may be the same or different, as long as the normal display of the display device is satisfied, which is not limited by the embodiment of the present disclosure.
  • the first pole of the sixth transistor M6 may also be connected to the second clock signal terminal CLKD to receive the second clock signal and use it as the first output signal for the pixel circuit. Scan driver. It should be noted that the first pole of the fifth transistor M5 and the first pole of the sixth transistor M6 are respectively connected to different clock signal terminals, which can avoid shifting the output terminal CR when the sensing scan signal needs to be output during the blanking period. The high level is also output, so that the first node Q1 and the second node Q2 of the next-stage shift register unit connected to the first node Q1 and the second node Q2 are charged to a high level, causing false output of the display panel.
  • the first electrode of the second capacitor C2 is connected to the first node Q1, and the second electrode of the second capacitor C2 is connected to the second electrode of the sixth transistor M6 (or the fifth transistor M5).
  • the second output circuit 142 includes a seventh transistor M7 and a third capacitor C3.
  • the gate of the seventh transistor M7 is connected to the second node Q2, and the first electrode of the seventh transistor M7 is connected to the fourth clock signal terminal CLKE2 to receive the fourth clock signal as the second output signal, and the second electrode of the seventh transistor M7 Connected to the second output terminal GOUT2.
  • the first pole of the third capacitor C3 is connected to the second node Q2, and the second pole of the third capacitor C3 is connected to the second output terminal GOUT2.
  • the first control circuit 120 includes a ninth transistor M9.
  • the gate of the ninth transistor M9 is connected to the input terminal STU to receive the input signal, the first electrode of the ninth transistor M9 is connected to the first node Q1, and the second electrode of the ninth transistor M9 is connected to the second node Q2.
  • the first control sub-circuit 131 includes a first transistor M1 and a first capacitor C1
  • the second control sub-circuit 132 includes a second transistor M2
  • the third control sub-circuit 133 includes a third transistor M3 and a fourth transistor M4.
  • the gate of the first transistor M1 is connected to the selection control terminal OE to receive the selection control signal, the first electrode of the first transistor M1 is connected to the first node Q1, and the second electrode of the first transistor M1 is connected to the first blanking node H1 .
  • the first pole of the first capacitor C1 is connected to the first blanking node H1, and the second pole of the first capacitor C1 is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the gate of the second transistor M2 is connected to the first blanking node H1, the first electrode of the second transistor M2 is connected to the first clock signal terminal CLKA to receive the first clock signal, and the second electrode of the second transistor M2 is connected to the second The blanking node H2 is connected.
  • the gate of the third transistor M3 is connected to the first clock signal terminal CLKA to receive the first clock signal, the first electrode of the third transistor M3 is connected to the second blanking node H2, and the second electrode of the third transistor M3 is connected to the first Node Q2 is connected.
  • the gate of the fourth transistor M4 is connected to the first clock signal terminal CLKA to receive the first clock signal, the first electrode of the fourth transistor M4 is connected to the second blanking node H2, and the second electrode of the fourth transistor M4 is connected to the second Node Q2 is connected.
  • the second control circuit 151 includes a tenth transistor M10 and an eleventh transistor M11
  • the third control circuit 152 includes a twelfth transistor M12 and a thirteenth transistor M1.
  • the gate of the tenth transistor M10 is connected to the first electrode and connected to the second voltage terminal VDD to receive the second voltage, and the second electrode of the tenth transistor M10 is connected to the third node Q3.
  • the gate of the eleventh transistor M11 is connected to the first node Q1, the first electrode of the eleventh transistor M11 is connected to the third node Q3, and the second electrode of the eleventh transistor M11 is connected to the first voltage terminal VGL1 to receive the One voltage.
  • the gate of the twelfth transistor M12 is connected to the first electrode and connected to the second voltage terminal VDD to receive the second voltage.
  • the second electrode of the twelfth transistor M12 is connected to the fourth node Q4;
  • the gate is connected to the second node Q2, the first electrode of the thirteenth transistor M13 is connected to the fourth node Q4, and the second electrode of the thirteenth transistor M13 is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the first node noise reduction circuit 161 includes a fourteenth transistor M14
  • the second node noise reduction circuit 162 includes a fifteenth transistor M15.
  • the gate of the fourteenth transistor M14 is connected to the third node Q3, the first electrode of the fourteenth transistor M14 is connected to the first node Q1, and the second electrode of the fourteenth transistor M14 is connected to the first voltage terminal VGL1 to receive the One voltage.
  • the gate of the fifteenth transistor M15 is connected to the fourth node Q4, the first electrode of the fifteenth transistor M15 is connected to the second node Q2, and the second electrode of the fifteenth transistor M15 is connected to the first voltage terminal VGL1 to receive Mentioned first voltage.
  • the first output noise reduction circuit 171 includes a sixteenth transistor M16 and a seventeenth transistor M17, and the second output noise reduction circuit The circuit 172 includes an eighteenth transistor M18.
  • the gate of the sixteenth transistor M16 is connected to the third node Q3, the first electrode of the sixteenth transistor M16 is connected to the shift output terminal CR, and the second electrode of the sixteenth transistor M16 is connected to the first voltage terminal VGL1 to receive First voltage.
  • the gate of the seventeenth transistor M17 is connected to the third node Q3, the first electrode of the seventeenth transistor M17 is connected to the scan signal output terminal GOUT1, and the second electrode of the seventeenth transistor M17 is connected to the third voltage terminal VGL2 to receive The third voltage.
  • the gate of the eighteenth transistor M18 is connected to the fourth node Q4, the first pole of the eighteenth transistor M18 is connected to the second output terminal GOUT2, and the second pole of the eighteenth transistor M18 is connected to the third voltage terminal VGL2 to receive The third voltage.
  • the first reset circuit 181 includes a nineteenth transistor M19
  • the second reset circuit 182 includes a twentieth transistor M20.
  • the gate of the nineteenth transistor M19 is connected to the first reset terminal STD to receive the first reset signal
  • the first electrode of the nineteenth transistor M19 is connected to the first node Q1
  • the second electrode of the nineteenth transistor M19 is connected to the first node Q1.
  • the voltage terminal VGL1 is connected to receive the first voltage.
  • the gate of the twentieth transistor M20 is connected to the first reset terminal STD to receive the first reset signal
  • the first electrode of the twentieth transistor M20 is connected to the second node Q2
  • the second electrode of the twentieth transistor M20 is connected to the first
  • the voltage terminal VGL1 is connected to receive the first voltage.
  • the first overall reset circuit 191 includes a twenty-first transistor M21
  • the second overall reset circuit 192 includes a twenty-second transistor M22.
  • the gate of the twenty-first transistor M21 is connected to the second reset terminal TRST to receive the second reset signal
  • the first pole of the twenty-first transistor M21 is connected to the first node Q1
  • the second pole of the twenty-first transistor M21 It is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the gate of the twenty-second transistor M22 is connected to the second reset terminal TRST to receive the second reset signal
  • the first pole of the twenty-second transistor M22 is connected to the second node Q2
  • the second terminal of the twenty-second transistor M22 The electrode is connected to the first voltage terminal VGL1 to receive the first voltage.
  • the first capacitor C1 can be used to maintain the potential at the first blanking node H1
  • the second capacitor C2 can be used to maintain the potential at the first node Q1.
  • the third capacitor C3 is used to maintain the potential at the second node Q2.
  • the first capacitor C1, the second capacitor C2, and the third capacitor C3 can be capacitive devices manufactured by a process, for example, a capacitor device can be realized by making a special capacitor electrode, and each electrode of the capacitor can be made through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • a capacitor device can be realized by making a special capacitor electrode, and each electrode of the capacitor can be made through a metal layer, a semiconductor layer (for example, Doped polysilicon), etc., or in some examples, by designing circuit wiring parameters so that the first capacitor C1, the second capacitor C2, and the third capacitor C3 can also be realized by the parasitic capacitances between the various devices.
  • connection method of the first capacitor C1, the second capacitor C2 and the third capacitor C3 is not limited to the method described above, and can also be other applicable connection methods, as long as it can be stored and written to the first blanking node H1 and the first node The levels of Q1 and the second node Q2 are sufficient.
  • VGL1 represents the first voltage terminal and the first voltage
  • VDD represents the second voltage terminal and the second voltage
  • VGL2 represents the third voltage terminal and the first voltage.
  • the first voltage VGL1 and the third voltage VGL2 are, for example, a low level
  • the second voltage VDD is, for example, a high level.
  • the second voltage VDD is greater than the first voltage VGL1 and the third voltage VGL2.
  • the high level and the low level are relative.
  • the high level indicates a higher voltage range (for example, the high level can be 5V, 10V or other suitable voltages), and multiple high levels can be the same or different.
  • the low level represents a lower voltage range (for example, the low level may adopt 0V, -5V, -10V or other suitable voltages), and multiple low levels may be the same or different.
  • the minimum value of the high level is greater than the maximum value of the low level.
  • controlling the level of a node includes charging the node to increase the level of the node, or the node Discharge to pull down the level of this node.
  • charging the node means charging the capacitor electrically connected to the node; similarly, discharging the node means charging the capacitor electrically connected to the node. Discharge; the high or low level of the node can be maintained through the capacitor.
  • GOUT1 represents both the scan signal output terminal and the first output signal
  • GOUT2 represents both the second output terminal and the second output signal
  • CLKA represents the first clock signal terminal and the first clock
  • Signal, CLKD represents the second clock signal terminal and the second clock signal
  • CLKE1 represents the third clock signal terminal and the third clock signal
  • CLKE2 represents the fourth clock signal terminal and the fourth clock signal
  • pulse-up means charging a node or an electrode of a transistor so that the level of the node or the electrode is absolutely The value increases to achieve the operation of the corresponding transistor (for example, turn-on); “pull-down” means to discharge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby achieving the corresponding Operation of the transistor (for example, turning off).
  • pulse-up means discharging a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is reduced, thereby realizing the corresponding transistor Operation (for example, turn on);
  • pulse down means to charge a node or an electrode of a transistor, so that the absolute value of the level of the node or the electrode is increased, thereby realizing the operation of the corresponding transistor (for example, turning off) .
  • the first node Q1, the second node Q2, the third node Q3, the fourth node Q4, the first blanking node H1 and the second blanking node H2 are not Represents the actual components, but represents the junction of related electrical connections in the circuit diagram.
  • the transistors used in the embodiments of the present disclosure may all be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • thin film transistors are used as examples for description.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages) );
  • the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages)
  • the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable Voltage).
  • the transistors in the embodiments of the present disclosure are all described by taking an N-type transistor as an example.
  • the first electrode of the transistor is the drain and the second electrode is the source.
  • the present disclosure includes but is not limited to this.
  • one or more transistors in the shift register unit 10 provided by the embodiment of the present disclosure may also be P-type transistors.
  • the first electrode of the transistor is the source and the second electrode is the drain.
  • the poles of the transistors of a certain type are connected correspondingly with reference to the poles of the corresponding transistors in the embodiments of the present disclosure, and the corresponding voltage terminals provide the corresponding high voltage or low voltage.
  • indium gallium zinc oxide Indium Gallium Zinc Oxide, IGZO
  • crystalline silicon can effectively reduce the size of the transistor and prevent leakage current.
  • At least one embodiment of the present disclosure also provides a gate driving circuit 20.
  • the gate driving circuit 20 includes a plurality of cascaded shift register units 10, of which any one or more shift registers
  • the unit 10 may adopt the structure of the shift register unit 10 provided in any embodiment of the present disclosure or a variant thereof.
  • the shift register unit 10 adopts the structure of the shift register unit 10 shown in FIG. 7 as an example for description.
  • A1, A2, A3, and A4 in FIG. 8 represent four shift register units 10 connected in cascade.
  • each shift register unit 21 includes a scan signal output terminal GOUT1, a second output terminal GOUT2, and a shift output terminal CR to respectively output the first output signal (including the shift signal CR and the scan output Signal GOUT1) and the second output signal GOUT2.
  • the scan output signal GOUT1 is referred to as the first output signal below.
  • the first output signal GOUT1 and the second output signal GOUT2 can respectively drive one row of sub-pixel units in the display panel 10.
  • the scan signal output terminal GOUT1 ⁇ 1> and the second output terminal GOUT2 ⁇ 2> in the first-stage shift register unit A1 can respectively drive the first row of sub-pixel units and the first row of the display panel 10 through the gate lines connected to them.
  • 2 rows of sub-pixel units, the scan signal output terminal GOUT1 ⁇ 3> and the second output terminal GOUT2 ⁇ 4> in the second-stage shift register unit A2 can drive the third row sub-pixels of the display panel 10 through the gate lines connected to them.
  • CR ⁇ 1> represents the shift output terminal of the first stage shift register unit
  • CR ⁇ 3> represents the shift output terminal of the second stage shift register unit
  • CR ⁇ 5> represents the shift output terminal of the 3rd stage shift register unit
  • CR ⁇ 7> represents the shift output terminal of the 4th stage shift register unit, and so on.
  • the gate driving circuit 20 includes a first sub-clock signal line CLKD_1, a second sub-clock signal line CLKD_3, a third sub-clock signal line CLKD_5, and a fourth sub-clock signal line CLKD_7.
  • the second clock signal terminal CLKD in the 4k-3th (k is an integer greater than zero) shift register unit is connected to the first sub-clock signal line CLKD_1 to receive the second clock signal of the 4k-3th shift register unit.
  • the second clock signal terminal CLKD in the 4k-2th stage shift register unit is connected to the second sub-clock signal line CLKD_3 to receive the second clock signal CLKD of the 4k-2th stage shift register unit; 4k
  • the second clock signal terminal CLKD in the -1 stage shift register unit is connected to the third sub-clock signal line CLKD_5 to receive the second clock signal CLKD of the 4k-1 stage shift register unit; in the 4k stage shift register unit
  • the second clock signal terminal CLKD is connected to the fourth sub-clock signal line CLKD_7 to receive the second clock signal CLKD of the 4k-th stage shift register unit.
  • the shift register unit 10 when the shift register unit 10 is cascaded, it is only necessary to provide the second clock signal to the second clock signal terminal CLKD in each stage of the shift register unit 10, and the second clock signal can be used as a shifter.
  • the bit signal CR is output to complete the scan shift.
  • the gate driving circuit 20 further includes a fifth sub-clock signal line CLKE_1 to a twelfth sub-clock signal line CLKE_8.
  • the third clock signal terminal CLKE1 in the 4k-3th stage shift register unit is connected to the fifth sub-clock signal line CLKE_1 to receive the third clock signal CLKE1 of the 4k-3th stage shift register unit, and the 4k-3th stage shift
  • the fourth clock signal terminal CLKE2 in the bit register unit is connected to the sixth sub-clock signal line CLKE_2 to receive the fourth clock signal CLKE2 of the 4k-3th stage shift register unit.
  • the third clock signal terminal CLKE1 in the 4k-2 stage shift register unit is connected to the seventh sub-clock signal line CLKE_3 to receive the third clock signal CLKE1 of the 4k-2 stage shift register unit, and the 4k-2 stage shift register unit
  • the fourth clock signal terminal CLKE2 in the bit register unit is connected to the eighth sub-clock signal line CLKE_4 to receive the fourth clock signal CLKE2 of the 4k-2th stage shift register unit.
  • the third clock signal terminal CLKE1 in the 4k-1 stage shift register unit is connected to the ninth sub-clock signal line CLKE_5 to receive the third clock signal CLKE1 of the 4k-1 stage shift register unit.
  • the 4k-1 stage shift register unit The fourth clock signal terminal CLKE2 in the bit register unit is connected to the tenth sub-clock signal line CLKE_6 to receive the fourth clock signal CLKE2 of the 4k-1th stage shift register unit.
  • the third clock signal terminal CLKE1 in the 4k-stage shift register unit is connected to the eleventh sub-clock signal line CLKE_7 to receive the third clock signal CLKE1 of the 4k-stage shift register unit.
  • the fourth clock signal terminal CLKE2 is connected to the twelfth sub-clock signal line CLKE_8 to receive the fourth clock signal CLKE2 of the 4k-th stage shift register unit.
  • the gate driving circuit 20 provided by the embodiment of the present disclosure can use a clock signal of 8CLK, so that the waveforms of the driving signals output by the gate driving circuit 20 can overlap, for example, the precharge time of each row of sub-pixel units can be increased. Therefore, the gate drive circuit 20 can be applied to high-frequency scanning display. have to be aware of is.
  • the number of signal lines may also be 10, 12, 14, or more, which is not limited in the embodiment of the present disclosure.
  • the trigger signal line STU_1 is connected to the input terminals STU of the first-stage shift register unit A1 and the second-stage shift register unit A2 to provide the input signal STU, and the total reset signal line TRST_1 It is connected to the second reset terminal TRST of the shift register unit 10 of each stage to provide a global reset signal TRST.
  • the selection control signal line OE_1 is connected to the selection control terminal OE of the shift register unit 10 of each stage to receive the selection control signal, and the thirteenth sub-clock signal line CLKA_1 is connected to the first clock signal terminal CLKA of the shift register unit 10 of each stage to Receive the first clock signal.
  • the input terminals STU of the other stages of the shift register unit 10 and the upper stage shift register unit 10 separated from it by one stage The shift output terminal CR is connected to receive the shift signal CR as the input signal STU.
  • the first reset terminal STD in the shift register units 10 of the remaining stages is connected to the shift output terminal CR of the lower stage shift register unit 10 separated by one stage to receive shift signals CR serves as the first reset signal STD.
  • cascading relationship shown in FIG. 8 is only an example. According to the description of the present disclosure, other cascading manners may also be adopted according to actual conditions, and the embodiments of the present disclosure do not limit this.
  • the bit register unit A4 also includes a plurality of shift register units 10 that are sequentially cascaded.
  • the embodiment of the present disclosure does not limit this, and the cascading method can refer to the cascading method described above, which will not be repeated here.
  • the gate driving circuit 20 further includes a plurality of voltage lines to provide a plurality of voltage signals to the shift register units of each stage, for example, including relatively high-level signals VDD and low-level signals VGL1, VGL2, etc.
  • the gate driving circuit 20 when used to drive a display panel, the gate driving circuit 20 can be arranged on one side of the display panel.
  • the display panel includes multiple rows of gate lines, and the scan signal output terminals GOUT1 and the second output terminal GOUT2 of the shift register units of each stage in the gate driving circuit 20 can be configured to be connected to the multiple rows of gate lines in sequence.
  • the gate driving circuit 20 can also be arranged on both sides of the display panel to realize bilateral driving. The embodiment of the present disclosure does not limit the arrangement of the gate driving circuit 20.
  • the shift register unit 10 in the gate driving circuit 20 shown in FIG. 8 may adopt the circuit structure shown in FIG. 5, and FIG. 9 shows the gate driving circuit 20 shown in FIG. Signal timing diagram at work.
  • H1 ⁇ 1>, H1 ⁇ 2>, and H1 ⁇ 3> represent the first stage shift register unit A1, the second stage shift register unit A2, and the third stage shift register unit A3, respectively.
  • Q1 ⁇ 1> represents the first node in the first-stage shift register unit A1, and controls the output of the scan signal output terminal GOUT1 ⁇ 1> of the first-stage shift register unit A1, and Q2 ⁇ 1> represents the first-stage shift
  • the second node in the register unit A1 controls the output of the second output terminal GOUT2 ⁇ 2> of the first-stage shift register unit A1
  • Q1 ⁇ 2> represents the first node in the second-stage shift register unit A2
  • Q2 ⁇ 2> represents the second node in the second-stage shift register unit A2, and controls the second node of the second-stage shift register unit A2
  • the output of the second output terminal GOUT2 ⁇ 4>; Q1 ⁇ 3> represents the first node in the third-stage shift register unit A3, which controls the output of the scan signal output terminal GOUT1 ⁇ 5> of the third-stage shift register unit A3, Q2 ⁇ 3> represents the second node in the third
  • GOUT1 ⁇ 1> represents the scan signal output terminal of the first-stage shift register unit A1 and the first output signal output by it
  • GOUT2 ⁇ 2> represents the second output terminal of the first-stage shift register unit A1 and its output Two output signal.
  • GOUT1 ⁇ 3> and GOUT2 ⁇ 4> respectively represent the scanning signal output terminal of the second-stage shift register unit A2 and the first output signal and the second output terminal and the second output signal output by it
  • GOUT1 ⁇ 5> and GOUT2 ⁇ 6> respectively represent the scan signal output terminal of the third-stage shift register unit A3 and the first output signal and second output terminal and the second output signal output by it
  • GOUT1 ⁇ 7> represents The scanning signal output terminal of the fourth stage shift register unit A4 and the first output signal outputted by it.
  • the numbers in parentheses indicate the number of rows of sub-pixel units in the display panel corresponding to the output end. The following embodiments are the same as this, and will not be repeated.
  • CR ⁇ 1> represents the shift signal of the first stage shift register unit
  • CR ⁇ 3> represents the shift signal of the second stage shift register unit
  • CR ⁇ 5> represents the shift signal of the third stage shift register unit
  • CR ⁇ 7> represents the shift signal of the 4th stage shift register unit
  • 1F represents the first frame, including a display period and a blanking period.
  • the display period is used to drive the display panel to display, and the blanking period is used to compensate for the pixel circuit in the display panel.
  • the signal level in the signal timing diagram shown in FIG. 9 is only schematic and does not represent a true level value.
  • the trigger signal line provides high level, the input terminal STU of the first stage shift register unit and the input terminal STU of the second stage shift register unit input high level, and the eighth transistor M8 and The ninth transistor M9 is turned on, so the high level input from the second voltage terminal VDD can charge the first node Q1 ⁇ 1> through the eighth transistor M8, so that the first node Q1 ⁇ 1> is pulled up to the first high
  • the level is maintained by the second capacitor C2.
  • the ninth transistor M9 since the ninth transistor M9 is turned on, the second node Q2 ⁇ 1> is connected to the first node Q1 ⁇ 1>. Therefore, the second node Q2 ⁇ 1> is also pulled up to the first high level and is Three capacitor C3 storage.
  • the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the first node Q1 ⁇ 1>, but due to the second clock signal terminal CLKD (connected to the first sub-clock signal line CLKD_1) and the third clock
  • the signal terminal CLKE1 (connected to the fifth sub-clock signal line CLKE_1) inputs a low-level signal at this stage, so the shift output terminal CR ⁇ 1> and the scan signal output terminal GOUT1 ⁇ 1> both output low-level signals.
  • the seventh transistor M7 is turned on under the control of the second node Q2 ⁇ 1>, but since the fourth clock signal terminal CLKE2 (connected to the sixth sub-clock signal line CLKE_2) inputs a low-level signal at this stage, the second output The terminal GOUT2 ⁇ 2> outputs a low-level signal.
  • the second clock signal terminal CLKD (and the first sub-clock signal line CLKD_1) and the third clock signal terminal CLKE1 (and the fifth sub-clock signal line CLKE_1) input high-level signals, and the first node Q1
  • the potential of ⁇ 1> is further pulled up to the second high level due to the bootstrap effect of the second capacitor C2, so the fifth transistor M5 and the sixth transistor M6 remain on, thereby shifting the output terminals CR ⁇ 1> and The scanning signal output terminal GOUT1 ⁇ 1> all output high-level signals.
  • the high-level signal output from the shift output terminal CR ⁇ 1> can be used for the scan shift of the upper and lower shift register units, for example, as the reset signal of the upper shift register unit or the next shift
  • the input signal of the register unit, and the high-level signal output from the scan signal output terminal GOUT1 ⁇ 1> and the second output terminal OUT2 can be used to drive the first row of sub-pixel units and the second row of sub-pixel units in the display panel To display.
  • the second clock signal terminal CLKD, the third clock signal terminal CLKE1, and the fourth clock signal terminal CLKE2 (and the sixth sub-clock signal line CLKE_2) input high-level signals, and the first node Q1 ⁇ 1>
  • the shift output terminal CR ⁇ 1> and the scan signal output terminal GOUT1 ⁇ 1> both output high-level signals.
  • the fourth clock signal terminal CLKE2 since the fourth clock signal terminal CLKE2 inputs a high level signal, the potential of the second node Q2 ⁇ 1> is further pulled up to the second high level due to the bootstrap effect of the third capacitor C3, so the seventh transistor M7 remains Turn on, so that the second output terminal GOUT2 ⁇ 2> outputs a high-level signal.
  • the selection control signal line OE_1 provides a high level. Therefore, the selection control terminal OE of the shift register unit of each stage inputs a high level, so the first transistor M1 is turned on, so that the first node Q1 ⁇ 1> and the first node Q1 ⁇ 1> A blanking node H1 ⁇ 1> is connected. Since the first node Q1 ⁇ 1> is at a high level at this stage, the first blanking node H1 ⁇ 1> is also pulled up to a high level, and is also pulled up by the first capacitor C1 storage. The pull-up process of the first blanking node H1 ⁇ 1> of the second-stage shift register unit is similar to this, and will not be repeated.
  • the second clock signal terminal CLKD and the third clock signal terminal CLKE1 input low-level signals. Since the first node Q1 ⁇ 1> remains high at this time, the fifth transistor M5 and the sixth transistor M6 remains on, so that both the shift output terminal CR ⁇ 1> and the scan signal output terminal GOUT1 ⁇ 1> output low-level signals. Due to the bootstrap effect of the second capacitor C2, the potential of the first node Q1 ⁇ 1> will also drop.
  • the third stage shift register unit Since the first reset terminal STD of the first stage shift register unit A1 is connected to the shift output terminal CR ⁇ 5> of the third stage shift register unit A3, the third stage shift register unit The shift output terminal CR ⁇ 5> of A3 outputs high level, so the first reset terminal STD of the first stage shift register unit A1 inputs high level, the nineteenth transistor M19 and the twentieth transistor M20 are turned on, One node Q1 ⁇ 1> and the second node Q2 ⁇ 1> are pulled down to a low level, completing the resetting of the first node Q1 ⁇ 1> and the second node Q2 ⁇ 1>.
  • the eleventh transistor M11 and the thirteenth transistor M13 are turned off, and the high level input from the second voltage terminal can turn the third node Q3 ⁇ 1> and the fourth node Q4 ⁇ 1> are pulled up, and the third node Q3 ⁇ 1> and the fourth node Q4 ⁇ 1> are pulled up to a high level, so the fourteenth transistor M14 and the fifteenth transistor M15 are turned on , To further reset the first node Q1 ⁇ 1> and the second node Q2 ⁇ 1>.
  • the sixteenth transistor M16, the seventeenth transistor M17, and the eighteenth transistor M18 are also turned on, so that the shift output terminal CR ⁇ 1>, the scanning signal output terminal GOUT1 ⁇ 1> and the second output terminal GOUT2 ⁇ 2 can be connected. > Pull down further to reset.
  • the first-stage shift register unit drives the sub-pixels in the first row and the second-row sub-pixels in the display panel to complete the display, and so on, the second and third-stage shift register units drive the sub-pixels in the display panel row by row.
  • the pixel unit completes one frame of display drive. So far, the display period of one frame ends.
  • the high potential of the first blanking node H1 ⁇ 1> may be maintained until the blanking period of the first frame 1F.
  • the need to compensate for the second row of sub-pixel units in the first frame 1F is taken as an example for description, and the following operations are performed in the blanking period of the first frame 1F.
  • the second transistor M2 is turned on, so that the first clock signal terminal CLKA is connected to the second blanking node H2 ⁇ 1>.
  • the thirteenth sub-clock signal line CLKA_1 provides a high level. Since the first clock signal terminal CLKA is connected to the thirteenth sub-clock signal line CLKA_1, the input of the first clock signal terminal CLKA is high at this stage Therefore, at this stage, the second blanking node H2 ⁇ 1> is at a high level.
  • the third transistor M3 and the fourth transistor M4 are turned on in response to the high level received by the first clock signal terminal CLKA, so that the second The blanking node H2 ⁇ 1> is connected to the first node Q1 ⁇ 1> and the second node Q2 ⁇ 2>, thereby pulling the first node Q1 ⁇ 1> and the second node Q2 ⁇ 2> to the first high level .
  • the sixth sub-clock signal line CLKE_2 provides a high level
  • the fourth clock signal terminal CLKE2 (connected to the sixth sub-clock signal line CLKE_2) of the first-stage shift register unit A1 inputs a high level signal
  • the potential of the second node Q2 ⁇ 1> is further pulled up to the second level due to the bootstrap action of the third capacitor C3, the seventh transistor M7 of the first-stage shift register unit A1 is turned on, and the first-stage shift
  • the high-level signal input from the fourth clock signal terminal CLKE2 of the bit register unit A1 can be output to the second output terminal GOUT2 ⁇ 2>.
  • the signal output from the second output terminal GOUT2 ⁇ 2> can be used to drive the sensing transistor in the sub-pixel unit in the display panel to achieve external compensation.
  • the second clock signal terminal CLKD (connected to the first sub-clock signal line CLKD_1) and the third clock signal terminal CLKE1 (connected to the fifth sub-clock signal line CLKE_1 of the first stage shift register unit A1) )
  • the signal input from the fourth clock signal terminal CLKE2 (connected to the sixth sub-clock signal line CLKE_2) from high level to low level, the potential of the second node Q2 ⁇ 2> is due to the bootstrap action of the third capacitor C3 It is pulled down to the first high level.
  • the selection control signal line OE_1 and the total reset signal line TRST_1 provide a high level. Since the selection control terminals OE of the shift register units of each level are connected to the selection control signal line OE_1, the shift register units of each level The second reset terminal TRST is connected to the total reset signal line TRST_1, so the first blanking node H1, the first node Q1 and the second node Q2 of the shift register units of each level can be reset.
  • the driving signal corresponding to the first row of sub-pixel units and the second row of pixel units of the display panel is output in the blanking period of the first frame 1F as an example. It is noted that the embodiment of the present disclosure does not limit this.
  • the same timing of the two signals refers to time synchronization at a high level, and the amplitude of the two signals is not required to be the same.
  • the display device 1 includes a gate driving circuit 20 provided by an embodiment of the present disclosure and a plurality of sub-pixel units 410 arranged in an array.
  • the display device 1 further includes a display panel 40, and a pixel array composed of a plurality of sub-pixel units 410 is arranged in the display panel 40.
  • the scan signal output terminal GOUT1 and the second output terminal GOUT2 in the first output terminal OUT1 of each shift register unit 10 in the gate driving circuit 20 are electrically connected to the sub-pixel units 410 in different rows, for example, the gate
  • the driving circuit 20 is electrically connected to the sub-pixel unit 410 through the gate line GL.
  • the gate driving circuit 20 is used to provide a driving signal to the pixel array.
  • the driving signal can drive the scan transistor and the sensing transistor in the sub-pixel unit 410.
  • the display device 1 may further include a data driving circuit 30 for providing data signals to the pixel array.
  • the data driving circuit 30 is electrically connected to the sub-pixel unit 410 through the data line DL.
  • the display device 1 in this embodiment can be: LCD panel, LCD TV, display, OLED panel, OLED TV, electronic paper display device, mobile phone, tablet computer, notebook computer, digital photo frame, navigator, etc. Products or parts with display functions.
  • At least one embodiment of the present disclosure further provides a driving method, which can be used to drive the shift register unit 10 provided by the embodiment of the present disclosure.
  • a plurality of the shift register units 10 can be cascaded to construct the gate of at least one embodiment of the present disclosure.
  • the gate driving circuit is used to drive the display panel to display at least one frame of picture.
  • the driving method includes a display period and a blanking period for one frame.
  • the input circuit 110 charges the first node Q1 in response to the input signal input from the input terminal STU
  • the first control circuit 120 charges the second node Q2 in response to the input signal and the level of the first node Q1, and blanks
  • the control circuit 130 charges the first blanking node H1 of the blanking control circuit 130 under the control of the level of the first node Q1
  • the first output circuit 141 charges the first blanking node H1 of the blanking control circuit 130 under the control of the level of the first node Q1.
  • An output terminal OUT1 outputs the first output signal
  • the second output circuit 142 outputs a second output signal at the second output terminal GOUT2 under the control of the level of the second node Q2.
  • the blanking control circuit 130 charges the first node Q1 and the second node Q2 under the control of the selection control signal, the first clock signal and the level of the first blanking node H1; the first output circuit 141 outputs the first output signal at the first output terminal OUT1 under the control of the level of the first node Q1, and the second output circuit 142 outputs the first output signal at the second output terminal GOUT2 under the control of the level of the second node Q2 Two output signal.

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Abstract

一种移位寄存器单元(10)、栅极驱动电路(20)、显示装置(1)及驱动方法。移位寄存器单元(10)包括输入电路(110)、第一控制电路(120)、消隐控制电路(130)、第一输出电路(141)和第二输出电路(142)。输入电路(110)配置为响应于输入信号对第一节点(Q1)的电平进行控制；第一控制电路(120)配置为响应于输入信号以及第一节点(Q1)的电平，对第二节点(Q2)的电平进行控制；消隐控制电路(130)配置为对第一节点(Q1)的电平和第二节点(Q2)的电平进行控制；第一输出电路(141)配置为在第一节点(Q1)的电平的控制下，在第一输出端(OUT1)输出第一输出信号；第二输出电路(142)配置为在第二节点(Q2)的电平的控制下，在第二输出端(GOUT2)输出第二输出信号。移位寄存器单元(10)可以节省晶体管和电容的数目，从而使得采用该移位寄存器单元(10)的显示装置(1)可以减小边框尺寸。

Description

移位寄存器单元及驱动方法、栅极驱动电路和显示装置 技术领域
本公开的实施例涉及一种移位寄存器单元及驱动方法、栅极驱动电路和显示装置。
背景技术
在显示技术领域，例如液晶显示面板或有机发光二极管(Organic Light Emitting Diode,OLED)显示面板的像素阵列通常包括多行栅线和与该多行栅线交错的多列数据线。对栅线的驱动可以通过栅极驱动电路实现。栅极驱动电路通常集成在栅极驱动芯片(Gate IC)中。
发明内容
本公开至少一实施例提供一种移位寄存器单元，包括输入电路、第一控制电路、消隐控制电路、第一输出电路和第二输出电路。所述输入电路与输入端连接，且配置为响应于所述输入端输入的输入信号对第一节点的电平进行控制；所述第一控制电路与所述输入端、所述第一节点和第二节点连接，且配置为响应于所述输入端输入的所述输入信号以及所述第一节点的电平，对所述第二节点的电平进行控制；所述消隐控制电路与所述第一节点和所述第二节点连接，且配置为在选择控制信号、第一时钟信号和所述第一节点的电平的控制下，对所述第一节点的电平和所述第二节点的电平进行控制；所述第一输出电路包括第一输出端，且所述第一输出电路配置为在所述第一节点的电平的控制下，在所述第一输出端输出第一输出信号；所述第二输出电路包括第二输出端，且所述第二输出电路配置为在所述第二节点的电平的控制下，在所述第二输出端输出第二输出信号。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述消隐控制电路包括第一控制子电路、第二控制子电路和第三控制子电路；所述第一控制子电路与所述第一节点和第一消隐节点连接，且配置为在所述选择控制信号和所述第一节点的电平的控制下，对所述第一消隐节点的电平进行控制；所述第二控制子电路与所述第一消隐节点和第二消隐节点连接，且配置为在 所述第一消隐节点的电平的控制下，对所述第二消隐节点的电平进行控制；所述第三控制子电路与所述第二消隐节点、所述第一节点和所述第二节点连接，且配置为在所述第一时钟信号的控制下，对所述第一节点和所述第二节点的电平进行控制。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一控制子电路包括第一晶体管和第一电容，所述第二控制子电路包括第二晶体管，所述第三控制子电路包括第三晶体管和第四晶体管；所述第一晶体管的栅极和选择控制端连接以接收所述选择控制信号，所述第一晶体管的第一极和所述第一节点连接，所述第一晶体管的第二极和所述第一消隐节点连接；所述第一电容的第一极和所述第一消隐节点连接，所述第一电容的第二极和第一电压端连接以接收第一电压；所述第二晶体管的栅极和所述第一消隐节点连接，所述第二晶体管的第一极和第一时钟信号端连接以接收所述第一时钟信号，所述第二晶体管的第二极和所述第二消隐节点连接；所述第三晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第三晶体管的第一极和所述第二消隐节点连接，所述第三晶体管的第二极和所述第一节点连接；所述第四晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第四晶体管的第一极和所述第二消隐节点连接，所述第四晶体管的第二极和所述第二节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一输出端包括移位输出端和至少一个扫描信号输出端。
例如，在本公开至少一实施例提供的移位寄存器单元中，在所述第一输出端包括移位输出端和一个扫描信号输出端的情形下，所述第一输出电路包括第五晶体管、第六晶体管和第二电容；所述第五晶体管的栅极和所述第一节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收第二时钟信号并作为所述第一输出信号，所述第五晶体管的第二极和所述移位输出端连接；所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和第三时钟信号端连接以接收第三时钟信号并作为所述第一输出信号，所述第六晶体管的第二极和所述扫描信号输出端连接；所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述第五晶体管或所述第六晶体管的第二极连接；所述第二时钟信号和所述第三时钟信号在显示时段的 时序相同。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二输出电路包括第七晶体管和第三电容；所述第七晶体管的栅极和所述第二节点连接，所述第七晶体管的第一极和第四时钟信号端连接以接收第四时钟信号并作为所述第二输出信号，所述第七晶体管的第二极和所述第二输出端连接；所述第三电容的第一极和所述第二节点连接，所述第三电容的第二极和所述第二输出端连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述输入电路包括第八晶体管；所述第八晶体管的栅极和所述输入端连接以接收所述输入信号，所述第八晶体管的第一极和第二电压端连接以接收第二电压，所述第八晶体管的第二极和所述第一节点连接。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一控制电路包括第九晶体管；所述第九晶体管的栅极和所述输入端连接以接收所述输入信号，所述第九晶体管的第一极和所述第一节点连接，所述第九晶体管的第二极和所述第二节点连接。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第二控制电路和第三控制电路；所述第二控制电路与所述第一节点和第三节点连接，且配置为在所述第一节点的电平的控制下，对所述第三节点的电平进行控制；所述第三控制电路与所述第二节点和第四节点连接，且配置为在所述第二节点的电平的控制下，对所述第四节点的电平进行控制。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第二控制电路包括第十晶体管和第十一晶体管，所述第三控制电路包括第十二晶体管和第十三晶体管；所述第十晶体管的栅极和第一极连接，且与第二电压端连接以接收第二电压，所述第十晶体管的第二极和所述第三节点连接；所述第十一晶体管的栅极和所述第一节点连接，所述第十一晶体管的第一极和所述第三节点连接，所述第十一晶体管的第二极和第一电压端连接以接收第一电压；所述第十二晶体管的栅极和第一极连接，且与所述第二电压端连接以接收所述第二电压，所述第十二晶体管的第二极和所述第四节点连接；所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述第四节点连接，所述第十三晶体管的第二极和所述第一电压端连接以接收所 述第一电压。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第一节点降噪电路和第二节点降噪电路；所述第一节点降噪电路与所述第一节点和所述第三节点连接，且配置为在所述第三节点的电平的控制下，对所述第一节点降噪；所述第二节点降噪电路与所述第二节点和所述第四节点连接，且配置为在所述第四节点的电平的控制下，对所述第二节点进行降噪。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一节点降噪电路包括第十四晶体管，所述第二节点降噪电路包括第十五晶体管；所述第十四晶体管的栅极和所述第三节点连接，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极和第一电压端连接以接收第一电压；所述第十五晶体管的栅极和所述第四节点连接，所述第十五晶体管的第一极和所述第二节点连接，所述第十五晶体管的第二极和所述第一电压端连接以接收所述第一电压。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第一输出降噪电路和第二输出降噪电路；所述第一输出降噪电路与所述第三节点和所述第一输出端连接，且配置为在所述第三节点的电平的控制下，对所述第一输出端降噪；所述第二输出降噪电路与所述第四节点和所述第二输出端连接，且配置为在所述第四节点的电平的控制下，对所述第二输出端降噪。
例如，在本公开至少一实施例提供的移位寄存器单元中，，在所述第一输出端包括移位输出端和一个扫描信号输出端的情形下，所述第一输出降噪电路包括第十六晶体管和第十七晶体管，所述第二输出降噪电路包括第十八晶体管；所述第十六晶体管的栅极和所述第三节点连接，所述第十六晶体管的第一极和所述移位输出端连接，所述第十六晶体管的第二极和第一电压端连接以接收第一电压；所述第十七晶体管的栅极和所述第三节点连接，所述第十七晶体管的第一极和所述扫描信号输出端连接，所述第十七晶体管的第二极和第三电压端连接以接收第三电压；所述第十八晶体管的栅极和所述第四节点连接，所述第十八晶体管的第一极和所述第二输出端连接，所述第十八晶体管的第二极和所述第三电压端连接以接收所述第三电压。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第一复位电路和第二复位电路；所述第一复位电路与所述第一节点和第一复位端连接， 且配置为响应于所述第一复位端提供的第一复位信号，对所述第一节点复位；所述第二复位电路与所述第二节点和所述第一复位端连接，且配置为响应于所述第一复位信号，对所述第二节点复位。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一复位电路包括第十九晶体管，所述第二复位电路包括第二十晶体管；所述第十九晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第十九晶体管的第一极和所述第一节点连接，所述第十九晶体管的第二极和第一电压端连接以接收第一电压；所述第二十晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第二十晶体管的第一极和所述第二节点连接，所述第二十晶体管的第二极和所述第一电压端连接以接收所述第一电压。
例如，本公开至少一实施例提供的移位寄存器单元，还包括第一总复位电路和第二总复位电路；所述第一总复位电路与所述第一节点和第二复位端连接，且配置为响应于所述第二复位端提供的第二复位信号，对所述第一节点复位；所述第二总复位电路与所述第二节点和所述第二复位端连接，且配置为响应于所述第二复位信号，对所述第二节点复位。
例如，在本公开至少一实施例提供的移位寄存器单元中，所述第一总复位电路包括第二十一晶体管，所述第二总复位电路包括第二十二晶体管；所述第二十一晶体管的栅极和所述第二复位端连接以接收所述第二复位信号，所述第二十一晶体管的第一极和所述第一节点连接，所述第二十一晶体管的第二极和第一电压端连接以接收第一电压；所述第二十二晶体管的的栅极和所述第二复位端连接以接收所述第二复位信号，所述第二十二晶体管的第一极和所述第二节点连接，所述第二十二晶体管的第二极和所述第一电压端连接以接收所述第一电压。
本公开至少一实施例提供一种栅极驱动电路，包括本公开任一实施例提供的移位寄存器单元。
本公开至少一实施例提供一种显示装置，包括本公开任一实施例提供的栅极驱动电路以及多个呈阵列排布的子像素单元；所述栅极驱动电路中的每一个移位寄存器单元中的所述第一输出端和所述第二输出端分别和位于不同行的子像素单元电连接。
本公开至少一实施例提供一种移位寄存器单元的驱动方法，包括用于一 帧的显示时段和消隐时段；在所述显示时段，所述输入电路响应于所述输入端输入的输入信号对所述第一节点充电，所述第一控制电路响应于所述输入信号以及所述第一节点的电平，对所述第二节点充电，所述消隐控制电路在所述第一节点的电平的控制下，对所述消隐控制电路的第一消隐节点进行充电；所述第一输出电路在所述第一节点的电平的控制下，在所述第一输出端输出所述第一输出信号，所述第二输出电路在所述第二节点的电平的控制下，在所述第二输出端输出所述第二输出信号；在所述消隐阶段，所述消隐控制电路在所述选择控制信号、所述第一时钟信号和所述第一消隐节点的电平的控制下，对所述第一节点和所述第二节点进行充电；所述第一输出电路在所述第一节点的电平的控制下，在所述第一输出端输出所述第一输出信号，所述第二输出电路在所述第二节点的电平的控制下，在所述第二输出端输出所述第二输出信号。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意图；
图2为本公开至少一实施例提供的一种消隐控制电路的示意图；
图3为本公开至少一实施例提供的另一种移位寄存器单元的示意图；
图4为本公开至少一实施例提供的又一种移位寄存器单元的示意图；
图5为图4所示的一种移位寄存器单元的一种具体实现示例的电路图；
图6为图4所示的一种移位寄存器单元的另一种具体实现示例的电路图；
图7为图4所示的一种移位寄存器单元的又一种具体实现示例的电路图；
图8为本公开至少一实施例提供的一种栅极驱动电路的示意图；
图9为本公开至少一实施例提供的一种对应于图8所示的栅极驱动电路工作时的信号时序图；以及
图10为本公开至少一实施例提供的一种显示装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
在对OLED显示面板中的子像素单元进行补偿时，除了在子像素单元中设置像素补偿电路进行内部补偿外，还可以通过设置感测晶体管进行外部补偿。在进行外部补偿时，由移位寄存器单元构成的栅极驱动电路需要向显示面板中的子像素单元分别提供用于扫描晶体管和感测晶体管的驱动信号，例如，在一帧的显示时段提供用于扫描晶体管的扫描驱动信号，在一帧的消隐时段提供用于感测晶体管的感测驱动信号。
在一种外部补偿方法中，栅极驱动电路输出的感测驱动信号是逐行顺序扫描的，例如，在第一帧的消隐时段输出用于显示面板中第一行的子像素单元的感测驱动信号，在第二帧的消隐时段输出用于显示面板中第二行的子像素单元的感测驱动信号，依次类推，以每帧输出对应一行子像素单元的感测驱动信号的频率逐行顺序输出，即完成对该显示面板的逐行顺序补偿。
如上所述，在栅极驱动电路驱动一个显示面板中的多行子像素单元时，如果要实现外部补偿，则需要该栅极驱动电路不仅可以输出用于显示时段的扫描驱动信号，同时还需要输出用于消隐时段的感测驱动信号。
但是，栅极驱动电路要实现在显示时段和消隐时段输出两种不同周期和 不同脉冲宽度的驱动信号是非常困难的，而且，还要求栅极驱动电路的结构尽量的简单。因此，如何通过尽量少的晶体管数目以及电容数据实现具有上述功能的高PPI(Pixels Per Inch，每英寸像素数量)的显示装置，成为本领域的技术人员亟需解决的问题。
针对上述问题，本公开至少一实施例提供一种移位寄存器单元，该移位寄存器单元包括输入电路、第一控制电路、消隐控制电路、第一输出电路和第二输出电路。输入电路与输入端连接，且配置为响应于输入端输入的输入信号对第一节点的电平进行控制；第一控制电路与输入端、第一节点和第二节点连接，且配置为响应于输入端输入的输入信号以及第一节点的电平，对第二节点的电平进行控制；消隐控制电路与第一节点和第二节点连接，且配置为在选择控制信号、第一时钟信号和第一节点的电平的控制下，对第一节点的电平和第二节点的电平进行控制；第一输出电路包括第一输出端，且第一输出电路配置为在第一节点的电平的控制下，在第一输出端输出第一输出信号；第二输出电路包括第二输出端，且第二输出电路配置为在第二节点的电平的控制下，在第二输出端输出第二输出信号。
本公开一些实施例还提供对应于上述移位寄存器单元的栅极驱动电路、显示装置及驱动方法。
本公开上述实施例提供的移位寄存器单元，通过共用一个消隐控制电路实现对第一节点的电平和第二节点的电平的控制，以在第一节点的电平和第二节点的电平的控制下，实现通过一级移位寄存器单元输出两行驱动信号的功能，从而可以极大地减少晶体管数目和电容数目，减小采用该移位寄存器单元的显示装置的边框尺寸，降低成本，提高该显示装置的PPI。
需要说明的是，在本公开的实施例中，随机补偿指的是区别于逐行顺序补偿的一种外部补偿方法，在某一帧的消隐时段可以随机输出对应于显示面板中任意一行的子像素单元的感测驱动信号，以下各实施例与此相同，不再赘述。
另外，在本公开的实施例中，为了表示清楚、简洁，定义“一帧”、“每帧”或“某一帧”包括依次进行的显示时段和消隐时段，例如在显示时段中栅极驱动电路输出驱动信号，该驱动信号可以驱动显示面板中的多行子像素单元从第一行到最后一行完成完整的一幅图像的扫描显示，在消隐时段中栅极驱动 电路输出驱动信号，该驱动信号可以用于驱动显示面板中的某一行子像素单元中的感测晶体管，以完成该行子像素单元的外部补偿。
下面结合附图对本公开的实施例及其示例进行详细说明。
图1为本公开至少一实施例提供的一种移位寄存器单元的示意图。如图1所示，该移位寄存器单元10可以包括输入电路110、第一控制电路120、消隐控制电路130、第一输出电路141和第二输出电路142。通过级联多个该移位寄存器单元10可以得到栅极驱动电路，该栅极驱动电路用于驱动显示面板，为显示面板的多条栅线依序提供扫描信号，从而在显示面板显示一帧画面的期间进行逐行或隔行扫描等。
如图1所示，输入电路110与输入端STU连接，且配置为响应于输入端STU输入的输入信号对第一节点Q1的电平进行控制。例如，在一些示例中，输入电路110与输入端STU、第二电压端VDD和第一节点Q1连接，配置为在输入端STU提供的输入信号的控制下导通，使第二电压端VDD和第一节点Q1连接，从而使第二电压端VDD提供的第二电压被输入到第一节点Q1，将第一节点Q1的电位充电至工作电位(例如，可以使得与第一节点Q1连接的晶体管导通的电位)。例如，在另一些示例中，输入电路110可以与输入端STU和第一节点Q1连接，配置为在输入端STU提供的输入信号的控制下导通，使输入端STU和第一节点Q1连接，从而使输入端STU提供的输入信号被输入到第一节点Q1，将第一节点Q1的电位上拉到工作电位。需要注意的是，第二电压端VDD还可以由提供时钟信号的时钟信号端代替，只要满足在相应的阶段可以对第一节点Q1进行充电即可，本公开的实施例对此不作限制。
第一控制电路120与输入端STU、第一节点Q1和第二节点Q2连接，且配置为响应于输入端STU输入的输入信号以及第一节点Q1的电平，对第二节点Q2的电平进行控制。例如，在一些示例中，第一控制电路120与输入端STU、第一节点Q1和第二节点Q2连接，配置为在输入端STU提供的输入信号的控制下导通，使第二节点Q2和第一节点Q1连接，从而使得第二节点Q2的电位与第一节点Q1的电位一致，即通过第一节点Q1将第二节点Q2的电位充电至工作电位。
消隐控制电路130与第一节点Q1和第二节点Q2连接，且配置为在选择 控制信号、第一时钟信号和第一节点Q1的电平的控制下，对第一节点Q1的电平和第二节点Q2的电平进行控制。例如，在一些示例中，消隐控制电路130与选择控制端OE、第一时钟信号端CLKA、第一电压端VGL1、第一节点Q1和第二节点Q2连接，且配置为在选择控制端OE提供的选择控制信号的控制下存储第一节点Q1的电平，并在一帧的消隐时段，在第一时钟信号端CLKA提供的第一时钟信号和存储的第一节点Q1的电平的控制下，将第一时钟信号端CLKA提供的第一时钟信号提供至第一节点Q1和第二节点Q2，从而将第一节点Q1的电位和第二节点Q2的电位充电至工作电位。在该实施例中，一方面，第一节点Q1的电平和第二节点Q2的电平可以通过其共用的消隐控制电路130同时进行控制，不需要通过分别的电路进行分别控制，从而节省了移位寄存器单元中晶体管的数量，减小采用该移位寄存器单元的显示装置的边框尺寸，降低成本；另一方面，消隐控制电路130的输入端连接至第一节点Q1，而非连接至控制消隐时段的消隐输入端，即，显示时段和消隐时段可以共用一个输入电路110，从而极大地简化了移位寄存器单元的电路设计。
第一输出电路141包括第一输出端OUT1，且第一输出电路141配置为在第一节点Q1的电平的控制下，在第一输出端OUT1输出第一输出信号。例如，在一些示例中，第一输出电路141与第一节点Q1、第一输出端OUT1、第二时钟信号端CLKD连接，且配置为第一节点Q1的电平的控制下导通，使得第二时钟信号端CLKD提供的第二时钟信号作为第一输出信号输出至第一输出端OUT1。
例如，在一些示例中，第一输出端OUT1包括移位输出端和至少一个扫描信号输出端，从而将输出信号例如第二时钟信号端CLKD提供的第二时钟信号分别输出至移位输出端和扫描信号输出端，以提高该移位寄存器单元10的驱动能力。例如，在图3所示的示例中，至少一个扫描信号输出端包括一个扫描信号输出端GOUT1。例如，移位输出端CR用于为下一级移位寄存器单元10提供输入信号以及为上一级移位寄存器单元提供复位信号，扫描信号输出端GOUT1用于为显示面板中一行像素单元的像素电路提供驱动信号(例如，扫描驱动信号或感测驱动信号)。例如，移位输出端CR和该扫描信号输出端GOUT1可以输出相同的输出信号，也可以输出不同的输出信号。 需要注意的是，在其他示例中，当包括多个扫描信号输出端时，各个扫描信号输出端也可以输出不同的输出信号，具体的设置根据实际情况而定，本公开的实施例对此不作限制。
例如，有些移位寄存器单元10(例如，前几级移位寄存器单元)可以和触发信号线连接，从而接收由该触发信号线提供的输入信号STU；或者，有些移位寄存器单元10(例如，除该前几级移位寄存器单元之外的其与各级移位寄存器单元)还可以接收其它级移位寄存器单元10输出的移位信号CR作为输入信号STU。
需要注意的是，在另一些示例中，移位输出端可以仅在一帧的显示时段输出第一输出信号以满足级联需要(当然，也可以在消隐时段输出，只要不引起消隐时段的误显示即可)，扫描信号输出端为了实现对像素电路中的扫描晶体管和感测晶体管的分别驱动，除了在一帧的显示时段需要输出扫描驱动信号外，还需要在一帧的消隐时段输出感测驱动信号，因此，为了避免在消隐时段输出的感测驱动信号在移位输出端输出会造成显示错乱的现象，还可以包括第三时钟信号端CLKE1(如图3所示)。例如，通过第三时钟信号端CLKE1控制扫描信号输出端GOUT1的输出，通过第二时钟信号端CLKD控制移位输出端CR的输出，即扫描信号输出端GOUT1和移位输出端CR的输出的输出信号通过不同的时钟信号端提供，以避免在消隐时段输出的感测驱动信号在移位输出端输出。例如，该第三时钟信号端CLKE1提供的第三时钟信号的波形与第二时钟信号端CLKD提供的第二时钟信号的波形在显示时段完全相同，在消隐时段可以相同，也可以不相同。
第二输出电路142包括第二输出端GOUT2，且第二输出电路142配置为在第二节点Q2的电平的控制下，在第二输出端GOUT2输出第二输出信号。例如，在一些示例中，第二输出电路142与第二节点Q2、第二输出端GOUT2、第四时钟信号端CLKE2连接，且配置为第二节点Q2的电平的控制下导通，使得第四时钟信号端CLKE2提供的第四时钟信号作为第二输出信号输出至第二输出端GOUT2。
例如，第一输出端OUT1中的扫描信号输出端GOUT1和第二输出端GOUT2连接到不同的栅线。例如，第一输出端OUT1中的扫描信号输出端GOUT1连接第N(N为大于1的整数)行栅线，第二输出端GPUT2连接第 N+1行栅线。例如，该第一输出信号作为第N行栅线传输的扫描驱动信号或感测驱动信号，驱动与该第N行栅线连接的像素电路。例如，该第二输出信号作为第N+1行栅线传输的扫描驱动信号或感测驱动信号，驱动与该第N+1行栅线连接的像素电路，因此，本公开实施例提供的移位寄存器单元可以输出两行驱动信号。
本公开上述实施例提供的移位寄存器单元，通过共用一个消隐控制电路实现对第一节点Q1的电平和第二节点Q2的电平的控制，从而实现通过一级移位寄存器单元输出两行驱动信号的功能，从而极大地减少了晶体管数目和电容数目，减小采用该移位寄存器单元的显示装置的边框尺寸，降低成本，提高该显示装置的PPI。
图2为本公开至少一实施例提供的一种示例性消隐控制电路的示意图。如图2所示，该消隐控制电路130包括第一控制子电路131、第二控制子电路132和第三控制子电路133。
第一控制子电路131与第一节点Q1和第一消隐节点H1连接，且配置为在选择控制信号和第一节点Q1的电平的控制下，对第一消隐节点H1的电平进行控制。例如，第一控制子电路131与第一节点Q1、选择控制端OE、第一消隐节点H1和第一电压端VGL1连接，且配置为在选择控制端OE提供的选择控制信号的控制下导通，使得第一节点Q1与第一消隐节点H1连接，从而将第一节点Q1的电平写入第一消隐节点H1。
第二控制子电路132与第一消隐节点H1和第二消隐节点H2连接，且配置为在第一消隐节点H1的电平的控制下，对第二消隐节点H2的电平进行控制。例如，第二控制子电路132与第一时钟信号端CLKA、第一消隐节点H1和第二消隐节点H2连接，且配置为在第一消隐节点H1的电平的控制下导通，使得第一时钟信号端CLKA与第二消隐节点H2连接，从而将第一时钟信号写入第二消隐节点H2。
第三控制子电路133与第二消隐节点H2、第一节点Q1和第二节点Q2连接，且配置为在第一时钟信号的控制下，对第一节点Q1和第二节点Q2的电平进行控制。例如，第三控制子电路133与第一时钟信号端CLKA、第二消隐节点H2、第一节点Q1和第二节点Q2连接，且配置为在第一时钟信号端CLKA提供的第一时钟信号的控制下导通，使得第一节点Q1和第二节 点Q2与第二消隐节点H2连接，从而将第二消隐节点H2的电平写入第一节点Q1和第二节点Q2。例如，第一时钟信号端CLKA提供的第一时钟信号在一帧的消隐时段为有效电平时，可以通过第三控制子电路133在消隐时段同时控制第一节点Q1和第二节点Q2的电平，实现驱动相邻两行像素电路的移位寄存器单元中消隐控制电路的共用，从而减少了移位寄存器单元的晶体管的数量，有利于减小采用该移位寄存器单元的显示装置的边框尺寸。
图3为本公开至少一实施例提供的另一种移位寄存器单元的示意图。如图3所示，在图1所示的示例中，该移位寄存器单元10还包括第二控制电路151和第三控制电路152；在另一些示例中，该移位寄存器单元10还包括第一节点降噪电路161和第二节点降噪电路162；在另一些示例中，该移位寄存器单元10还包括第一输出降噪电路171和第二输出降噪电路172；在另一些示例中，该移位寄存器单元10还包括第一复位电路181和第二复位电路182。需要说明的是，图3所示的移位寄存器单元10的其他电路结构与图1中所示的移位寄存器单元10基本上相同，重复之处不再赘述。
第二控制电路151与第一节点Q1和第三节点Q3连接，且配置为在第一节点Q1的电平的控制下，对第三节点Q3的电平进行控制。例如，在一些示例中，第二控制电路151被配置为接收第二电压VDD和第一电压VGL1。例如，当第一节点Q1处于高电平时，第二控制电路151可以利用低电平的第一电压VGL1将第三节点Q3下拉至低电平。又例如，当第一节点Q1的电位处于低电平时，第二控制电路151可以利用第二电压VDD(例如为高电平)对第三节点Q3进行充电，以将第三节点Q3上拉至高电平。
第三控制电路152与第二节点Q2和第四节点Q4连接，且配置为在第二节点Q2的电平的控制下，对第四节点Q4的电平进行控制。例如，在一些示例中，第三控制电路152被配置为接收第二电压VDD和第一电压VGL1。例如，当第二节点Q2处于高电平时，第三控制电路152可以利用低电平的第一电压VGL1将第四节点Q4下拉至低电平。又例如，当第二节点Q2的电位处于低电平时，第三控制电路152可以利用第二电压VDD(例如为高电平)对第四节点Q4进行充电，以将第四节点Q4上拉至高电平。
第一节点降噪电路161与第一节点Q1和第三节点Q3连接，且配置为在第三节点Q3的电平的控制下，对第一节点Q1降噪。例如，在一些示例中， 第一节点降噪电路161与第一电压端VGL1、第一节点Q1和第三节点Q3连接，且配置为在第三节点Q3的电平的控制下导通时，使得第一节点Q1和第一电压端VGL1连接，从而可以利用第一电压VGL1对第一节点Q1进行下拉(例如，放电)，以实现降噪。
第二节点降噪电路162与第二节点Q2和第四节点Q4连接，且配置为在第四节点Q4的电平的控制下，对第二节点Q2进行降噪。例如，在一些示例中，第二节点降噪电路162与第一电压端VGL1、第二节点Q2和第四节点Q4连接，且配置为在第四节点Q4的电平的控制下导通时，使得第二节点Q2和第一电压端VGL1连接，从而可以利用第一电压VGL1对第二节点Q2进行下拉(例如，放电)，以实现降噪。
第一输出降噪电路171与第三节点Q3和第一输出端OUT1(例如，包括移位输出端CR和扫描信号输出端GOUT1)连接，且配置为在第三节点Q3的电平的控制下，对第一输出端OUT1降噪。例如，在一些示例中，第一输出降噪电路171与第三电压端VGL2、第三节点Q3和第一输出端OUT1连接，且配置为在第三节点Q3的电平的控制下导通时，使得第一输出端OUT1和第三电压端VGL2连接，从而可以利用第三电压VGL2对第一输出端OUT1进行下拉(例如，放电)，以实现降噪。
第二输出降噪电路172与第四节点Q4和第二输出端GOUT2连接，且配置为在第四节点Q4的电平的控制下，对第二输出端GOUT2降噪。例如，在一些示例中，第二输出降噪电路172与第三电压端VGL2、第四节点Q4和第二输出端GOUT2连接，且配置为在第四节点Q4的电平的控制下导通时，使得第二输出端GOUT2和第三电压端VGL2连接，从而可以利用第三电压VGL2对第二输出端GOUT2进行下拉(例如，放电)，以实现降噪。
需要说明的是，在本公开的一些实施例中，也可以利用第一电压VGL1对第一输出端OUT1和第二输出端GOUT2进行下拉复位，本公开对此不作限制。另外，在本公开的实施例中，第三电压VGL2例如为低电平，以下各实施例与此相同，不再赘述。在本公开的实施例中，第三电压VGL2可以和第一电压VGL1相同，也可以不同。
第一复位电路181与第一节点Q1和第一复位端STD连接，且配置为响应于第一复位端STD提供的第一复位信号，对第一节点Q1复位。例如，在 一些示例中，在一帧的显示时段中，第一复位电路181响应于第一复位信号STD而导通，从而可以利用第一电压VGL1对第一节点Q1进行下拉复位。例如，当多个移位寄存器单元10级联构成栅极驱动电路时，某一级移位寄存器单元10可以接收其它级移位寄存器单元10输出的移位信号CR作为显示复位信号STD。
第二复位电路182与第二节点Q2和第一复位端STD连接，且配置为响应于第一复位信号，对第二节点Q2复位。例如，第二复位电路182的工作原和第一复位电路181的工作原理类似，在此不再赘述。
图4为本公开至少一实施例提供的又一种移位寄存器单元的示意图。如图4所示，在图3所示的示例的基础上，该移位寄存器单元10还包括第一总复位电路191和第二总复位电路192。需要说明的是，图4所示的移位寄存器单元10的其他电路结构与图3中所示的移位寄存器单元10基本上相同，重复之处不再赘述。
第一总复位电路191与第一节点Q1和第二复位端TRST连接，且配置为响应于第二复位端TRST提供的第二复位信号，对第一节点Q1复位。例如，当多个移位寄存器单元10级联构成栅极驱动电路时，在一帧的显示时段前或一帧的消隐时段后，各级移位寄存器单元10中的第一总复位电路191响应于第二复位信号TRST而导通，使得第四电压端VGL1和第一节点Q1连接，从而可以利用低电平的第四电压VGL1对第一节点Q1进行下拉复位，从而实现对栅极驱动电路20的全局复位。
第二总复位电路192与第二节点Q2和第二复位端TRST连接，且配置为响应于第二复位信号，对第二节点Q2复位。例如，第二总复位电路192的工作原理和第一总复位电路191的工作原理类似，在此不再赘述。
本领域技术人员可以理解，尽管图1-图4中示出了多个控制电路和多个复位电路，然而上述示例并不能限制本公开的保护范围。在实际应用中，技术人员可以根据情况选择使用或不使用上述各电路中的一个或多个，基于前述各电路的各种组合变型均不脱离本公开的原理，对此不再赘述。
图4所示的移位寄存器单元的其他结构可参考图3中的相关描述，在此不再赘述。
在本公开的一些实施例中，图4中所示的移位寄存器单元10可以实现为 图5所示的电路结构。如图5所示，该移位寄存器单元10包括：第一晶体管M1至第二十二晶体管M22、第一电容C1、第二电容C2以及第三电容C3。需要说明的是，在图5中所示的晶体管均以N型晶体管为例进行说明，本公开的实施例对此不作限制，例如移位寄存器单元10中的至少部分晶体管也可以采用P型晶体管。
如图5所示，输入电路110包括第八晶体管M8。第八晶体管M8的栅极和输入端STU连接以接收输入信号，第八晶体管M8的第一极和第二电压端VDD连接以接收第二电压，第八晶体管M8的第二极和第一节点Q1连接。
例如，在另一些示例中，如图6所示，第八晶体管M8的栅极和第一极彼此电连接且被配置为接收输入信号STU，从而在输入信号STU为高电平时，利用高电平的输入信号STU对第一节点Q1进行充电。
如图5所示，在第一输出端OUT1包括移位输出端CR和一个扫描信号输出端GOUT1的情形下，第一输出电路141包括第五晶体管M5、第六晶体管M6和第二电容C2。
第五晶体管M5的栅极和第一节点Q1连接，第五晶体管M5的第一极和第二时钟信号端CLKD连接以接收第二时钟信号并作为第一输出信号，第五晶体管M5的第二极和移位输出端CR连接。
第六晶体管M6的栅极和第一节点Q1连接，第六晶体管M6的第一极和第三时钟信号端CLKE1连接以接收第三时钟信号并作为第一输出信号，第六晶体管M6的第二极和扫描信号输出端GOUT1连接。例如，第二时钟信号CLKD和第三时钟信号CLKE1在显示时段的时序相同。例如，第三时钟信号和第二时钟信号在消隐时段的时序可以相同也可以不同，只要满足显示装置的正常显示即可，本公开的实施例对此不作限制。例如，在另一些实施例中，如图7所示，第六晶体管M6的第一极也可以和第二时钟信号端CLKD连接以接收第二时钟信号并作为第一输出信号，用于像素电路的扫描驱动。需要注意的是，第五晶体管M5的第一极和第六晶体管M6的第一极分别连接到不同的时钟信号端，可以避免在消隐时段需要输出感测扫描信号时，移位输出端CR也输出高电平，使得与其相连的下一级移位寄存器单元的第一节点Q1和第二节点Q2被充电至高电平，造成显示面板的误输出。
第二电容C2的第一极和第一节点Q1连接，第二电容C2的第二极和第 六晶体管M6(或第五晶体管M5)的第二极连接。
第二输出电路142包括第七晶体管M7和第三电容C3。第七晶体管M7的栅极和第二节点Q2连接，第七晶体管M7的第一极和第四时钟信号端CLKE2连接以接收第四时钟信号并作为第二输出信号，第七晶体管的第二极和第二输出端GOUT2连接。第三电容C3的第一极和第二节点Q2连接，第三电容C3的第二极和第二输出端GOUT2连接。
第一控制电路120包括第九晶体管M9。第九晶体管M9的栅极和输入端STU连接以接收输入信号，第九晶体管M9的第一极和第一节点Q1连接，第九晶体管M9的第二极和第二节点Q2连接。
第一控制子电路131包括第一晶体管M1和第一电容C1，第二控制子电路132包括第二晶体管M2，第三控制子电路133包括第三晶体管M3和第四晶体管M4。
第一晶体管M1的栅极和选择控制端OE连接以接收选择控制信号，第一晶体管M1的第一极和第一节点Q1连接，第一晶体管M1的第二极和第一消隐节点H1连接。第一电容C1的第一极和第一消隐节点H1连接，第一电容C1的第二极和第一电压端VGL1连接以接收第一电压。
第二晶体管M2的栅极和第一消隐节点H1连接，第二晶体管M2的第一极和第一时钟信号端CLKA连接以接收第一时钟信号，第二晶体管M2的第二极和第二消隐节点H2连接。
第三晶体管M3的栅极和第一时钟信号端CLKA连接以接收第一时钟信号，第三晶体管M3的第一极和第二消隐节点H2连接，第三晶体管M3的第二极和第一节点Q2连接。第四晶体管M4的栅极和第一时钟信号端CLKA连接以接收第一时钟信号，第四晶体管M4的第一极和第二消隐节点H2连接，第四晶体管M4的第二极和第二节点Q2连接。
第二控制电路151包括第十晶体管M10和第十一晶体管M11，第三控制电路152包括第十二晶体管M12和第十三晶体管M1。
第十晶体管M10的栅极和第一极连接，且与第二电压端VDD连接以接收第二电压，第十晶体管M10的第二极和第三节点Q3连接。第十一晶体管M11的栅极和第一节点Q1连接，第十一晶体管M11的第一极和第三节点Q3连接，第十一晶体管M11的第二极和第一电压端VGL1连接以接收第一 电压。
第十二晶体管M12的栅极和第一极连接，且与第二电压端VDD连接以接收第二电压，第十二晶体管M12的第二极和第四节点Q4连接；第十三晶体管M13的栅极和第二节点Q2连接，第十三晶体管M13的第一极和第四节点Q4连接，第十三晶体管M13的第二极和第一电压端VGL1连接以接收第一电压。
第一节点降噪电路161包括第十四晶体管M14，第二节点降噪电路162包括第十五晶体管M15。第十四晶体管M14的栅极和第三节点Q3连接，第十四晶体管M14的第一极和第一节点Q1连接，第十四晶体管M14的第二极和第一电压端VGL1连接以接收第一电压。第十五晶体管M15的栅极和第四节点Q4连接，第十五晶体管M15的第一极和第二节点Q2连接，第十五晶体管M15的第二极和第一电压端VGL1连接以接收所述第一电压。
例如，在第一输出端OUT1包括移位输出端CR和一个扫描信号输出端GOUT1的情形下，第一输出降噪电路171包括第十六晶体管M16和第十七晶体管M17，第二输出降噪电路172包括第十八晶体管M18。
第十六晶体管M16的栅极和第三节点Q3连接，第十六晶体管M16的第一极和移位输出端CR连接，第十六晶体管M16的第二极和第一电压端VGL1连接以接收第一电压。第十七晶体管M17的栅极和第三节点Q3连接，第十七晶体管M17的第一极和扫描信号输出端GOUT1连接，第十七晶体管M17的第二极和第三电压端VGL2连接以接收第三电压。第十八晶体管M18的栅极和第四节点Q4连接，第十八晶体管M18的第一极和第二输出端GOUT2连接，第十八晶体管M18的第二极和第三电压端VGL2连接以接收第三电压。
第一复位电路181包括第十九晶体管M19，第二复位电路182包括第二十晶体管M20。第十九晶体管M19的栅极和第一复位端STD连接以接收第一复位信号，第十九晶体管M19的第一极和第一节点Q1连接，第十九晶体管M19的第二极和第一电压端VGL1连接以接收第一电压。第二十晶体管M20的栅极和第一复位端STD连接以接收第一复位信号，第二十晶体管M20的第一极和第二节点Q2连接，第二十晶体管M20的第二极和第一电压端VGL1连接以接收第一电压。
第一总复位电路191包括第二十一晶体管M21，第二总复位电路192包括第二十二晶体管M22。第二十一晶体管M21的栅极和第二复位端TRST连接以接收第二复位信号，第二十一晶体管M21的第一极和第一节点Q1连接，第二十一晶体管M21的第二极和第一电压端VGL1连接以接收第一电压。第二十二晶体管M22的的栅极和第二复位端TRST连接以接收第二复位信号，第二十二晶体管M22的第一极和第二节点Q2连接，第二十二晶体管M22的第二极和第一电压端VGL1连接以接收第一电压。
如前所述，在本公开的实施例提供的移位寄存器单元10中，可以利用第一电容C1维持第一消隐节点H1处的电位，利用第二电容C2维持第一节点Q1处的电位，利用第三电容C3维持第二节点Q2处的电位。第一电容C1、第二电容C2和第三电容C3可以是通过工艺制程制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容的各个电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现，或者在一些示例中，通过设计电路布线参数使得第一电容C1、第二电容C2和第三电容C3也可以通过各个器件之间的寄生电容实现。第一电容C1、第二电容C2和第三电容C3的连接方式不局限于上面描述的方式，也可以为其他适用的连接方式，只要能存储写入到第一消隐节点H1、第一节点Q1和第二节点Q2的电平即可。
需要说明的是，在本公开的一些实施例中，VGL1即表示第一电压端又表示第一电压，VDD即表示第二电压端又表示第二电压，VGL2即表示第三电压端又表示第三电压。第一电压VGL1和第三电压VGL2例如为低电平，第二电压VDD例如为高电平，例如，第二电压VDD大于第一电压VGL1和第三电压VGL2，以下各实施例与此相同，不再赘述。
另外，需要说明的是，在本公开的一些实施例中，高电平和低电平是相对而言的。高电平表示一个较高的电压范围(例如，高电平可以采用5V、10V或其他合适的电压)，且多个高电平可以相同也可以不同。类似地，低电平表示一个较低的电压范围(例如，低电平可以采用0V、-5V、-10V或其他合适的电压)，且多个低电平可以相同也可以不同。例如，高电平的最小值比低电平的最大值大。
需要说明的是，在本公开的一些实施例中，对一个节点(例如第一节点Q1等)的电平进行控制，包括对该节点进行充电以拉高该节点的电平，或者 对该节点进行放电以拉低该节点的电平。例如，可以设置一个与该节点电连接的电容，对该节点进行充电即表示对与该节点电连接的电容进行充电；类似地，对该节点进行放电即表示对与该节点电连接的电容进行放电；通过该电容可以维持该节点的高电平或低电平。
需要说明的是，本公开中，GOUT1既表示扫描信号输出端又表示第一输出信号，GOUT2既表示第二输出端又表示第二输出信号，CLKA即表示第一时钟信号端又表示第一时钟信号，CLKD即表示第二时钟信号端又表示第二时钟信号，CLKE1即表示第三时钟信号端又表示第三时钟信号，CLKE2即表示第四时钟信号端又表示第四时钟信号，以下实施例与此相同，不再赘述。
在本公开的实施例中，例如，当各个电路实现为N型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如截止)。
又例如，当各个电路实现为P型晶体管时，术语“上拉”表示对一个节点或一个晶体管的一个电极进行放电，以使得该节点或该电极的电平的绝对值降低，从而实现相应晶体管的操作(例如导通)；“下拉”表示对一个节点或一个晶体管的一个电极进行充电，以使得该节点或该电极的电平的绝对值升高，从而实现相应晶体管的操作(例如截止)。
需要注意的是，在本公开的各个实施例的说明中，第一节点Q1、第二节点Q2、第三节点Q3、第四节点Q4、第一消隐节点H1和第二消隐节点H2并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点。
本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极。此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。当晶体管为P型晶体管时，开启电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)， 关闭电压为高电平电压(例如，5V、10V或其他合适的电压)；当晶体管为N型晶体管时，开启电压为高电平电压(例如，5V、10V或其他合适的电压)，关闭电压为低电平电压(例如，0V、-5V、-10V或其他合适的电压)。
另外，本公开的实施例中的晶体管均以N型晶体管为例进行说明，此时，晶体管的第一极是漏极，第二极是源极。需要说明的是，本公开包括但不限于此。例如，本公开的实施例提供的移位寄存器单元10中的一个或多个晶体管也可以采用P型晶体管，此时，晶体管第一极是源极，第二极是漏极，只需将选定类型的晶体管的各极参照本公开的实施例中的相应晶体管的各极相应连接，并且使相应的电压端提供对应的高电压或低电压即可。当采用N型晶体管时，可以采用氧化铟镓锌(Indium Gallium Zinc Oxide，IGZO)作为薄膜晶体管的有源层，相对于采用低温多晶硅(Low Temperature Poly Silicon，LTPS)或非晶硅(例如氢化非晶硅)作为薄膜晶体管的有源层，可以有效减小晶体管的尺寸以及防止漏电流。
本公开的至少一实施例还提供一种栅极驱动电路20，如图8所示，该栅极驱动电路20包括多个级联的移位寄存器单元10，其中任意一个或多个移位寄存器单元10可以采用本公开任一实施例提供的移位寄存器单元10的结构或其变型。例如，在图8所示的示例中，以移位寄存器单元10采用图7所示的移位寄存器单元10的结构为例进行说明。图8中的A1、A2、A3和A4表示级联的四个移位寄存器单元10。
例如，如图8所示，每个移位寄存器单元21包括扫描信号输出端GOUT1、第二输出端GOUT2和移位输出端CR，以分别输出第一输出信号(包括移位信号CR和扫描输出信号GOUT1)和第二输出信号GOUT2。需要注意的是，为了表述清楚、简洁，下面将扫描输出信号GOUT1称作第一输出信号。
当该栅极驱动电路20用于驱动显示面板10中的多行子像素单元时，第一输出信号GOUT1和第二输出信号GOUT2可以分别驱动显示面板10中的一行子像素单元。例如，第一级移位寄存器单元A1中的扫描信号输出端GOUT1<1>和第二输出端GOUT2<2>可以通过与其连接的栅线分别驱动显示面板10的第1行子像素单元和第2行子像素单元，第二级移位寄存器单元A2中的扫描信号输出端GOUT1<3>和第二输出端GOUT2<4>可以通过与其连接的栅线分别驱动显示面板10的第3行子像素单元和第4行子像素单元， 以此类推。
为了表示清楚、简洁，例如，在图8中，CR<1>表示第1级移位寄存器单元的移位输出端，CR<3>表示第2级移位寄存器单元的移位输出端，CR<5>表示第3级移位寄存器单元的移位输出端，CR<7>表示第4级移位寄存器单元的移位输出端，以此类推。
例如，如图8所示，栅极驱动电路20包括第一子时钟信号线CLKD_1、第二子时钟信号线CLKD_3、第三子时钟信号线CLKD_5和第四子时钟信号线CLKD_7。例如，第4k-3(k为大于零的整数)级移位寄存器单元中的第二时钟信号端CLKD与第一子时钟信号线CLKD_1连接以接收第4k-3级移位寄存器单元的第二时钟信号CLKD；第4k-2级移位寄存器单元中的第二时钟信号端CLKD与第二子时钟信号线CLKD_3连接以接收第4k-2级移位寄存器单元的第二时钟信号CLKD；第4k-1级移位寄存器单元中的第二时钟信号端CLKD与第三子时钟信号线CLKD_5连接以接收第4k-1级移位寄存器单元的第二时钟信号CLKD；第4k级移位寄存器单元中的第二时钟信号端CLKD与第四子时钟信号线CLKD_7连接以接收第4k级移位寄存器单元的第二时钟信号CLKD。
如上所述，在移位寄存器单元10进行级联时，只需要向每一级移位寄存器单元10中的第二时钟信号端CLKD提供第二时钟信号即可，该第二时钟信号可以作为移位信号CR输出以完成扫描移位。
如图8所示，栅极驱动电路20还包括第五子时钟信号线CLKE_1至第十二子时钟信号线CLKE_8。
第4k-3级移位寄存器单元中的第三时钟信号端CLKE1和第五子时钟信号线CLKE_1连接以接收第4k-3级移位寄存器单元的第三时钟信号CLKE1，第4k-3级移位寄存器单元中的第四时钟信号端CLKE2和第六子时钟信号线CLKE_2连接以接收第4k-3级移位寄存器单元的第四时钟信号CLKE2。
第4k-2级移位寄存器单元中的第三时钟信号端CLKE1和第七子时钟信号线CLKE_3连接以接收第4k-2级移位寄存器单元的第三时钟信号CLKE1，第4k-2级移位寄存器单元中的第四时钟信号端CLKE2和第八子时钟信号线CLKE_4连接以接收第4k-2级移位寄存器单元的第四时钟信号CLKE2。
第4k-1级移位寄存器单元中的第三时钟信号端CLKE1和第九子时钟信 号线CLKE_5连接以接收第4k-1级移位寄存器单元的第三时钟信号CLKE1，第4k-1级移位寄存器单元中的第四时钟信号端CLKE2和第十子时钟信号线CLKE_6连接以接收第4k-1级移位寄存器单元的第四时钟信号CLKE2。
第4k级移位寄存器单元中的第三时钟信号端CLKE1和第十一子时钟信号线CLKE_7连接以接收第4k级移位寄存器单元的第三时钟信号CLKE1，第4k级移位寄存器单元中的第四时钟信号端CLKE2和第十二子时钟信号线CLKE_8连接以接收第4k级移位寄存器单元的第四时钟信号CLKE2。
如上所述，通过第五子时钟信号线CLKE_1至第十二子时钟信号线CLKE_8共8条时钟信号线向各级移位寄存器单元10提供逐行输出的驱动信号(具体信号时序可以参考图9)。即本公开的实施例提供的栅极驱动电路20可以采用8CLK的时钟信号，这样可以使得该栅极驱动电路20输出的驱动信号的波形交叠，例如可以增加每一行子像素单元的预充电时间，从而使得该栅极驱动电路20可以适用于高频率的扫描显示。需要注意的是。信号线的条数还可以是10、12、14等更多条，本公开的实施例对此不作限制。
如图8所示，第十三子时钟信号线CLKA_1、总复位信号线TRST_1、选择控制信号线OE_1和触发信号线STU_1。
如图8所示，在本实施例中，触发信号线STU_1和第1级移位寄存器单元A1和第2级移位寄存器单元A2的输入端STU连接以提供输入信号STU，总复位信号线TRST_1和各级移位寄存器单元10的第二复位端TRST连接以提供全局复位信号TRST。选择控制信号线OE_1和各级移位寄存器单元10的选择控制端OE连接以接收选择控制信号，第十三子时钟信号线CLKA_1和各级移位寄存器单元10的第一时钟信号端CLKA连接以接收第一时钟信号。
如图8所示，除第1级移位寄存器单元10和第2级移位寄存器单元10外，其余各级移位寄存器单元10的输入端STU和与其相隔一级的上级移位寄存器单元10的移位输出端CR连接以接收移位信号CR并作为输入信号STU。除了最后2级移位寄存器单元10外，其余各级移位寄存器单元10中的第一复位端STD和与其相隔一级的下级移位寄存器单元10的移位输出端CR连接以接收移位信号CR并作为第一复位信号STD。
需要说明的是，图8中所示的级联关系仅是一种示例，根据本公开的描 述，还可以根据实际情况采用其它级联方式，本公开的实施例对此不作限制。
另需要注意的是，为了表示清楚、简洁，图8中仅示意性的第1级移位寄存器单元A1、第2级移位寄存器单元A2、第三级移位寄存器单元A3和第四级移位寄存器单元A4，还包括依次级联下去的多个移位寄存器单元10，本公开的实施例对此不作限制，且其级联方式可以参考上面描述的级联方式，在此不再赘述。
例如，该栅极驱动电路20还包括多条电压线，以向各级移位寄存器单元提供多个电压信号，例如包括相对的高电平信号VDD以及低电平信号VGL1、VGL2等。
例如，当采用该栅极驱动电路20驱动一显示面板时，可以将该栅极驱动电路20设置于显示面板的一侧。例如，该显示面板包括多行栅线，栅极驱动电路20中的各级移位寄存器单元的扫描信号输出端GOUT1和第二输出端GOUT2可以配置为依序和多行栅线连接，以用于输出驱动信号。当然，还可以分别在显示面板的两侧设置该栅极驱动电路20，以实现双边驱动，本公开的实施例对栅极驱动电路20的设置方式不作限制。
例如，在一些示例中，图8所示的栅极驱动电路20中的移位寄存器单元10可以采用图5中所示的电路结构，图9示出了图8所示的栅极驱动电路20工作时的信号时序图。
在图9中，H1<1>、H1<2>和H1<3>分别表示第1级移位寄存器单元A1、第2级移位寄存器单元A2和第3级移位寄存器单元A3中的第一消隐节点。
Q1<1>表示第1级移位寄存器单元A1中的第一节点，控制第1级移位寄存器单元A1的扫描信号输出端GOUT1<1>的输出，Q2<1>表示第1级移位寄存器单元A1中的第二节点，控制第1级移位寄存器单元A1的第二输出端GOUT2<2>的输出；Q1<2>表示第2级移位寄存器单元A2中的第一节点，控制第2级移位寄存器单元A2的扫描信号输出端GOUT1<3>的输出，Q2<2>表示第2级移位寄存器单元A2中的第二节点，控制第2级移位寄存器单元A2的第二输出端GOUT2<4>的输出；Q1<3>表示第3级移位寄存器单元A3中的第一节点，控制第3级移位寄存器单元A3的扫描信号输出端GOUT1<5>的输出，Q2<3>表示第3级移位寄存器单元A3中的第二节点，控制第3级移位寄存器单元A3的第二输出端GOUT2<6>的输出。括号中的数字表示该 节点对应的移位寄存器单元的级数，以下各实施例与此相同，不再赘述。
GOUT1<1>表示第1级移位寄存器单元A1的扫描信号输出端以及其输出的第一输出信号，GOUT2<2>表示第1级移位寄存器单元A1的第二输出端和其输出的第二输出信号。类似地，GOUT1<3>和GOUT2<4>分别表示第2级移位寄存器单元A2的扫描信号输出端及其输出的第一输出信号和第二输出端及其输出的第二输出信号，GOUT1<5>和GOUT2<6>分别表示第3级移位寄存器单元A3的扫描信号输出端及其输出的第一输出信号和第二输出端及其输出的第二输出信号,GOUT1<7>表示第4级移位寄存器单元A4的扫描信号输出端及其输出的第一输出信号。括号中的数字表示该输出端对应的显示面板中子像素单元的行数，以下各实施例与此相同，不再赘述。
CR<1>表示第1级移位寄存器单元的移位信号，CR<3>表示第2级移位寄存器单元的移位信号，CR<5>表示第3级移位寄存器单元的移位信号，CR<7>表示第4级移位寄存器单元的移位信号，以此类推。括号中的数字表示该输出端对应的显示面板中子像素单元的行数，以下各实施例与此相同，不再赘述。
1F表示第一帧，包括显示时段和消隐时段，显示时段用于驱动显示面板显示，消隐时段用于对显示面板中的像素电路进行补偿。图9所示的信号时序图中的信号电平只是示意性的，不代表真实电平值。
下面结合图9中的信号时序图以及图5所示的移位寄存器单元10，对图8中所示的栅极驱动电路20的工作原理进行说明。
在第一帧1F的显示时段中，针对第1级移位寄存器单元A1的工作过程描述如下。
在第一阶段t1中，触发信号线提供高电平，第1级移位寄存器单元的输入端端STU和第2级移位寄存器单元的输入端端STU输入高电平，第八晶体管M8和第九晶体管M9导通，所以第二电压端VDD输入的高电平可以通过第八晶体管M8对第一节点Q1<1>进行充电，使得第一节点Q1<1>被上拉至第一高电平并被第二电容C2保持。同时，由于第九晶体管M9导通，第二节点Q2<1>与第一节点Q1<1>连接，因此，第二节点Q2<1>也被上拉至第一高电平，并被第三电容C3存储。
在此阶段，第五晶体管M5和第六晶体管M6在第一节点Q1<1>的控制 下导通，但由于第二时钟信号端CLKD(与第一子时钟信号线CLKD_1连接)和第三时钟信号端CLKE1(与第五子时钟信号线CLKE_1连接)在此阶段输入低电平信号，所以移位输出端CR<1>和扫描信号输出端GOUT1<1>均输出低电平信号。第七晶体管M7在第二节点Q2<1>的控制下导通，但由于第四时钟信号端CLKE2(与第六子时钟信号线CLKE_2连接)在此阶段输入低电平信号，所以第二输出端GOUT2<2>输出低电平信号。
在此阶段，完成对第一节点Q1<1>和第二节点Q2<1>的预充电。
第2级移位寄存器单元在此阶段的工作原理与此类似，不再赘述。
在第二阶段t2中，第二时钟信号端CLKD(与第一子时钟信号线CLKD_1)和第三时钟信号端CLKE1(与第五子时钟信号线CLKE_1)输入高电平信号，第一节点Q1<1>的电位由于第二电容C2的自举效应而进一步被拉高至第二高电平，所以第五晶体管M5和第六晶体管M6保持导通，从而移位输出端CR<1>和扫描信号输出端GOUT1<1>均输出高电平信号。
例如，从移位输出端CR<1>输出的高电平信号可以用于上下级移位寄存器单元的扫描移位，例如，用作上一级移位寄存器单元的复位信号或下一级移位寄存器单元的输入信号，而从扫描信号输出端GOUT1<1>和第二输出端OUT2输出的高电平信号可以用于驱动显示面板中的第1行子像素单元和第2行子像素单元进行显示。
在第三阶段t3中，第二时钟信号端CLKD、第三时钟信号端CLKE1和第四时钟信号端CLKE2(与第六子时钟信号线CLKE_2)输入高电平信号，第一节点Q1<1>的继续保持高电平，所以移位输出端CR<1>和扫描信号输出端GOUT1<1>均输出高电平信号。同时，由于第四时钟信号端CLKE2输入高电平信号，第二节点Q2<1>电位由于第三电容C3的自举效应而进一步被拉高至第二高电平，所以第七晶体管M7保持导通，从而第二输出端GOUT2<2>输出高电平信号。
在此阶段，选择控制信号线OE_1提供高电平，因此，各级移位寄存器单元的选择控制端OE输入高电平，所以第一晶体管M1导通，使得第一节点Q1<1>和第一消隐节点H1<1>连接，由于第一节点Q1<1>在此阶段为高电平，所以第一消隐节点H1<1>也被上拉至高电平，并被第一电容C1存储。第2级移位寄存器单元的第一消隐节点H1<1>的上拉过程与此类似，不再赘 述。
在第四阶段t4中，第二时钟信号端CLKD和第三时钟信号端CLKE1输入低电平信号，由于此时第一节点Q1<1>保持高电平，所以第五晶体管M5和第六晶体管M6保持导通，从而移位输出端CR<1>和扫描信号输出端GOUT1<1>均输出低电平信号。由于第二电容C2的自举作用，所以第一节点Q1<1>的电位也会下降。
在第五阶段t5，由于第1级移位寄存器单元A1的第一复位端STD和第3级移位寄存器单元A3的移位输出端CR<5>连接，此时第3级移位寄存器单元A3的移位输出端CR<5>输出高电平，所以第1级移位寄存器单元A1的第一复位端STD输入高电平，第十九晶体管M19和第二十晶体管M20导通，第一节点Q1<1>和第二节点Q2<1>被下拉至低电平，完成对第一节点Q1<1>和第二节点Q2<1>的复位。由于第一节点Q1<1>和第二节点Q2<1>为低电平，第十一晶体管M11和第十三晶体管M13关闭，同时第二电压端输入的高电平可以将第三节点Q3<1>和第四节点Q4<1>上拉，第三节点Q3<1>和第四节点Q4<1>被上拉至高电平，所以第十四晶体管M14和第十五晶体管M15导通，以进一步对第一节点Q1<1>和第二节点Q2<1>进行复位。同时第十六晶体管M16、第十七晶体管M17和第十八晶体管M18也导通，从而可以对移位输出端CR<1>、扫描信号输出端GOUT1<1>和第二输出端GOUT2<2>进一步下拉复位。
第1级移位寄存器单元驱动显示面板中第一行的子像素和第二行子像素完成显示后，依次类推，第二级、第三级等移位寄存器单元逐行驱动显示面板中的子像素单元完成一帧的显示驱动。至此，一帧的显示时段结束。
例如，第一消隐节点H1<1>的高电位可以一直保持到第一帧1F的消隐时段中。以下实施例中以在第一帧1F中需要对第2行子像素单元进行补偿为例进行说明，则在第一帧1F的消隐时段中进行如下操作。
在第六阶段t6中，由于第一消隐节点H1<1>的高电位，所以第二晶体管M2导通，使得第一时钟信号端CLKA与第二消隐节点H2<1>连接。在此阶段，第十三子时钟信号线CLKA_1提供高电平，由于第一时钟信号端CLKA和第十三子时钟信号线CLKA_1连接，所以在此阶段第一时钟信号端CLKA输入为高电平，所以在此阶段，第二消隐节点H2<1>为高电平，同时，第三 晶体管M3和第四晶体管M4响应于第一时钟信号端CLKA接收的高电平均导通，使得第二消隐节点H2<1>与第一节点Q1<1>和第二节点Q2<2>连接，从而将第一节点Q1<1>和第二节点Q2<2>拉高至第一高电平。
在第七阶段t7中，第六子时钟信号线CLKE_2提供高电平，第1级移位寄存器单元A1的第四时钟信号端CLKE2(与第六子时钟信号线CLKE_2连接)输入高电平信号，第二节点Q2<1>的电位由于第三电容C3的自举作用而进一步被拉高至第二电平，第1级移位寄存器单元A1的第七晶体管M7导通，第1级移位寄存器单元A1的第四时钟信号端CLKE2输入的高电平信号可以输出至第二输出端GOUT2<2>。例如，在此阶段，第二输出端GOUT2<2>输出的信号可以用于驱动显示面板中的子像素单元中的感测晶体管，以实现外部补偿。
在第八阶段t8中，第1级移位寄存器单元A1的第二时钟信号端CLKD(与第一子时钟信号线CLKD_1连接)、第三时钟信号端CLKE1(与第五子时钟信号线CLKE_1连接)和第四时钟信号端CLKE2(与第六子时钟信号线CLKE_2连接)输入的信号从高电平变为低电平，第二节点Q2<2>的电位由于第三电容C3的自举作用被下拉至第一高电平。
在第九阶段t9中，选择控制信号线OE_1和总复位信号线TRST_1提供高电平，由于各级移位寄存器单元的选择控制端OE均和选择控制信号线OE_1连接，各级移位寄存器单元的第二复位端TRST均和总复位信号线TRST_1连接，所以可以对各级移位寄存器单元的第一消隐节点H1以及第一节点Q1和第二节点Q2进行复位。
至此，第一帧的驱动时序结束。后续在第二帧、第三帧等更多阶段中对栅极驱动电路的驱动可以参考上述描述，这里不再赘述。
需要说明是，在上述对随机补偿的工作原理进行描述时，是以第一帧1F的消隐时段输出对应于显示面板的第1行子像素单元和第2行像素单元的驱动信号为例进行说明的，本公开的实施例对此不作限定。例如，当在某一帧的消隐时段中需要输出对应于显示面板的第n行子像素单元和第n+1行子像素单元的驱动信号时，则需要在该帧的消隐时段中将第n/2级移位寄存器单元的第一节点Q1和第二节点Q2的电位上拉至高电平，同时在该帧的消隐时段中，通过第n/2级移位寄存器单元的的第三时钟信号端CLKE1或第四时钟 信号端CLKE2输入高电平信号，n为大于零的偶数。
另外，在本公开的实施例中，两个信号时序相同指的是位于高电平的时间同步，而不要求两个信号的幅值相同。
本公开至少一实施例还提供一种显示装置1，如图10所示，该显示装置1包括本公开实施例提供的栅极驱动电路20以及多个呈阵列排布的子像素单元410。例如，该显示装置1还包括显示面板40，多个子像素单元410构成的像素阵列设置在显示面板40中。
栅极驱动电路20中的每一个移位寄存器单元10中的第一输出端OUT1中的扫描信号输出端GOUT1和第二输出端GOUT2分别和不同行的子像素单元410电连接，例如，栅极驱动电路20通过栅线GL与子像素单元410电连接。栅极驱动电路20用于提供驱动信号至像素阵列，例如该驱动信号可以驱动子像素单元410中的扫描晶体管和感测晶体管。
例如，该显示装置1还可以包括数据驱动电路30，该数据驱动电路30用于提供数据信号至像素阵列。例如，数据驱动电路30通过数据线DL与子像素单元410电连接。
需要说明的是，本实施例中的显示装置1可以为：液晶面板、液晶电视、显示器、OLED面板、OLED电视、电子纸显示装置、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
本公开的实施例提供的显示装置1的技术效果可以参考上述实施例中关于栅极驱动电路20的相应描述，这里不再赘述。
本公开至少一实施例还提供一种驱动方法，可以用于驱动本公开的实施例提供的移位寄存器单元10，多个该移位寄存器单元10可以级联构建本公开至少一实施例的栅极驱动电路，该栅极驱动电路用于驱动显示面板显示至少一帧画面。该驱动方法包括用于一帧的显示时段和消隐时段。
在显示时段，输入电路110响应于输入端STU输入的输入信号对第一节点Q1充电，第一控制电路120响应于输入信号以及第一节点Q1的电平，对第二节点Q2充电，消隐控制电路130在第一节点Q1的电平的控制下，对消隐控制电路130的第一消隐节点H1进行充电；第一输出电路141在第一节点Q1的电平的控制下，在第一输出端OUT1输出第一输出信号，第二输出电路142在第二节点Q2的电平的控制下，在第二输出端GOUT2输出第二 输出信号。
在消隐阶段，消隐控制电路130在选择控制信号、第一时钟信号和第一消隐节点H1的电平的控制下，对第一节点Q1和第二节点Q2进行充电；第一输出电路141在第一节点Q1的电平的控制下，在第一输出端OUT1输出第一输出信号，第二输出电路142在第二节点Q2的电平的控制下，在第二输出端GOUT2输出第二输出信号。
需要说明的是，关于本公开的实施例提供的移位寄存器单元的驱动方法的详细描述和技术效果可以参考本公开的实施例中对于移位寄存器单元10和栅极驱动电路20的工作原理的描述，这里不再赘述。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以权利要求的保护范围为准。

Claims (21)

  1. 一种移位寄存器单元，包括输入电路、第一控制电路、消隐控制电路、第一输出电路和第二输出电路；其中，
    所述输入电路与输入端连接，且配置为响应于所述输入端输入的输入信号对第一节点的电平进行控制；
    所述第一控制电路与所述输入端、所述第一节点和第二节点连接，且配置为响应于所述输入端输入的所述输入信号以及所述第一节点的电平，对所述第二节点的电平进行控制；
    所述消隐控制电路与所述第一节点和所述第二节点连接，且配置为在选择控制信号、第一时钟信号和所述第一节点的电平的控制下，对所述第一节点的电平和所述第二节点的电平进行控制；
    所述第一输出电路包括第一输出端，且所述第一输出电路配置为在所述第一节点的电平的控制下，在所述第一输出端输出第一输出信号；
    所述第二输出电路包括第二输出端，且所述第二输出电路配置为在所述第二节点的电平的控制下，在所述第二输出端输出第二输出信号。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述消隐控制电路包括第一控制子电路、第二控制子电路和第三控制子电路；其中，
    所述第一控制子电路与所述第一节点和第一消隐节点连接，且配置为在所述选择控制信号和所述第一节点的电平的控制下，对所述第一消隐节点的电平进行控制；
    所述第二控制子电路与所述第一消隐节点和第二消隐节点连接，且配置为在所述第一消隐节点的电平的控制下，对所述第二消隐节点的电平进行控制；
    所述第三控制子电路与所述第二消隐节点、所述第一节点和所述第二节点连接，且配置为在所述第一时钟信号的控制下，对所述第一节点和所述第二节点的电平进行控制。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一控制子电路包括第一晶体管和第一电容，所述第二控制子电路包括第二晶体管，所述第三控制子电路包括第三晶体管和第四晶体管；其中，
    所述第一晶体管的栅极和选择控制端连接以接收所述选择控制信号，所述第一晶体管的第一极和所述第一节点连接，所述第一晶体管的第二极和所述第一消隐节点连接；
    所述第一电容的第一极和所述第一消隐节点连接，所述第一电容的第二极和第一电压端连接以接收第一电压；
    所述第二晶体管的栅极和所述第一消隐节点连接，所述第二晶体管的第一极和第一时钟信号端连接以接收所述第一时钟信号，所述第二晶体管的第二极和所述第二消隐节点连接；
    所述第三晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第三晶体管的第一极和所述第二消隐节点连接，所述第三晶体管的第二极和所述第一节点连接；
    所述第四晶体管的栅极和所述第一时钟信号端连接以接收所述第一时钟信号，所述第四晶体管的第一极和所述第二消隐节点连接，所述第四晶体管的第二极和所述第二节点连接。
  4. 根据权利要求1-3任一所述的移位寄存器单元，其中，所述第一输出端包括移位输出端和至少一个扫描信号输出端。
  5. 根据权利要求4所述的移位寄存器单元，其中，在所述第一输出端包括移位输出端和一个扫描信号输出端的情形下，所述第一输出电路包括第五晶体管、第六晶体管和第二电容；其中，
    所述第五晶体管的栅极和所述第一节点连接，所述第五晶体管的第一极和第二时钟信号端连接以接收第二时钟信号并作为所述第一输出信号，所述第五晶体管的第二极和所述移位输出端连接；
    所述第六晶体管的栅极和所述第一节点连接，所述第六晶体管的第一极和第三时钟信号端连接以接收第三时钟信号并作为所述第一输出信号，所述第六晶体管的第二极和所述扫描信号输出端连接；
    所述第二电容的第一极和所述第一节点连接，所述第二电容的第二极和所述第五晶体管或所述第六晶体管的第二极连接；
    其中，所述第二时钟信号和所述第三时钟信号在显示时段的时序相同。
  6. 根据权利要求1-5任一所述的移位寄存器单元，其中，所述第二输出电路包括第七晶体管和第三电容；其中，
    所述第七晶体管的栅极和所述第二节点连接，所述第七晶体管的第一极和第四时钟信号端连接以接收第四时钟信号并作为所述第二输出信号，所述第七晶体管的第二极和所述第二输出端连接；
    所述第三电容的第一极和所述第二节点连接，所述第三电容的第二极和所述第二输出端连接。
  7. 根据权利要求1-6任一所述的移位寄存器单元，其中，所述输入电路包括第八晶体管，
    其中，所述第八晶体管的栅极和所述输入端连接以接收所述输入信号，所述第八晶体管的第一极和第二电压端连接以接收第二电压，所述第八晶体管的第二极和所述第一节点连接。
  8. 根据权利要求1-7任一所述的移位寄存器单元，其中，所述第一控制电路包括第九晶体管，
    其中，所述第九晶体管的栅极和所述输入端连接以接收所述输入信号，所述第九晶体管的第一极和所述第一节点连接，所述第九晶体管的第二极和所述第二节点连接。
  9. 根据权利要求1-8任一所述的移位寄存器单元，还包括第二控制电路和第三控制电路；其中，
    所述第二控制电路与所述第一节点和第三节点连接，且配置为在所述第一节点的电平的控制下，对所述第三节点的电平进行控制；
    所述第三控制电路与所述第二节点和第四节点连接，且配置为在所述第二节点的电平的控制下，对所述第四节点的电平进行控制。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第二控制电路包括第十晶体管和第十一晶体管，所述第三控制电路包括第十二晶体管和第十三晶体管；其中，
    所述第十晶体管的栅极和第一极连接，且与第二电压端连接以接收第二电压，所述第十晶体管的第二极和所述第三节点连接；
    所述第十一晶体管的栅极和所述第一节点连接，所述第十一晶体管的第一极和所述第三节点连接，所述第十一晶体管的第二极和第一电压端连接以接收第一电压；
    所述第十二晶体管的栅极和第一极连接，且与所述第二电压端连接以接 收所述第二电压，所述第十二晶体管的第二极和所述第四节点连接；
    所述第十三晶体管的栅极和所述第二节点连接，所述第十三晶体管的第一极和所述第四节点连接，所述第十三晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  11. 根据权利要求9或10所述的移位寄存器单元，还包括第一节点降噪电路和第二节点降噪电路；其中，
    所述第一节点降噪电路与所述第一节点和所述第三节点连接，且配置为在所述第三节点的电平的控制下，对所述第一节点降噪；
    所述第二节点降噪电路与所述第二节点和所述第四节点连接，且配置为在所述第四节点的电平的控制下，对所述第二节点进行降噪。
  12. 根据权利要求11所述的移位寄存器单元，其中，所述第一节点降噪电路包括第十四晶体管，所述第二节点降噪电路包括第十五晶体管；其中，
    所述第十四晶体管的栅极和所述第三节点连接，所述第十四晶体管的第一极和所述第一节点连接，所述第十四晶体管的第二极和第一电压端连接以接收第一电压；
    所述第十五晶体管的栅极和所述第四节点连接，所述第十五晶体管的第一极和所述第二节点连接，所述第十五晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  13. 根据权利要求9-12任一所述的移位寄存器单元，还包括第一输出降噪电路和第二输出降噪电路；其中，
    所述第一输出降噪电路与所述第三节点和所述第一输出端连接，且配置为在所述第三节点的电平的控制下，对所述第一输出端降噪；
    所述第二输出降噪电路与所述第四节点和所述第二输出端连接，且配置为在所述第四节点的电平的控制下，对所述第二输出端降噪。
  14. 根据权利要求13所述的移位寄存器单元，其中，在所述第一输出端包括移位输出端和一个扫描信号输出端的情形下，所述第一输出降噪电路包括第十六晶体管和第十七晶体管，所述第二输出降噪电路包括第十八晶体管；其中，
    所述第十六晶体管的栅极和所述第三节点连接，所述第十六晶体管的第一极和所述移位输出端连接，所述第十六晶体管的第二极和第一电压端连接 以接收第一电压；
    所述第十七晶体管的栅极和所述第三节点连接，所述第十七晶体管的第一极和所述扫描信号输出端连接，所述第十七晶体管的第二极和第三电压端连接以接收第三电压；
    所述第十八晶体管的栅极和所述第四节点连接，所述第十八晶体管的第一极和所述第二输出端连接，所述第十八晶体管的第二极和所述第三电压端连接以接收所述第三电压。
  15. 根据权利要求9-14任一所述的移位寄存器单元，还包括第一复位电路和第二复位电路；其中，
    所述第一复位电路与所述第一节点和第一复位端连接，且配置为响应于所述第一复位端提供的第一复位信号，对所述第一节点复位；
    所述第二复位电路与所述第二节点和所述第一复位端连接，且配置为响应于所述第一复位信号，对所述第二节点复位。
  16. 根据权利要求15所述的移位寄存器单元，其中，所述第一复位电路包括第十九晶体管，所述第二复位电路包括第二十晶体管；其中，
    所述第十九晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第十九晶体管的第一极和所述第一节点连接，所述第十九晶体管的第二极和第一电压端连接以接收第一电压；
    所述第二十晶体管的栅极和所述第一复位端连接以接收所述第一复位信号，所述第二十晶体管的第一极和所述第二节点连接，所述第二十晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  17. 根据权利要求9-16任一所述的移位寄存器单元，还包括第一总复位电路和第二总复位电路；其中，
    所述第一总复位电路与所述第一节点和第二复位端连接，且配置为响应于所述第二复位端提供的第二复位信号，对所述第一节点复位；
    所述第二总复位电路与所述第二节点和所述第二复位端连接，且配置为响应于所述第二复位信号，对所述第二节点复位。
  18. 根据权利要求17所述的移位寄存器单元，其中，所述第一总复位电路包括第二十一晶体管，所述第二总复位电路包括第二十二晶体管；其中，
    所述第二十一晶体管的栅极和所述第二复位端连接以接收所述第二复位 信号，所述第二十一晶体管的第一极和所述第一节点连接，所述第二十一晶体管的第二极和第一电压端连接以接收第一电压；
    所述第二十二晶体管的的栅极和所述第二复位端连接以接收所述第二复位信号，所述第二十二晶体管的第一极和所述第二节点连接，所述第二十二晶体管的第二极和所述第一电压端连接以接收所述第一电压。
  19. 一种栅极驱动电路，包括如权利要求1-18任一所述的移位寄存器单元。
  20. 一种显示装置，包括如权利要求19所述的栅极驱动电路以及多个呈阵列排布的子像素单元，
    其中，所述栅极驱动电路中的每一个移位寄存器单元中的所述第一输出端和所述第二输出端分别和位于不同行的子像素单元电连接。
  21. 一种如权利要求1-18任一所述的移位寄存器单元的驱动方法，包括用于一帧的显示时段和消隐时段，其中，
    在所述显示时段，
    所述输入电路响应于所述输入端输入的输入信号对所述第一节点充电，所述第一控制电路响应于所述输入信号以及所述第一节点的电平，对所述第二节点充电，所述消隐控制电路在所述第一节点的电平的控制下，对所述消隐控制电路的第一消隐节点进行充电；
    所述第一输出电路在所述第一节点的电平的控制下，在所述第一输出端输出所述第一输出信号，所述第二输出电路在所述第二节点的电平的控制下，在所述第二输出端输出所述第二输出信号；
    在所述消隐阶段，
    所述消隐控制电路在所述选择控制信号、所述第一时钟信号和所述第一消隐节点的电平的控制下，对所述第一节点和所述第二节点进行充电；
    所述第一输出电路在所述第一节点的电平的控制下，在所述第一输出端输出所述第一输出信号，所述第二输出电路在所述第二节点的电平的控制下，在所述第二输出端输出所述第二输出信号。
PCT/CN2019/099801 2019-08-08 2019-08-08 移位寄存器单元及驱动方法、栅极驱动电路和显示装置 WO2021022554A1 (zh)

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US16/957,161 US11244595B2 (en) 2019-08-08 2019-08-08 Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
CN201980001296.XA CN112639947B (zh) 2019-08-08 2019-08-08 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
CN202210028284.XA CN114300029A (zh) 2019-08-08 2019-08-08 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
PCT/CN2019/099801 WO2021022554A1 (zh) 2019-08-08 2019-08-08 移位寄存器单元及驱动方法、栅极驱动电路和显示装置
US17/555,695 US11688318B2 (en) 2019-08-08 2021-12-20 Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
US18/313,576 US12057046B2 (en) 2019-08-08 2023-05-08 Shift register unit, driving method, gate driving circuit, and display device
US18/754,789 US20240346973A1 (en) 2019-08-08 2024-06-26 Shift register unit, driving method, gate driving circuit, and display device

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US17/555,695 Continuation-In-Part US11688318B2 (en) 2019-08-08 2021-12-20 Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device
US17/555,695 Continuation US11688318B2 (en) 2019-08-08 2021-12-20 Shift register unit comprising input circuit, first control circuit, blanking control circuit, first output circuit, and second output circuit, driving method, gate driving circuit, and display device

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