TWI269567B - Method employed by a base station for transferring data and base station/user equipment having hybrid parallel/serial bus interface - Google Patents
Method employed by a base station for transferring data and base station/user equipment having hybrid parallel/serial bus interface Download PDFInfo
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- TWI269567B TWI269567B TW091134142A TW91134142A TWI269567B TW I269567 B TWI269567 B TW I269567B TW 091134142 A TW091134142 A TW 091134142A TW 91134142 A TW91134142 A TW 91134142A TW I269567 B TWI269567 B TW I269567B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M9/00—Parallel/series conversion or vice versa
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/14—Channel dividing arrangements, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
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Abstract
Description
1269567 ⑴ 玖、發明說明 (發明說明應敘明:發明所屬之技術領域、先前技術、内容、實施方式及圖式簡單說明) 技術領域 本發明係關於匯流排資料傳送。特別是,本發明係為減 少傳送匯流排資料的線路。 先前技藝1269567 (1) Description of the invention (Description of the invention should be clarified: the technical field, prior art, content, embodiment and schematic description of the invention) Technical Field The present invention relates to bus data transmission. In particular, the present invention is to reduce the number of lines that carry bus data. Previous skill
圖1所示者即為用於傳送資料之匯流排其一範例。圖1 係一用於無線通訊系統之接收與傳送增益控制器(GC) 30 、32,及一 GC控制器38說明圖。一通訊台,像是基地台或 使用者設備,會傳送(TX)及接收(RX)信號。為控制這些信 號增益,落屬於其他接收/傳送元件的運作範圍之間,GC 30 、32會調整RX及TX信號上的增益度。The one shown in Figure 1 is an example of a bus for transmitting data. 1 is an illustration of a receive and transmit gain controller (GC) 30, 32, and a GC controller 38 for a wireless communication system. A communication station, such as a base station or user equipment, transmits (TX) and receive (RX) signals. To control these signal gains between the operating ranges of other receive/transmit components, GC 30, 32 adjusts the gain on the RX and TX signals.
為控制GC 30、32的增益參數,會利用一 GC控制器38。 即如圖1所示,該GC控制器38會利用一功率控制匯流排, 像是16條線路匯流排34、36來送出TX 36及RX 34信號的增 益值,像是各者為八條線路。功率控制匯流排線路34、36 雖可供允快速資料傳送,然這會要求該GC 30、32及該GC 控制器38上許多接腳,或是像一專用積體電路(ASIC)之積 體電路(1C)上GC 30、32及GC控制器38間的許多連線。增加 接腳數會要求額外電路板空間與連線。增加1C連線會佔用 珍貴的1C空間。大量的接腳或連線或會依實作方式而定提 南匯流排成本。 從而,希望是可具有其他的資料傳送方式。 發明内容 1269567 __一__To control the gain parameters of the GCs 30, 32, a GC controller 38 is utilized. That is, as shown in FIG. 1, the GC controller 38 utilizes a power control bus, such as 16 line busses 34, 36, to send the gain values of the TX 36 and RX 34 signals, such as eight lines for each. . Although the power control bus lines 34, 36 are available for fast data transfer, this would require the GC 30, 32 and many pins on the GC controller 38, or an integrated circuit like an integrated integrated circuit (ASIC). (1C) Many connections between GC 30, 32 and GC controller 38. Increasing the number of pins will require additional board space and wiring. Adding a 1C connection will take up a precious 1C space. A large number of pins or connections may be used to determine the cost of the South Bus. Thus, it is desirable to have other means of data transfer. SUMMARY OF THE INVENTION 1269567 __一__
(2) 鮝初說明續I(2) 鮝 initial description continued I
一種混合平行/串列匯流排介面,此者具有一資料區塊 解多工裝置。該資料區塊解多工裝置具有一輸入,此者經 組態設定以接收一資料區塊,並將該資料區塊解多工成複 數個細塊。對於各個細塊,一平行轉串列轉換器可將該細 塊轉化成串列資料。一線路可傳送各個細塊的串列資料。 一串列轉平行轉換器可轉換各細塊的串列資料以復原該 細塊。資料區塊重建裝置可將各復原細塊合併成該資料區 塊。一基地台(或一使用者設備)具有一增益控制控制器。 該增益控制控制器會產生一具有代表一增益值之η位元的 資料區塊。一資料區塊解多工裝置具有一輸入,此者經組 態設定以接收該資料區塊,並將該資料區塊解多工成複數 個細塊。各個細塊具有複數個位元。對於各個細塊,一平 行轉樂列轉換器可將該細塊轉化成申列資料,一線路傳送 該細塊串列資料,而一串列轉平行轉換器可轉換該細塊串 列資料以復原該細塊。一資料區塊重建裝置可將該等經復 原細塊合併成該資料區塊。一增益控制器接收該資料區塊 ,並利用該資料區塊的增益值以調整其增益。 實施方式 圖2所示者係一混合平行/串列匯流排介面區塊圖,而圖 3為一混合平行/串列匯流排介面資料傳送作業流程圖。一 資料區塊會被跨於該介面而從節點1 50傳送到節點2 52 (54) 。一資料區塊解多工裝置40接收該區塊,並將其解多工成 為i個細塊,以利於i條資料傳送線路44上傳送(56)。該數值 i係根據連線數目與傳送速度之間的取捨而定。一種決定i 1269567 ω 值的方式是首莽决中 聲轉:爹择矯夏 1' 育先决疋一傳送該資料區 延遲。按照此最大延遲, 斤件承允之最大 」/尺疋出傳接 小線路數耳。利用最小數量的、〜品塊所需要的最 會被選定為至少該最小值量 以傳送資料的線路 電路板上或於— iCit ’ 44可為接腳,以及其在 儿運接上的相闕連線。— 的万式是將區塊切劃成-最顯著到一最“成細塊 圖4說明,於兩條線路 小颂著細塊。為如 解多工成一四位… 八位元區機,該區塊會被 K 四位兀最顯著細妙芬 、 另一種方式目彳是將, Α 四位兀取小顯著細塊。 前i個位元會變# I έ A 7万、1個細塊。孩區塊的 W心 的第—位元。其次的i個位元- 寬成各i個細塊的第二位元 ^ 元。為說明如圖5所示之在兩下去一直到該最後i個位 ㈡所不< S兩條連線上的一八位元區妙 第一個位元會被映對到細 ^ 瓜i的罘一位兀。第二個位元备 被映對到細塊2的第一 _ θ ^ 罘二個位元·會被映對到細塊i 的罘一仫7C,如此繼續下去,一直到將最後一個位元映對 到細塊2的最後位元。 各個、”田塊會被迗到i個平行轉串列(p/s)轉換器仏之相對 應者(58),從平行位元轉換成串列位元,並於線路上舉列 循序地傳送(60)。在各條線路的相對側會是一串列轉平行 (S/P)轉換器46。各個S/P轉換器46會將所傳串列資料轉換成 其原始細塊(62)。第i個經復原細塊會被一資料區塊重建裝 置48處理,以重建該原始資料區塊(64)。 另一万面’雙向方式,會利用丨條連線以按雙向方式傳 送資料’即如圖6。可按雙向傳送資訊資料,或是可按單 (4) 1269567 一方向傳送資訊而朝另一方向送返確認信號。在此,一資 料區塊解多工及重建裝置66會接收從節點1 5〇傳送到節點 2 52的資料區塊。該解多工及重建裝置66會將該區塊解多 工成i個細塊。i個P/S轉換器68會將各個細塊轉換成亭列資 料。一組多工器(MUX)/DEMUX 71將各個p/s轉換器68耦接到 i條線路44的相對應者。在節點2 52處,另一組的多工器 MUX/DEMUX 75將線路44連接到一組s/P轉換器72。該組s/p 轉換器72會將各細塊的所收串列資料轉換成為原始傳送 的細塊。所收細塊會被一資料區塊解多工及重建裝置% 重建成原始資料區塊,並輸出為所接收的資料區塊。 對於從節點2 52傳送到節點丨50的各區塊,該資料區塊 解多工及重建裝置76會接收一資料區塊。該區塊會被解多 工成為各細塊,並將各細塊傳送到一組p/s轉換器74。該 P/S轉換器74會將各細塊轉換成串列格式,以供跨於丨條線 路44傳送。節點2組的MUX/DEMUX 75會將該等p/s轉換器74 耦接到1條線路44,而節點1組的MUX/DEMUX 71會將線路44 耦接到i個S/P轉換器70。該等s/p轉換器7〇將所傳資料轉換 成其原始細塊。該資料區塊解多工及重建裝置66從所收細 塊重建出資料區塊,以輸出所接收的資料區塊。既然一次 只會在單一方向上傳送資料,這種實作可按半雙工方式運 作。 圖7係一雙向切換電路的實作簡圖。該節點1 p/s轉換器 68的串列輸出會被輸入到一三態式緩衝器78。該緩衝器78 具有另一輸入,這會被耦接到一表示高狀態的電壓。該緩 ΆΑ Ύ …二 / i"/广 \ h 二 發明說W績頁: 麵_議1議_讓_繼議11議 點,會送出 1269567 (6)A hybrid parallel/serial bus interface, which has a data block demultiplexing device. The data block demultiplexing device has an input configured to receive a data block and to demultiplex the data block into a plurality of fine blocks. For each thin block, a parallel to serial converter converts the block into a serial data. A line can transmit serial data of each thin block. A serial to parallel converter converts the serial data of each fine block to restore the fine block. The data block reconstruction device can merge the restored thin blocks into the data block. A base station (or a user equipment) has a gain control controller. The gain control controller generates a data block having n bits representing a gain value. A data block demultiplexing device has an input, which is configured to receive the data block and to demultiplex the data block into a plurality of fine blocks. Each thin block has a plurality of bits. For each of the thin blocks, a parallel-sound-to-column converter converts the thin block into an application data, a line transfers the fine block serial data, and a serial-to-parallel converter converts the fine block serial data to Restore the thin block. A data block reconstruction device may merge the restored fine blocks into the data block. A gain controller receives the data block and uses the gain value of the data block to adjust its gain. Embodiment FIG. 2 is a hybrid parallel/serial bus interface block diagram, and FIG. 3 is a flow chart of a mixed parallel/serial bus interface data transfer operation. A data block is transmitted from node 1 50 to node 2 52 (54) across the interface. A data block demultiplexing device 40 receives the block and demultiplexes it into i fine blocks for facilitating transmission on the i data transfer line 44 (56). This value i is based on the trade-off between the number of connections and the transmission speed. One way to determine the value of i 1269567 ω is to make a decision in the first round of the sound: choose the summer 1's priority to send the data area delay. According to this maximum delay, the maximum size of the pieces is allowed to be transmitted. Using the minimum number of ~-blocks required to select at least the minimum amount to transmit data on the circuit board or - iCit '44 can be a pin, and its relatives on the child. Connected. - The 10,000 type is to cut the block into - most significant to the most "fine block" Figure 4 shows that the two lines are small and small. For the solution, the multiplex is a four-digit... octet area machine The block will be the most prominently fine by K, and the other way will be, and the four will take small and significant blocks. The first i will change # I έ A 70,000 The block is the first bit of the W heart of the child block. The next i bit - the second bit of each i block is wide. The last i-bit (2) is not the first bit of the one-octet area of the two lines. The first bit of the first-order bit will be mapped to the one of the fine-grained me. The second bit is prepared. The first _ θ ^ 罘 two bits mapped to the thin block 2 will be mapped to the 仫 仫 7C of the thin block i, and so on, until the last bit is mapped to the thin block 2 The last bit. Each field, the field block will be switched to the corresponding parallel switch (p/s) converter (58), converted from parallel bit to tandem bit, and on the line. The sequence is transmitted (60). On the opposite side of each line will be a series of parallel to parallel (S/P) converters 46. Each S/P converter 46 converts the transmitted serial data into its original fine block (62). The i-th recovered thin block is processed by a data block reconstruction device 48 to reconstruct the original data block (64). Another 10,000-sided “two-way way will use the splicing line to transmit information in a two-way manner” as shown in Figure 6. The information can be transmitted in both directions, or the information can be sent in one direction (4) 1269567 and the confirmation signal can be sent in the other direction. Here, a data block demultiplexing and reconstruction device 66 receives the data block transmitted from node 15 5 to node 2 52. The demultiplexing and reconstruction device 66 will demultiplex the block into i fine blocks. The i P/S converters 68 convert each of the fine blocks into a kiosk. A set of multiplexers (MUX) / DEMUX 71 couples the respective p/s converters 68 to the corresponding ones of the i lines 44. At node 2 52, another set of multiplexer MUX/DEMUX 75 connects line 44 to a set of s/P converters 72. The set of s/p converters 72 converts the received serial data of each fine block into a fine block of the original transmission. The received fine block will be reconstructed into the original data block by a data block demultiplexing and reconstruction device %, and output as the received data block. For each block transmitted from node 2 52 to node 50, the data block demultiplexing and reconstruction device 76 receives a data block. The block is demultiplexed into individual blocks and the blocks are transferred to a set of p/s converters 74. The P/S converter 74 converts each of the thin blocks into a tandem format for transmission across the spool line 44. The MUX/DEMUX 75 of the Node 2 group couples the p/s converter 74 to one line 44, while the MUX/DEMUX 71 of the Node 1 group couples the line 44 to the i S/P converters 70. . The s/p converters 7 convert the transmitted data into its original thin blocks. The data block demultiplexing and reconstruction device 66 reconstructs the data block from the received block to output the received data block. Since the data will only be transmitted in a single direction at a time, this implementation can be operated in a half-duplex manner. Figure 7 is a schematic diagram of the implementation of a bidirectional switching circuit. The serial output of the node 1 p/s converter 68 is input to a tristate buffer 78. The buffer 78 has another input that is coupled to a voltage indicative of a high state. The ΆΑ Ύ 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二 二
元件的計時。為表述該資料區塊傳送作業的起 一開始位元。即如圖8所示,各線路會在其正常零水準。 然後會送出一表示開始區塊傳送作業的開始位元。在本例 中,所有線路會送出一開始位元,然實僅需在一條線路上 送出開始位元。如在任一條線路上送出開始位元,像是一 1值,則接收節點會明暸開始該區塊資料傳送作業。在此 ,會透過其相對應線路送出各個幸列細塊。在傳送各細塊 後,線路會回返至彼等正常狀態,像是皆為低者。Timing of components. To indicate the starting bit of the data block transfer operation. That is, as shown in Figure 8, each line will be at its normal zero level. A start bit indicating the start of the block transfer job is then sent. In this example, all lines will send a start bit, but only the start bit will be sent on one line. If a start bit is sent on any line, such as a value of 1, the receiving node will know to start the block data transfer operation. Here, each of the fortunate columns is sent through its corresponding line. After transmitting the fine blocks, the lines will return to their normal state, as if they were all low.
在其他實作裡,也會利用開始位元做為待予執行之函數 的表不态。這種貫作方式可如圖9說明。而如圖10所示者 ,如任一連線的第一位元為1值,該接收節點會瞭解待予 傳送區塊資料。即如圖11之GC控制器實作的表格所列,利 用三種開始位元組合:01、10及11。00表示尚未送出開始 位元。各個組合代表一種函數。在本例中_,0 1表示應執行 一相對減少函數,像是將該資料區塊值減少1值。10表示 應執行一相對增加函數,像是將該資料區塊值增加1值。 11表示應執行一絕對值函數,此時該區塊會維持相同數值 。為增加可用函數的數目,可利用額外位元,例如,可將 每條線路2個開始位元映對到達七(7)項函數,或是將i條線 路的η個開始位元映對到達in+1-l種函數。處理裝置86會依 開始位元所述,對所收的資料區塊執行函數。 在如圖12所示的另款實作裡,開始位元表示一目的地裝 置。即如圖1 3所示,此為兩個目的地裝置/兩條線路實作 ,開始位元的組合會關聯到對所傳資料區塊之目的地裝置 -11 - 1269567 . (7) I __娜 88-92。01表示裝置1 ; 10表示裝置2 ;而11表示裝置3。在收 到該資料區塊重建裝置48的開始位元後,所重建的區塊會 被送到相對應裝置88-92。為增加潛在目的地裝置的數目 ,可利用額外的開始位元。對於在各i條線路上的η個開始 位元,可選定達in+1-l個裝置。In other implementations, the starting bit is also used as a function of the function to be executed. This mode of operation can be illustrated in FIG. As shown in FIG. 10, if the first bit of any connection is a value, the receiving node knows the data to be transmitted. That is, as shown in the table of the GC controller implementation of Fig. 11, three combinations of start bits are used: 01, 10, and 11.00 indicate that the start bit has not been sent. Each combination represents a function. In this example _, 0 1 indicates that a relative reduction function should be performed, such as reducing the data block value by one value. 10 indicates that a relative increase function should be performed, such as increasing the value of the data block by one. 11 indicates that an absolute value function should be executed, and the block will maintain the same value. In order to increase the number of available functions, extra bits can be used. For example, two start bits of each line can be mapped to the seven (7) term function, or the n start bits of i lines can be mapped to arrive. In+1-l kind of function. Processing device 86 executes a function on the received data block as described in the start bit. In the alternative implementation shown in Figure 12, the start bit represents a destination device. That is, as shown in Fig. 13, this is the implementation of two destination devices/two lines, and the combination of the start bits is associated with the destination device -11 - 1269567 for the data block to be transmitted. (7) I _ _Na 88-92. 01 indicates device 1; 10 indicates device 2; and 11 indicates device 3. After receiving the start bit of the data block reconstruction device 48, the reconstructed block is sent to the corresponding device 88-92. To increase the number of potential destination devices, additional start bits can be utilized. For n start bits on each i line, up to 1 - 1 devices can be selected.
即如圖14所示,可利用開始位元來表示函數及目的地裝 置兩者。圖14顯示一具有像是RX及TX GC兩個裝置的三條 連線系統。在各條線路上利用開始位元,圖中繪出兩個裝 置的三種函數。在本例中,線路1的開始位元代表該標的 裝置,「0」為裝置1,而「1」為裝置2。連線2及3的位元 代表所執行函數。「11」代表絕對值函數;「10」代表相對 增加函數;而「01」代表相對減少函數。所有三個開始位 元為零,意即「000」,會是正常非資料傳送狀態,而在此 並未使用「001」。可利用額外的位元以增j口更多的函數或 裝置。對於在各i條線路上的η個開始位元,可選定達in+1-lThat is, as shown in Fig. 14, both the function and the destination device can be represented by the start bit. Figure 14 shows a three-wire system with two devices like RX and TX GC. The start bit is used on each line, and the three functions of the two devices are drawn in the figure. In this example, the start bit of line 1 represents the target device, with "0" being device 1 and "1" being device 2. The bits of lines 2 and 3 represent the function being executed. "11" represents an absolute value function; "10" represents a relative increase function; and "01" represents a relative decrease function. All three start bits are zero, meaning "000", which is normal non-data transfer status, and "001" is not used here. Additional bits can be utilized to add more functions or devices. For n start bits on each i line, you can select in in+1-l
個函數/裝置組合。 圖15係一實作表示函數及目的地裝置兩者之開始位元 的系統區塊圖。經復原的細塊會由該資料區塊重建裝置48 所接收。根據所收到的開始位元,該處理裝置86會執行所 述函數,而將所處理區塊送到所述之目的地裝置88-92。 即如圖16流程圖所示,會將表示該函數/目的地的開始 位元增入各個細塊内(94)。在此,會透過這i條線路送出這 些細塊(96)。利用開始位元,會在資料區塊上執行適當函 數,資料區塊會被送到適當目的地或兩者(98)。 -12- 1269567 發明說明續頁 ⑻ 為增加同步系統内的產通量,會利用時脈的正(雙1及負 (單)邊緣兩者來傳送區塊資料。其一實作可如圖W所示” 資料區塊解多工裝置100收到資料區塊,並將其解多工 兩個(雙及單)組i個細塊。在此,會將丨個細塊的各組资料 送到個別各組的i個P/S裝置102、1〇4。即如圖17所示,L 的單P/S裝置102會具有i個P/s裝置,這會擁有其經反置= 118所反置的時脈信號。因此,經反置的時脈信號會是麫 相對於該系統時脈而延遲的半個時脈週期。一組i個 106會在該組雙P/s裝置1〇4與該組單p/s裝置1〇2之 Jί安兩 倍於該時脈速率而進行選定。在各連線上傳送的產獲資料 會是兩倍的時脈速率。在各連線的另一端是一相對應的 DEMUX 108。這些DEMUX 108會循序地按兩倍時脈速率, 將各條線路44耦接到一雙112與單11〇緩衝器。各個緩衝器 112、110接收一相對應的雙與單位元,並握持該數值一個 完整時脈週期。一雙U6與單U4組的S/p裝置會復原該等雙 與單細塊。一資料區塊重建裝置122會從各個所傳細塊重 建該資料區塊。 圖18說明利用該正及負時脈邊緣,在一系統線路上進行 的貝料傳送作業。圖示者係待予於線路1上傳送的雙資料 與單資料。斜楔部分表示合併信號内的負時脈邊緣,而無 斜楔邵分則表示正者。即如圖示,資料傳送速率會增加/ 倍。 圖19係一用於一 GC控制器38及一 GC 124之間的混合不打 /串列介面較佳實作。一資料區塊,像是16位元的GC控制 -13- (9) 1269567 貝料(8位TG RX和8位元TX),會被從該GC控制器 貝料區塊解多工裝置4〇。該資料區塊會被解多工成為兩個 細塊,像是兩個8位元細塊。會對各個細塊增附一開始位 元像疋令為每個細塊9位元。在此,會利用兩個p/s轉換 器42於兩條線路上傳送這兩個細塊。當s/p轉換器牝偵測到 開始位7C時就會將所接收細塊轉換為平行格式。該資料區 塊重建裝置會重建原始16位元以控制GC 124的增益。如開 ^位兀表述出一函數,即如圖11所示,該AGC 124會在調 整增益之前,先對所收區塊執行該項函數。 圖20係於一混合平行/串列匯流排轉換器另一較佳實作 ,此係位於GC控制器38及一 Rx GC 3〇與TX GC 32間,並利 用二(3)條線路。該GC控制器38會按適當rx及τχ增益值與 開始位元’即如圖14所示,送出一資料區塊給該gc 30、 32 °如確採用按圖14的開始位元,裝置1為rx GC 30而裝置 2為TX GC 32。該資料區塊解多工裝置4〇會將該資料區塊解 多工成為三個細塊,以供透過這三條線路而傳送。利用三 個P/S轉換器42及三個S/P轉換46,各細塊會被串列地在各 線路上傳送,並轉換成原始細塊。該資料區塊重建裝置48 會重建原始資料區塊,並執行如開始位元所述之函數,像 是相對增加、相對減少及絕對值。所獲資料會被送到如開 始位元所述之RX或TX GC 30、32。 圖式簡單說明 圖1係RX與TX GC和GC控制器圖式說明。 圖2係一混合平行/串列匯流排介面區塊圖。 -14 - 1269567 _-__ (10) 奢明說呀續買 圖3係利用混合平行/串列匯流排介面之資料區塊傳送 作業流程圖。 圖4說明將一區塊轉成最顯著及最小顯著細塊之解多工 作業。 圖5說明利用資料交錯處理對一區塊進行解多工作業。 圖6係一雙向混合平行/串列匯流排介面之區塊圖。 圖7係一雙向線路實作圖式。Function/device combination. Figure 15 is a system block diagram showing the start bits of both the function and the destination device. The recovered thin blocks are received by the data block reconstruction device 48. Based on the received start bit, the processing device 86 executes the function and sends the processed block to the destination device 88-92. That is, as shown in the flowchart of Fig. 16, the start bit indicating the function/destination is added to each of the thin blocks (94). Here, these fine blocks (96) are sent through the i lines. With the start bit, the appropriate function is executed on the data block and the data block is sent to the appropriate destination or both (98). -12- 1269567 Describing the Invention (8) In order to increase the throughput in the synchronous system, the positive (double 1 and negative (single) edges of the clock are used to transmit the block data. One of the implementations can be as shown in Figure W The data block demultiplexing device 100 receives the data block and demultiplexes two (double and single) groups of i fine blocks. Here, the data of each group of the thin blocks is sent. To each of the individual P/S devices 102, 1〇4, that is, as shown in Fig. 17, the single P/S device 102 of L will have i P/s devices, which will have its reversed = 118 The inverted clock signal. Therefore, the inverted clock signal will be half a clock period delayed by 麫 relative to the system clock. A set of i 106 will be in the set of dual P/s devices. 4 is selected with the set of single p/s devices 1〇2, which is twice the clock rate. The data acquired on each line will be twice the clock rate. The other end is a corresponding DEMUX 108. These DEMUXs 108 sequentially couple each line 44 to a pair 112 and a single 11 buffer at twice the clock rate. Each buffer 112, 110 receives a relative The double and unit cells, and hold the value for a complete clock cycle. A pair of U6 and single U4 S/p devices will restore the double and single blocks. A data block reconstruction device 122 will The fine block reconstructs the data block. Figure 18 illustrates the bead transfer operation performed on a system line using the positive and negative clock edges. The figure is the double data and single data to be transmitted on line 1. The wedge portion indicates the negative clock edge in the combined signal, and the non-wedge skew indicates the positive. That is, as shown, the data transfer rate is increased/time. Figure 19 is a GC controller 38 and A hybrid uninterrupted/serial interface between GCs is preferred. A data block, such as a 16-bit GC control-13-(9) 1269567 (8-bit TG RX and 8-bit TX) ), the multiplexer will be solved from the GC controller block. The data block will be multiplexed into two thin blocks, like two 8-bit thin blocks. Adding a starting bit like a command to 9 bits per fine block. Here, two p/s converters 42 are used to transmit the two thin blocks on two lines. When the s/p converter detects the start bit 7C, it will convert the received fine block into a parallel format. The data block reconstruction device reconstructs the original 16 bits to control the gain of the GC 124. A function is expressed, that is, as shown in Fig. 11, the AGC 124 performs the function on the received block before adjusting the gain. Fig. 20 is another preferred example of a hybrid parallel/serial bus converter. In practice, this is located between the GC controller 38 and an Rx GC 3〇 and the TX GC 32, and utilizes two (3) lines. The GC controller 38 will press the appropriate rx and τχ gain values with the start bit'. As shown in FIG. 14, a data block is sent to the gc 30, 32 ° if the start bit according to FIG. 14 is used, device 1 is rx GC 30 and device 2 is TX GC 32. The data block demultiplexing device 4 will unmultiplex the data block into three fine blocks for transmission through the three lines. With three P/S converters 42 and three S/P conversions 46, the fine blocks are transmitted in series on each line and converted into original thin blocks. The data block reconstruction unit 48 reconstructs the original data block and performs functions such as relative increase, relative decrease, and absolute value as described in the start bit. The information obtained will be sent to the RX or TX GC 30, 32 as described in the starting bit. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a graphical representation of the RX and TX GC and GC controllers. Figure 2 is a block diagram of a hybrid parallel/serial bus interface. -14 - 1269567 _-__ (10) Explain that the purchase of Figure 3 is a flow chart of the data block transfer using the hybrid parallel/serial bus interface. Figure 4 illustrates the multiplexed operation of converting a block into the most significant and least significant fine blocks. Figure 5 illustrates the use of data interleaving to solve a block of work. Figure 6 is a block diagram of a bidirectional hybrid parallel/serial bus interface. Figure 7 is a two-way line implementation diagram.
圖8係開始位元之計時圖。 圖9係一函數可控制性之混合平行/申列匯流排介面的 區塊圖。 圖10係一函數可控制性之混合平行/串列匯流排介面的 開始位元計時圖。 圖11係表示各項函數之開始位元實作列表。 圖12係目的地控制混合平行/串列匯流排介面之區塊圖。 圖13係表示各項目的地之開始位元實作列表。Figure 8 is a timing diagram of the starting bit. Figure 9 is a block diagram of a hybrid parallel/destination bus interface of function controllability. Figure 10 is a start bit timing diagram of a hybrid parallel/serial bus interface of function controllability. Figure 11 is a diagram showing the starting bit implementation of each function. Figure 12 is a block diagram of the destination control hybrid parallel/serial bus interface. Figure 13 is a list of the starting bits of each destination.
圖14係表示各項目的地/函數之開始位元實作列表。 圖15係目的地/函數控制混合平行/串列匯流排介面之區 塊圖。 圖16係表示各項目的地/函數之開始位元流程圖。 圖17係正及負時脈邊緣之混合平行/串列匯流排介面區 塊圖。 圖1 8係正及負時脈邊緣之混合平行/申列匯流排介面計 時圖。 圖19係一 2線式GC/GC控制器匯流排區塊圖。 -15- 1269567 圖 30 32 34 36 38 40 42 44 46 48 50 52 66 68 70 72 74 76 78 80 82 84 (π) I發明靛明績買: 20係一 3線式GC/GC控制器匯流排區塊圖。 圖式代表符號說明 接收增益控制器 傳送增益控制器 線路匯流排 線路匯流排 GC控制器 資料區塊解多工裝置 平行轉串列(P/S)轉換器 資料傳送線路 串列轉平行(S/P)轉換器 資料區塊重建裝置 節點1 節點2 資料區塊解多工及重建裝置 平行轉串列(P/S)轉換器 串列轉平行(S/P)轉換器 串列轉平行(S/P)轉換器 平行轉申列(p/s)轉換器 資料區塊解多工及重建裝置 緩衝器 緩衝器 緩衝器 緩衝器 -16· 1269567(12) 85 線路 86 電阻 88 目的地裝置 90 目的地裝置 92 目的地裝置 100 資料區塊解多工裝置 102 單P/S裝置 104 雙P/S裝置 106 多工器 108 解多工器 110 緩衝器 112 緩衝器 114 單P/S裝置 116 雙P/S裝置 122 資料區塊重建裝置 124 增益控制器 發明說明續頁 凝淺緣纖_緣攀转綴裝綠攀黎賴翁纖毅懸黎纖Figure 14 is a list of implementations of start bits for each destination/function. Figure 15 is a block diagram of the destination/function control hybrid parallel/serial bus interface. Figure 16 is a flow chart showing the start bit of each destination/function. Figure 17 is a block diagram of a hybrid parallel/serial bus interface interface for positive and negative clock edges. Figure 1 shows the timing of the hybrid parallel/description bus interface interface of the positive and negative clock edges. Figure 19 is a block diagram of a 2-wire GC/GC controller bus. -15- 1269567 Fig. 30 32 34 36 38 40 42 44 46 48 50 52 66 68 70 72 74 76 78 80 82 84 (π) I Invention 靛 绩 绩 Buy: 20 Series One 3-Wire GC/GC Controller Busbar Area Block diagram. Schematic Representation Symbol Description Receive Gain Controller Transmit Gain Controller Line Bus Bars Busbar GC Controller Data Block Solution Multiplexer Parallel Serial Train (P/S) Converter Data Transmission Line Serial Parallel to Parallel (S/ P) Converter data block reconstruction device node 1 node 2 data block solution multiplexing and reconstruction device parallel-to-serial column (P/S) converter serial-to-parallel (S/P) converter serial-to-parallel (S /P) Converter Parallel Transfer Application (p/s) Converter Data Block Demultiplexing and Reconstruction Device Buffer Buffer Buffer Buffer-16· 1269567(12) 85 Line 86 Resistor 88 Destination Device 90 Purpose Ground device 92 destination device 100 data block demultiplexing device 102 single P/S device 104 dual P/S device 106 multiplexer 108 demultiplexer 110 buffer 112 buffer 114 single P/S device 116 double P /S device 122 data block reconstruction device 124 gain controller invention description continuation page condensed shallow edge fiber _ edge climbing splicing green climbing Li Lai Weng Yi Yi hanging Li fiber
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TWI408929B (en) * | 2007-03-23 | 2013-09-11 | Qualcomm Inc | Methods and apparatus for initial acquisition gain control in a communication system |
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WO2003046738A1 (en) | 2003-06-05 |
DE60221271T2 (en) | 2008-04-10 |
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ES2287360T3 (en) | 2007-12-16 |
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US7475273B2 (en) | 2009-01-06 |
EP1446723A1 (en) | 2004-08-18 |
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TW200303674A (en) | 2003-09-01 |
CA2467844A1 (en) | 2003-06-05 |
US7240233B2 (en) | 2007-07-03 |
TW200641629A (en) | 2006-12-01 |
US20050105370A1 (en) | 2005-05-19 |
JP2007164812A (en) | 2007-06-28 |
JP3951240B2 (en) | 2007-08-01 |
JP2005510801A (en) | 2005-04-21 |
EP1446723B1 (en) | 2007-07-18 |
CN1589438A (en) | 2005-03-02 |
HK1069906A1 (en) | 2005-06-03 |
CA2467844C (en) | 2008-04-01 |
ATE367682T1 (en) | 2007-08-15 |
US20070113117A1 (en) | 2007-05-17 |
MXPA04004788A (en) | 2004-08-11 |
TW200422836A (en) | 2004-11-01 |
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