KR970056528A - Analog Bus / I ^ 2C Bus Protocol Converters - Google Patents
Analog Bus / I ^ 2C Bus Protocol Converters Download PDFInfo
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- KR970056528A KR970056528A KR1019950049404A KR19950049404A KR970056528A KR 970056528 A KR970056528 A KR 970056528A KR 1019950049404 A KR1019950049404 A KR 1019950049404A KR 19950049404 A KR19950049404 A KR 19950049404A KR 970056528 A KR970056528 A KR 970056528A
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- analog
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Abstract
본 발명은 아날로그 버스(analog bus)를 통해 수신한 데이터를 I2C(I2C: Integreated Integreated Circuit)버스 방식 데이터로 변환하기 위한 아날로그 버스/I2C버스 프로토콜 변환기에 관한 것이다The present invention is a data received through the analog bus (analog bus) I 2 C: related to analog bus / I 2 C bus protocol converter for converting a data bus system (I 2 C Integreated Integreated Circuit)
본 발명의 프로토콜 변환기는 아날로그 버스의 어드레스 라인을 통해 수신된 아날로그 어드레스를 디지탈 값으로 변환하기 위한 제1아날로그/디지탈 변환기와, 상기 아날로그 버스의 데이터 라인을 통해 수신된 아날로그 데이터를 디지탈 값으로 변환하기 위한 제2아날로그/디지탈 변환기와, 상기 제1아날로그/디지털 변환기로부터의 병렬 디지탈 어드레스를 입력 인에이블 신호에 따라 수신하기 위한 제1 3상태 입력 버퍼와, 상기 제2아날로그/디지탈 변환기로부터의 병렬 디지탈 데이터를 입력 인에이블 신호에 따라 수신하기 위한 제2 3상태 입력 버퍼와, 상기 제1 및 제2 3상태 입력 버퍼에 각각 연결되어 래치 인에이블 신호의 인가에 따라 각각 어드레스 및 데이터를 래치하기 위한 제1 및 제2래치와, 상기 제1래치로부터 입력된 8비트 어드레스를 제1클럭에 동기하여 직렬 데이터 라인으로 출력하는 제1시프트 레지스터와, 상기 제2래치로부터 입력된 8비트 데이터를 제2클럭에 동기하여 직렬 데이터 라인으로 출력하는 제2시프트 레지스터와, 상기 제1 및 제2시프트 레지스터에 대한 상기 제1 및 제2클럭의 제공하며, I2C 버스 프로토콜을 만족하는데 필요한 스타트 및 스톱신호, 리드 및 라이트 신호, 수신확인 및 수신확인 불능 신호를 포함한 각종 제어신호를 변환된 어드레스 및 데이터 출력 전후에 삽입하여 직렬 데이터 라인으로 출력하며, 이와 동시에 동기 클럭을 클럭라인으로 출력하기 위한 로직 발생 수단과, 변환기 내에 필요한 각종 클럭을 발생하는 클럭 발생기와, 상기 어드레스와 데이터에 대한 규정 비트 수신을 카운팅하기 위한 카운터로 구성되는 것을 특징으로 한다.The protocol converter of the present invention includes a first analog / digital converter for converting an analog address received through an address line of an analog bus into a digital value, and converting analog data received through a data line of the analog bus into a digital value. A second analog / digital converter for receiving, a first tri-state input buffer for receiving a parallel digital address from the first analog / digital converter according to an input enable signal, and a parallel digital from the second analog / digital converter. A second tri-state input buffer for receiving data in accordance with an input enable signal, and a third tri-state input buffer connected to the first and second tri-state input buffers, respectively, for latching address and data according to application of a latch enable signal, respectively. The first and second latches, and the 8-bit address input from the first latch, A first shift register for outputting a serial data line in synchronization with a lock; a second shift register for outputting 8-bit data input from the second latch to a serial data line in synchronization with a second clock; Provides the first and second clocks for two shift registers and converts various control signals including start and stop signals, read and write signals, acknowledgment and non-acknowledge signals required to satisfy the I 2 C bus protocol. Logic generation means for inserting before and after address and data output to a serial data line, and at the same time for outputting a synchronous clock to a clock line, a clock generator for generating various clocks required in the converter, and specifying the address and data And a counter for counting bit receptions.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제4도는 본 발명에 따른 아날로그 버스/I2C 버스 프로토콜 변환기의 심볼 블록도.4 is a symbol block diagram of an analog bus / I 2 C bus protocol converter according to the present invention.
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950049404A KR970056528A (en) | 1995-12-13 | 1995-12-13 | Analog Bus / I ^ 2C Bus Protocol Converters |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950049404A KR970056528A (en) | 1995-12-13 | 1995-12-13 | Analog Bus / I ^ 2C Bus Protocol Converters |
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KR970056528A true KR970056528A (en) | 1997-07-31 |
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KR1019950049404A KR970056528A (en) | 1995-12-13 | 1995-12-13 | Analog Bus / I ^ 2C Bus Protocol Converters |
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KR (1) | KR970056528A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6848018B2 (en) | 2001-11-21 | 2005-01-25 | Interdigital Technology Corporation | Method employed by a base station for transferring data |
US7107479B2 (en) | 2001-11-21 | 2006-09-12 | Interdigital Technology Corporation | Apparatus and method for bidirectional transfer of data by a base station |
-
1995
- 1995-12-13 KR KR1019950049404A patent/KR970056528A/en not_active Application Discontinuation
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6848018B2 (en) | 2001-11-21 | 2005-01-25 | Interdigital Technology Corporation | Method employed by a base station for transferring data |
US7069464B2 (en) | 2001-11-21 | 2006-06-27 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
US7107479B2 (en) | 2001-11-21 | 2006-09-12 | Interdigital Technology Corporation | Apparatus and method for bidirectional transfer of data by a base station |
US7240233B2 (en) | 2001-11-21 | 2007-07-03 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
KR100808900B1 (en) * | 2001-11-21 | 2008-03-06 | 인터디지탈 테크날러지 코포레이션 | Base station having a hybrid parallel/serial bus interface |
KR100812858B1 (en) * | 2001-11-21 | 2008-03-11 | 인터디지탈 테크날러지 코포레이션 | User equipment having a hybrid parallel/serial bus interface |
KR100812859B1 (en) * | 2001-11-21 | 2008-03-11 | 인터디지탈 테크날러지 코포레이션 | User equipment having a hybrid parallel/serial bus interface |
US7475273B2 (en) | 2001-11-21 | 2009-01-06 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
US7752482B2 (en) | 2001-11-21 | 2010-07-06 | Interdigital Technology Corporation | Hybrid parallel/serial bus interface |
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