KR970056528A - Analog Bus / I ^ 2C Bus Protocol Converters - Google Patents

Abstract

The present invention is a data received through the analog bus (analog bus) I ² C: related to analog bus / I ² C bus protocol converter for converting a data bus system (I ² C Integreated Integreated Circuit)

The protocol converter of the present invention includes a first analog / digital converter for converting an analog address received through an address line of an analog bus into a digital value, and converting analog data received through a data line of the analog bus into a digital value. A second analog / digital converter for receiving, a first tri-state input buffer for receiving a parallel digital address from the first analog / digital converter according to an input enable signal, and a parallel digital from the second analog / digital converter. A second tri-state input buffer for receiving data in accordance with an input enable signal, and a third tri-state input buffer connected to the first and second tri-state input buffers, respectively, for latching address and data according to application of a latch enable signal, respectively. The first and second latches, and the 8-bit address input from the first latch, A first shift register for outputting a serial data line in synchronization with a lock; a second shift register for outputting 8-bit data input from the second latch to a serial data line in synchronization with a second clock; Provides the first and second clocks for two shift registers and converts various control signals including start and stop signals, read and write signals, acknowledgment and non-acknowledge signals required to satisfy the I ² C bus protocol. Logic generation means for inserting before and after address and data output to a serial data line, and at the same time for outputting a synchronous clock to a clock line, a clock generator for generating various clocks required in the converter, and specifying the address and data And a counter for counting bit receptions.

Description

Analog Bus / I2C Bus Protocol Converters

Since this is an open matter, no full text was included.

4 is a symbol block diagram of an analog bus / I ² C bus protocol converter according to the present invention.

Claims (1)

A first analog / digital converter for converting an analogue address received through an address line of an analog bus into a digital value, and a second analog / digital converter for converting analog data received through a data line of the analog bus into a digital value; A digital converter, a first tri-state input buffer for receiving a history digital address from the first analog / digital converter according to an input enable signal, and parallel enable data from the second analog / digital converter A second tri-state input buffer for receiving according to a signal, and first and second latches connected to the first and second tri-state input buffers respectively to latch an address and data according to the application of a latch enable signal. And an 8-bit address input from the first latch in synchronization with the first clock. A first shift register for outputting a second shift register; a second shift register for outputting 8-bit data input from the second latch to a serial data line in synchronization with a second clock; and the first for the first and second shift registers. Provides first and second clocks, inserts control signals including start and stop signals, read and write signals, acknowledgment and nonacknowledgement signals required to satisfy the I ² C bus protocol, before and after the converted address and data output A logic generating means for outputting a synchronous clock to a clock line, a clock generator for generating various clocks required in the converter, and a counter for counting reception of prescribed bits for the address and data. Analog / I ² C bus protocol converter, characterized in that consisting of. ※ Note: The disclosure is based on the initial application.