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CN1983597A - 场效应晶体管及其制造方法 - Google Patents

场效应晶体管及其制造方法 Download PDF

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CN1983597A
CN1983597A CNA2006101728308A CN200610172830A CN1983597A CN 1983597 A CN1983597 A CN 1983597A CN A2006101728308 A CNA2006101728308 A CN A2006101728308A CN 200610172830 A CN200610172830 A CN 200610172830A CN 1983597 A CN1983597 A CN 1983597A
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heavy doping
electric field
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CN100461415C (zh
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布赖恩·塞奇·莫
迪克·肖
史蒂文·萨普
伊萨克·本库亚
迪安·爱德华·普罗布斯特
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Fairchild Semiconductor Corp
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Abstract

提供了一种沟槽型场效应晶体管，它包括(a)半导体衬底；(b)在半导体衬底中延伸至预定深度的沟槽；(c)位于沟槽两侧的一对掺杂源结；(d)位于沟槽两侧的每个源结附近的掺杂重掺杂体，此重掺杂体的最深部分在所述半导体衬底中延伸的深度比沟槽的预定深度浅；以及(e)位于重掺杂体下面并包围重掺杂体的掺杂阱。

Description

场效应晶体管及其制造方法
本申请是申请日：1998.11.13，申请号为98122326.5，名称为“场效应晶体管及其制造方法”的申请的分案申请。
技术领域
本发明涉及场效应晶体管，尤其是有沟槽(trench)的DMOS晶体管及其制造方法。
背景技术
在半导体工业中，例如MOSFET(金属氧化物半导体场效应晶体管)等功率场效应晶体管是众所周知的。一种类型的MOSFET是DMOS(双扩散金属氧化物半导体)晶体管。DMOS晶体管通常包括生长有外延层的衬底、掺杂的源结、重掺杂体(dopedheavy body)、具有与重掺杂体相同掺杂(p或n)的掺杂阱以及栅极。在有沟槽的DMOS晶体管中，栅极是纵向沟槽。重掺杂体通常比沟槽底部扩散得更深，以把沟槽底角的电场减到最小，从而防止雪崩击穿破坏该器件。沟槽填充有导电的多晶硅，一般对多晶硅进行过度蚀刻以保证完全除去沟槽周围表面上的多晶硅。此过度蚀刻一般在多晶硅顶部和半导体衬底表面(即，外延层的表面)之间留下一凹槽。必须小心地控制此凹槽的深度，从而使它比源结的深度浅。如果此凹槽比源结深，则源极将错过栅极，从而导致高的开态电阻和高的阈值，从而可能变成不起作用的晶体管。
源和漏结可掺有p型或n型杂质；在任一种情况下，重掺杂体都掺有相反的杂质，例如对于n型源极和漏极，重掺杂体为p型。把源极和漏极掺有p型载流子的DMOS晶体管叫做“p沟道”。在p沟道DMOS晶体管中，把负电压加到晶体管的栅极使电流从源区通过重掺杂体的沟道区、外延层的积累区和衬底流到漏区。相反，把源极和漏极掺有n型载流子的DMOS晶体管叫做“n沟道”。在n沟道DMOS晶体管中，把正电压加到晶体管的栅极使电流从漏极向源极流动。
最好使DMOS晶体管在导通时具有低的源-漏电阻(Rdson)和低的寄生电容。
还要防止晶体管结构的“穿通”。在加上高的漏-源电压而使重掺杂体区域内的耗尽层延伸至源区时发生穿通，从而在晶体管应被断开时形成通过重掺杂体区域的不想要的导电通路。最后，晶体管应具有良好的“耐久性”，即需要高的启动电流来使DMOS晶体管中固有的寄生晶体管导通。
一般，把大量MOSFET单元并联起来形成单个晶体管。这些单元可排列成一“封闭式单元”结构，其中以栅格方式来布置沟槽，且这些单元被沟槽壁的各边所包围。或者，这些单元可排列成一“开放式单元”结构，其中以“条状”方式来布置沟槽，且这些单元只被沟槽壁两边所包围。使用电场终止技术来把结(掺杂区)终止在其上形成晶体管的硅片的周边(边缘)处。这将使击穿电压高于只由硅片中央部分中有源晶体管单元的特征来控制的情况。
发明内容
本发明提供了具有开放式单元布局的场效应晶体管，此布局提供了良好的均匀性和高的单元密度并容易定标。较佳的沟槽型DMOS晶体管具有低的Rdson、低的寄生电容、优良的可靠性、抗雪崩击穿劣化和耐久性。较佳器件还包括增强抗雪崩击穿的电场终止(field termination)。本发明的特征还在于制造沟槽DMOS晶体管的方法。
在一个方面，本发明的特征是一种场效应晶体管，它包括具有第一导电类型的杂质的半导体衬底；基本上相互平行排列的多个栅极形成沟槽，每个沟槽在所述衬底中延伸至第一深度，相邻沟槽之间的空间限定一接触区；位于每个沟槽两侧的一对掺杂的源结，所述源结具有第一导电类型的杂质；具有第二导电类型的杂质的掺杂阱，所述第二导电类型的电荷与第一导电类型的相反，所述掺杂阱形成于每对栅极形成沟槽之间的半导体衬底中；在所述掺杂阱内形成的重掺杂体，所述重掺杂体具有小于所述沟槽的第一深度的第二深度；以及沿接触区的长度限定于半导体衬底表面的重掺杂体接触区域，其中，所述重掺杂体与所述阱形成突变结，所述重掺杂体的深度相对于所述阱的深度如此调节，从而在有电压加到晶体管时，晶体管的峰值电场与所述沟槽隔开。
较佳实施例包括一个或多个以下的特征。掺杂阱具有基本上平坦的底部。相对于阱和沟槽的深度来选择重掺杂体区域的深度，从而在把电压加到晶体管时使峰值电场与沟槽隔开。掺杂阱的深度比沟槽的预定深度浅。沟槽具有弧形的顶角和底角。在重掺杂体和阱之间的界面处有突变结，从而在把电压加到晶体管时在界面区域中产生峰值电场。
在另一个方面，本发明的特征是一晶体管单元阵列。该阵列包括半导体衬底；基本上相互平行排列且沿第一方向延伸的多个栅极形成沟槽，相邻沟槽之间的空间限定一接触区，每个沟槽在所述衬底中延伸预定的深度，此预定深度对所有的所述栅极形成沟槽基本上是相同的；位于沟槽两侧并沿沟槽长度延伸的一对掺杂源结；在每对栅极形成沟槽之间位于每个源结附近的掺杂重掺杂体，每个所述重掺杂体的最深部分在所述半导体衬底中延伸至一可调深度，该可调深度大于所述掺杂源结的深度且小于所述沟槽的所述预定深度；重掺杂体下面包围每个重掺杂体的掺杂阱；以及其中，所述掺杂重掺杂体的所述可调深度使得在有电压加到晶体管单元阵列时，将使峰值电场与邻近的沟槽隔开。
较佳实施例包括一个或多个以下特征。掺杂阱具有基本上平坦的底部。相对于阱和栅极形成沟槽的深度来选择重掺杂体区域的深度，从而在把电压加到晶体管时使峰值电场与沟槽隔开。掺杂阱的深度比沟槽的预定深度浅。沟槽具有弧形的顶角和底角。在每个重掺杂体和对应的阱之间的界面处有突变结，从而在把电压加到晶体管时在界面区域中产生峰值电场。该阵列还包括包围阵列周边的电场终止结构。由电场终止结构包括其深度大于栅极形成沟槽深度的阱。电场终止结构包括围绕阵列周边连续延伸的终止沟槽，最好是多个同心排列的终止沟槽。
在另一个方面，本发明的特征还是一种半导体芯片(die)，它包括(a)在半导体衬底上排成一阵列的多个DMOS晶体管单元，每个DMOS晶体管单元包括栅极形成沟槽，每个所述栅极形成沟槽具有预定深度，所有栅极形成沟槽的深度基本上是相同的；以及(b)包围该阵列周边的电场终止结构，在半导体衬底中延伸的深度大于所述栅极形成沟槽的所述预定深度。
较佳实施例包括一个或多个以下的特征。电场终止结构包括掺杂阱。电场终止结构包括终止沟槽。电场终止结构包括多个同心排列的终止沟槽。每个DMOS晶体管单元还包括掺杂的重掺杂体，此掺杂重掺杂体在半导体衬底中延伸的深度限于小于栅极形成的沟槽预定深度。
本发明的特征还在于一种对沟槽型DMOS晶体管形成重掺杂体结构的方法，它包括(a)提供半导体衬底；(b)以第一能量和剂量把第一杂质注入衬底的一个区域；以及(c)接着以第二能量和剂量把第二杂质注入所述区域，所述的第二能量和剂量相对小于所述第一能量和剂量。
较佳实施例包括一个或多个以下特征。第一和第二杂质都包括硼。第一能量从大约150到200keV。第一剂量从大约1E15到5E15。第二能量从大约20到40keV。第二剂量从大约1E14到1E15。
此外，本发明的特征还在于一种形成沟槽型DMOS晶体管的源极的方法，它包括(a)提供半导体衬底；(b)以第一能量和剂量把第一杂质注入衬底的一个区域；以及(c)接着以第二能量和剂量把第二杂质注入该区域，第二能量和剂量相对小于第一能量和剂量。
较佳实施例包括一个或多个以下特征。第一杂质包括砷，第二杂质包括磷。第一能量从大约80到120keV。第一剂量从大约5E15到1E16。第二能量从大约40到70keV。第二剂量从大约1E15到5E15。在完成的DMOS晶体管中获得的源极深度从大约0.4到0.8μm。
在另一个方面，本发明的特征是一种制造沟槽型场效应晶体管的方法。此方法包括(a)绕半导体衬底的周长形成电场终止结；(b)在半导体衬底上形成外延层；(c)在外延层中构图和蚀刻出多个沟槽；(d)淀积多晶硅来填充这些沟槽；(e)以第一类型的杂质对多晶硅进行掺杂；(f)对衬底进行构图并注入相反的第二类型的杂质，以形成介于相邻沟槽之间的多个阱；(g)对衬底进行构图并注入第二类型的杂质，以在阱上方形成多个第二杂质类型的接触区和多个重掺杂体，每个重掺杂体相对于阱具有突变结；(h)对衬底进行构图并注入第一类型的杂质，以提供源区和第一杂质类型的接触区；以及(i)把介质加到半导体衬底的表面并对介质进行构图来暴露电接触区。
依据本发明的另一个方面，提供了一种制造沟槽晶体管的方法，包括：提供具有第一导电类型的杂质的半导体衬底；形成在半导体衬底中延伸至第一深度的沟槽；沿所述多个沟槽的沟槽壁形成一栅极介质材料层；以导电材料填充每个形成有栅极介质材料层的沟槽；在衬底中形成第二深度的掺杂阱，所述第二深度小于多个沟槽的所述第一深度，掺杂阱具有与所述第一导电类型相反的第二导电类型的杂质；形成在掺杂阱内延伸的第三深度的重掺杂体，所述第三深度小于所述掺杂阱的所述第二深度，所述重掺杂体具有第二导电类型的杂质且与所述阱形成突变结；在所述阱内形成源区，所述源区具有第一导电类型的杂质；以及相对于阱的深度调节突变结的位置，从而把晶体管峰值电场与沟槽隔开。
在上述方法中，还包括具有第二导电类型的杂质的深掺杂区，所述深掺杂区在衬底中延伸至第四深度，所述第四深度比所述沟槽的第一深度深。
在上述方法中，形成深掺杂区的步骤形成与所述衬底的PN结二极管，所述PN结二极管促进了提高晶体管的击穿电压。
在上述方法中，深掺杂区形成围绕衬底周边的终止结构。
在上述方法中，形成重掺杂体的步骤包括双注入工艺。
在上述方法中，双注入工艺包括：以第一能量水平和第一剂量第一次注入第一导电类型的杂质，以形成重掺杂体的第一掺杂区；以及以第二能量水平和第二剂量第二次注入第一导电类型的杂质，以形成重掺杂体的第二掺杂区。
在上述方法中，第一注入尽可能深地注入重掺杂体。
在上述方法中，第一能量水平高于第二能量水平。
在上述方法中，第一剂量高于第二剂量。
在上述方法中，形成重掺杂体的步骤包括扩散第二导电类型的杂质的工艺。
在上述方法中，形成重掺杂体的步骤包括在半导体衬底的表面处使用连续杂质源。
在上述方法中，形成多个沟槽的步骤包括对所述多个沟槽进行构图和蚀刻，所述多个沟槽沿纵轴平行延伸。
在上述方法中，还包括在相邻沟槽之间的衬底表面上形成接触区。
在上述方法中，形成接触区的步骤包括形成交替的源接触区和重掺杂体接触区。
从以下详细描述和权利要求书中将使本发明的其它特征和优点变得明显起来。
附图说明
图1是高倍放大的立体剖面示意图，示出依据本发明一个方面的包括多个DMOS晶体管的单元阵列的一部分。省略了源极金属层和一部分介质层来示出下面的层。图1A和1B是分别沿线A-A和B-B所取的图1阵列单行晶体管的剖面侧视图。在图1A和1B中，示出了源极金属和介质层。
图2是半导体芯片高倍放大的剖面侧视图，示出单元阵列和电场终止的一部分。
图3是示出用于形成图1沟槽型DMOS晶体管的较佳工艺的光掩模序列的流程图。
图4-4K是示出图3所示工艺各步骤的剖面侧视图。在图3中相应的方框下附带地示出图4-4K中详图的图号。
图5、5A和5B是反映出晶体管不同区域杂质浓度分布的扩散电阻曲线图。
具体实施方式
在图1中示出一单元阵列10，它包括多行12沟槽型DMOS晶体管。单元阵列10具有开放式单元结构，即沟槽14只沿一个方向排列而不是形成一个格栅。通过使n+源触点16和p+触点18按照在沟槽14之间交错平行排成行20而形成各个单元。在图1A的剖面中示出具有n+源触点的每行区域的结构，而图1B中示出具有p+触点的区域。
如图1A和1B所示，每个沟槽型DMOS晶体管包括掺杂的n+衬底(漏极)层22、轻度掺杂的n外延层24和栅极28。栅极28包括填充沟槽14的导电多晶硅。栅氧化物26涂敷沟槽壁并位于多晶硅下面。多晶硅上表面与半导体衬底表面30的凹陷距离为R(一般从大约0到0.4μm)。N+掺杂的源区32A、32B分别位于沟槽14的两侧。介质层35覆盖沟槽开口和两个源区32A、32B。p+重掺杂体区34在相邻单元的源区之间延伸，其下面是底部平坦的p阱36。在具有n+触点16的单元阵列区域中，有一浅的n+掺杂接触区在n+源区之间延伸。源金属层38覆盖单元阵列的表面。
图1A和1B所示的晶体管包括增强晶体管的耐久性及其抗雪崩击穿劣化的几个特征。
第一，相对于沟槽14和p阱平坦底部的深度来选择p+重掺杂体区域34的深度，从而在把电压加到晶体管时将使峰值电场出现在相邻沟槽之间的中间处。对于不同的布局，p+重掺杂体、p阱和沟槽的较佳相对深度是不同的。然而，根据经验(通过观察峰值电场的位置)或通过有限元分析可容易地确定较佳相对深度。
第二，沟槽14的底角是弧形的(最好顶角也是弧形的；此特征未示出)。可使用1997年10月28日提交的 08/959,197号美国在审查申请中所述的工艺来实现角的弧形。沟槽的弧形角还将把峰值电场从沟槽转角处移开并朝向相邻沟槽之间的中间位置。
第三，p+重掺杂体和p阱之间界面处的突变结使得在界面区域中产生峰值电场。在峰值电场的位置处引起雪崩倍增，这样引导热载流子离开敏感的栅极氧化物和沟道区。结果，此结构提高了可靠性和雪崩耐久性而不牺牲如同较深重掺杂体结的单元密度。可通过以下所述的双掺杂工艺或通过大部分为半导体领域中所公知的其它突变结形成工艺来实现此突变结。
最后，参考图2，单元阵列被电场终止结40所包围，这增加了器件的击穿电压并把雪崩电流从单元阵列引到芯片周边。电场终止结40是深的p+阱，其最深点最好从大约1到3μm，此深度大于p+重掺杂体区域34的深度以减小结的曲率所引起的电场。制作上述晶体管的较佳工艺如图3的流程图所示，图4-4K示意地示出各个步骤。注意，以下描述一些不需要说明的常规步骤，这些步骤没有在图4-4K中示出。如图3的箭头所示和以下所述，可改变图4-4K所示步骤的顺序。此外，如下所述，图4-4K所示的一些步骤是任意选择的。
最初提供半导体衬底。衬底最好是N++Si衬底，具有例如500μm的标准厚度以及例如0.001到0.005Ohm-cm的非常低的电阻率。众所周知，在此衬底上淀积外延层，其厚度最好从大约4到10μm。外延层的电阻率最好从大约0.1到3.0Ohm-cm。
接着，由图4-4C中所示的步骤来形成电场终止结40。在图4中，在外延层的表面上形成氧化层。氧化物的厚度最好从大约5到10K。接着，如图4A所示，对氧化层进行构图和蚀刻来限定一掩模，引入p+杂质来形成深的p+阱电场终止。适当的杂质是硼，以大约40到100keV的能量和1E14(1×1014)到1E16cm-2的剂量注入。如图4B所示，然后再通过例如扩散使p+杂质进入衬底，在p+结上形成场氧化层。氧化层厚度最好从大约4到10k。最后，对衬底有源区(形成单元阵列的区域)的氧化物(图4)进行构图并通过适当的蚀刻工艺除去该氧化物，只在适当区域中留下场氧化物。这样让衬底准备作形成单元阵列的以下步骤。
注意，作为替代步骤4-4c的方法，可用包围单元阵列周边且能减小电场和增大抗雪崩击穿劣化的环状沟槽来形成适当的电场终止结构。此沟槽电场终止不需要有效的场氧化物或深的p+重掺杂体结。结果，可减少工艺步骤的数目。例如，在5,430,324号美国专利中描述了使用沟槽环(或多个同心的沟槽环)来形成电场终止，这里引用其全部内容。此沟槽的深度最好与单元阵列中的沟槽深度相同。
由图4D-4K所示的步骤来形成单元阵列。首先，在衬底的外延层中进行构图并蚀刻出多个沟槽(图4D)。如上所述，最好使用08/959,197号美国审查中专利申请中所述的工艺来形成沟槽，从而每个沟槽的顶角和底角将变成光滑的弧形。如图1所示和以上所述，沟槽构图只沿一个方向排列限定成开放式单元结构。在形成沟槽后，如本领域内众所周知的，在沟槽壁上形成栅氧化层。栅氧化层的厚度最好从大约100到800。
接着，如图4E所示，依据沟槽宽度(如图4E的虚线所示)，淀积厚度从大约1到2μm的多晶硅来填充沟槽并覆盖衬底表面。然后利用其厚度相对于沟槽宽度的特性对该层进行平面化，通常从大约2到5k(如图4E中的实线所示)。然后，通过例如常规的POCL3掺杂或磷注入把多晶硅掺杂成为n型。由于对高度掺杂衬底再进行任何掺杂也不太可能增强缺陷吸收，所以不需要对晶片反面进行剥离(这通常在对多晶硅进行掺杂前进行以增强缺陷吸收)。
然后，如图4F所示，以光致抗蚀剂掩模对多晶硅进行构图和蚀刻，以把多晶硅从沟槽区中除去。在对多晶硅进行完全蚀刻以从衬底表面除去所有的多晶硅时，在沟槽中的多晶硅顶部和衬底表面之间自然地留下一小凹槽。必须如此控制此凹槽的深度，从而该深度不超出将在以后步骤中形成的n+源结的深度。如下所述，为了减少对工艺中这方面的控制需求，形成相对深的n+源结。
然后，如图4G所示，通过注入杂质(例如以30到100keV的能量和1E13到1E15的剂量注入的硼)并使用常规的引入技术使该杂质进入大约1到3μm的深度来形成p-阱。
如图3箭头所示，可在n+源结形成以前或在其后来进行接着的两个步骤(形成p+重掺杂体)。可以任一种顺序来进行p+重掺杂体的形成和n+源结的形成，这是因为它们都是抗蚀剂掩模的步骤且在它们之间没有扩散步骤。这有利于提高工艺灵活性。以下将描述在源极形成前进行的p+重掺杂体形成步骤；应理解，可通过简单地改变以下所述步骤的顺序来首先进行n+源极形成。
首先，如图4H所示，在将不被掺杂成为p+的区域上形成掩模。(注意，在已加上用于接触孔的介质层并对其进行构图(见以下的图4K)后从而介质本身提供了掩模后，如果形成p+重掺杂体则不需要此掩模步骤)。如上所述，p-阱和p+重掺杂体之间界面处的结最好是突变的。为此，进行杂质(例如，硼)的双注入。例如，较佳的双注入是能量为150到200keV和剂量为1E15到5E15的第一硼注入和能量为20到40keV和剂量为1E14到1E15的第二硼注入。高能量的第一注入使p+重掺杂体尽可能深地进入衬底，从而不会补偿以后引入的n+源结。能量较低/剂量较低的第二注入使p+重掺杂体从第一注入中形成的深区域向上延伸至衬底表面，以提供p+触点18。在此工艺过程中获得的p+重掺杂体结最好从0.4到1μm深(进入后的最终结深最好为大约0.5到1.5μm)，且它包括p阱界面附近的杂质浓度高的区域以及p+重掺杂体接触表面处杂质浓度相对低的区域。在图5中示出较佳的浓度分布。
本领域的技术人员应知道，可通过杂质扩散、使用表面处的连续杂质源或使用扩散较慢的原子等许多其它方式来形成突变结。
在形成p+重掺杂体后，进行常规的抗蚀剂剥离工艺以除去掩模，对新的掩模进行构图以制备用于形成n+源结的衬底。此掩模为n+阻挡掩模，如图4I所示对它进行构图以覆盖将提供p+触点18(图1和1B)的衬底表面区域。这使得在n型掺杂后形成交错的p+和n+触点(见相应于图1A和1B的图4I中的线A-A和B-B以及剖面图A-A和B-B)。
然后，使用双注入来形成n+源区和n+触点。例如，较佳的双注入工艺是能量从80到120keV及剂量从5E15到1E16的第一砷注入，接着是能量从40到70keV及剂量从1E15到5E15的第二磷注入。磷注入形成相对深的n+源结，如上所述，这样使得对多晶硅凹槽的深度工艺更灵活。磷离子在注入期间以及在以后的扩散步骤中将更加深入衬底。这样，有利于使n+区域在扩散后具有大约0.4到0.8μm的深度。砷注入使n+源延伸到衬底表面，还通过对所需接触区中p+重掺杂体的p型表面补偿(转换)成为n型来形成n+触点16(见图1和1A)。在图5A和5B中分别示出沿沟槽边缘的n+源和n+触点的较佳薄层电阻曲线。
这样，如上所述，通过用适当的掩模对衬底进行构图并分别以第一p+注入和第二n+注入来形成图1所示交错的p+和n+触点18和16。这种形成交错触点的方式有利于形成单元间距比这种阵列的典型间距小的开放式单元阵列，从而提高单元密度和降低Rdson。
接着，进行常规的n+引入来激活杂质。使用900℃下最好为10分钟的短循环，从而产生激活而没有过度扩散。
然后，在整个衬底表面上淀积例如硼磷硅酸玻璃(BPSG)等介质材料，该材料以常规的方式流动(图4J)，其后对介质进行构图及蚀刻以在n+和p+触点16、18上限定电接触开口。
如上所述，如有必要，此时(而不是在n+源形成前)可进行p+重掺杂体注入步骤，无需掩模，从而减少成本和工艺时间。
接着，介质在例如氮气净化等惰性气体中回流。如果在此之前刚注入了p+重掺杂体，则需要此步骤来激活p+杂质。如果在n+进入前早已注入了p+重掺杂体，若接触开口周围介质表面的边缘足够光滑，则可省略此步骤。
然后，通过半导体领域内公知的常规金属化、钝化淀积和熔合步骤来完成此单元阵列。
其它实施例都包括在权利要求书的范围内。例如，虽然以上描述了n沟道晶体管，但本发明的工艺还可用于形成p沟道晶体管。为此，可以简单地颠倒以上描述中的“p”和“n”，即上述区域中的“p”掺杂将换成“n”掺杂，反之亦然。

Claims (25)

1.一种晶体管单元阵列，其特征在于包括：
半导体衬底；
基本上相互平行排列且沿第一方向延伸的多个栅极形成沟槽，相邻沟槽之间的空间限定一接触区，每个沟槽在所述衬底中延伸预定的深度，此预定深度对所有所述栅极形成沟槽基本上是相同的；
包围每个沟槽且位于沟槽两侧并沿沟槽的长度延伸的一对掺杂的源结；
位于每对栅极形成沟槽之间且位于每个源结附近的掺杂重掺杂体，每个所述重掺杂体的最深部分在所述半导体衬底中延伸的深度比所述沟槽的所述预定深度浅；
在重掺杂体下面且包围每个重掺杂体的掺杂阱；以及
位于半导体衬底表面并沿接触区的长度交替排列的p+和n+触点。
2.如权利要求1所述的晶体管单元阵列，其特征在于每个所述掺杂阱具有基本上平坦的底部。
3.如权利要求1所述的晶体管单元阵列，其特征在于相对于阱和栅极形成沟槽的深度来选择每个重掺杂体区域的深度，从而在把电压加到晶体管时峰值电场将出现在相邻栅极形成沟槽的中间。
4.如权利要求1所述的晶体管单元阵列，其特征在于每个所述掺杂阱的深度小于所述栅极形成沟槽的预定深度。
5.如权利要求1所述的晶体管单元阵列，其特征在于每个所述栅极形成沟槽具有弧形的顶角和底角。
6.如权利要求1所述的晶体管单元阵列，其特征在于在重掺杂体和阱之间的每个界面处存在突变结，使得在把电压加到晶体管时在界面区域中产生峰值电场。
7.如权利要求1所述的晶体管单元阵列，其特征在于还包括包围阵列周边的电场终止结构。
8.如权利要求7所述的晶体管单元阵列，其特征在于所述电场终止结构包括深度大于栅极形成沟槽的深度的阱。
9.如权利要求7所述的晶体管单元阵列，其特征在于所述电场终止结构包括绕阵列周边连续延伸的终止沟槽。
10.如权利要求9所述的晶体管单元阵列，其特征在于所述电场终止结构包括同心排列的多个终止沟槽。
11.一种半导体芯片，其特征在于包括：
在半导体衬底上排列成阵列的多个DMOS晶体管单元，每个DMOS晶体管单元包括栅极形成沟槽，每个所述栅极形成沟槽具有预定深度，所有的栅极形成沟槽的深度基本上相同；以及
包围阵列周边的电场终止结构，所述结构在半导体衬底中延伸的深度比所述栅极形成沟槽的预定深度深。
12.如权利要求11所述的半导体芯片，其特征在于所述电场终止结构包括掺杂阱。
13.如权利要求11所述的半导体芯片，其特征在于所述电场终止结构包括终止沟槽。
14.如权利要求13所述的半导体芯片，其特征在于所述电场终止结构包括同心排列的多个终止沟槽。
15.如权利要求11所述的半导体芯片，其特征在于每个所述DMOS晶体管单元还包括掺杂的重掺杂体，所述重掺杂体在所述半导体衬底中延伸的深度小于所述栅极形成沟槽的所述预定深度。
16.一种制造沟槽型场效应晶体管的方法，其特征在于包括：
绕半导体衬底的周长形成电场终止结；
在半导体衬底上形成外延层；
在外延层中进行构图并蚀刻出多个沟槽；
淀积多晶硅来填充这些沟槽；
以第一类型的杂质对多晶硅进行掺杂；
对衬底进行构图并注入相反的第二类型的杂质，以形成介于相邻沟槽之间的多个阱；
对衬底进行构图并注入第二类型的杂质，以形成位于这些阱上方的多个第二杂质类型的接触区和多个重掺杂体，每个重掺杂体具有与阱相应的突变结；
对衬底进行构图并注入第一类型的杂质，以提供源区和第一杂质类型的接触区；以及
把介质加到半导体衬底的表面并对介质进行构图以暴露电接触区。
17.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于沟槽被构图成沿一个方向延伸且基本上相互平行。
18.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于构图和注入步骤还包括使第一杂质类型的接触区和第二杂质类型的接触区交替排列并在相邻沟槽之间线性延伸。
19.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于形成重掺杂体的注入步骤还包括以第一能量和剂量注入第一杂质且以第二能量和剂量注入第二杂质，第二能量和剂量相对小于第一能量和剂量。
20.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于形成源区的注入步骤包括以第一能量和剂量注入第一杂质并以第二能量和剂量注入第二杂质，第二能量和剂量相对小于第一能量和剂量。
21.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于在形成源区前形成重掺杂体。
22.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于在形成重掺杂体前形成源区。
23.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于通过形成沟槽环来形成所述电场终止。
24.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于通过形成以第二杂质类型的杂质掺杂的深阱来形成所述电场终止。
25.如权利要求16所述的制造沟槽型场效应晶体管的方法，其特征在于在形成重掺杂体和第二杂质类型的触点前加上所述介质，所述介质对重掺杂体和第二杂质类型的触点进行构图提供掩模。
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CN104934491A (zh) * 2014-03-19 2015-09-23 中芯国际集成电路制造(上海)有限公司 光电二极管、其制作方法及图像传感器件
CN104934491B (zh) * 2014-03-19 2017-06-06 中芯国际集成电路制造(上海)有限公司 光电二极管、其制作方法及图像传感器件
CN105321998A (zh) * 2014-07-10 2016-02-10 新唐科技股份有限公司 半导体元件及其制作方法
CN106537603A (zh) * 2015-02-16 2017-03-22 富士电机株式会社 半导体装置和半导体装置的制造方法
US10297682B2 (en) 2015-02-16 2019-05-21 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device
CN106537603B (zh) * 2015-02-16 2019-12-13 富士电机株式会社 半导体装置和半导体装置的制造方法
US10720519B2 (en) 2015-02-16 2020-07-21 Fuji Electric Co., Ltd. Semiconductor device and manufacturing method of semiconductor device

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US7511339B2 (en) 2009-03-31
CN100461415C (zh) 2009-02-11
JPH11243196A (ja) 1999-09-07
SG83108A1 (en) 2001-09-18
US20010023104A1 (en) 2001-09-20
US20100264487A1 (en) 2010-10-21
US20050079676A1 (en) 2005-04-14
HK1109495A1 (en) 2008-06-06
CN1227418A (zh) 1999-09-01
US6429481B1 (en) 2002-08-06
US6521497B2 (en) 2003-02-18
US20020140027A1 (en) 2002-10-03
US6710406B2 (en) 2004-03-23
US20090134458A1 (en) 2009-05-28
CN100338778C (zh) 2007-09-19
TW465047B (en) 2001-11-21
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KR19990045294A (ko) 1999-06-25
US20100112767A1 (en) 2010-05-06
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US6828195B2 (en) 2004-12-07
US8044463B2 (en) 2011-10-25
US7736978B2 (en) 2010-06-15
US7148111B2 (en) 2006-12-12
US20040145015A1 (en) 2004-07-29
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US8476133B2 (en) 2013-07-02
US20070042551A1 (en) 2007-02-22

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