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JPS56131960A - Semiconductor device and its preparation - Google Patents

Semiconductor device and its preparation

Info

Publication number
JPS56131960A
JPS56131960A JP3529780A JP3529780A JPS56131960A JP S56131960 A JPS56131960 A JP S56131960A JP 3529780 A JP3529780 A JP 3529780A JP 3529780 A JP3529780 A JP 3529780A JP S56131960 A JPS56131960 A JP S56131960A
Authority
JP
Japan
Prior art keywords
withstanding voltage
sio2
face
covering
mechanical strength
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3529780A
Other languages
Japanese (ja)
Inventor
Kosuke Yasuno
Kosei Kajiwara
Tatsunori Nakajima
Kazutoshi Nagano
Seiji Onaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3529780A priority Critical patent/JPS56131960A/en
Publication of JPS56131960A publication Critical patent/JPS56131960A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE:To obtain FET of high withstanding voltage, high mechanical strength and high density by providing a concave having a side face and a bottom face on the main face of Si substrate, performing double diffusions from the side face. CONSTITUTION:When N<-> epitaxial layer on the surface of N<+> type substrate (100) is anisotropically etched with SiO2 as a mask, a groove with flat bottom is formed wherein mechanical strength thereof increases more than V groove. Moreover, by covering with SiO2 8, removing side faces only selectively, performing double diffusion, P layer 3, N<+> source 4' which become channel are formed by ion implantation and heat-treated. Next, removing the film 8, covering with gate oxide films 9 and 9', a gate electrode 10 is provided. In this consitution, four channels per concave are obtained and high density effect is obtained easily. Further, as there are no regions for electric field to easily concentrate, high withstanding voltage is available, thereby becoming withstanding voltage approximately of N<-> epitaxial layer. By so doing, a fine insulating gate type device of high performance can be obtained.
JP3529780A 1980-03-19 1980-03-19 Semiconductor device and its preparation Pending JPS56131960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3529780A JPS56131960A (en) 1980-03-19 1980-03-19 Semiconductor device and its preparation

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3529780A JPS56131960A (en) 1980-03-19 1980-03-19 Semiconductor device and its preparation

Publications (1)

Publication Number Publication Date
JPS56131960A true JPS56131960A (en) 1981-10-15

Family

ID=12437834

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3529780A Pending JPS56131960A (en) 1980-03-19 1980-03-19 Semiconductor device and its preparation

Country Status (1)

Country Link
JP (1) JPS56131960A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106870A (en) * 1981-12-18 1983-06-25 Nissan Motor Co Ltd Power metal oxide semiconductor field-effect transistor
JPH01185976A (en) * 1988-01-20 1989-07-25 Mitsubishi Electric Corp Power mos-fet
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58106870A (en) * 1981-12-18 1983-06-25 Nissan Motor Co Ltd Power metal oxide semiconductor field-effect transistor
JPH01185976A (en) * 1988-01-20 1989-07-25 Mitsubishi Electric Corp Power mos-fet
US6429481B1 (en) 1997-11-14 2002-08-06 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6710406B2 (en) 1997-11-14 2004-03-23 Fairchild Semiconductor Corporation Field effect transistor and method of its manufacture
US6828195B2 (en) 1997-11-14 2004-12-07 Fairchild Semiconductor Corporation Method of manufacturing a trench transistor having a heavy body region
US7148111B2 (en) 1997-11-14 2006-12-12 Fairchild Semiconductor Corporation Method of manufacturing a trench transistor having a heavy body region
US7696571B2 (en) 1997-11-14 2010-04-13 Fairchild Semiconductor Corporation Method of manufacturing a trench transistor having a heavy body region
US8044463B2 (en) 1997-11-14 2011-10-25 Fairchild Semiconductor Corporation Method of manufacturing a trench transistor having a heavy body region

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