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CN103515260B - 封装内封装及其形成方法 - Google Patents

封装内封装及其形成方法 Download PDF

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Publication number
CN103515260B
CN103515260B CN201310261023.3A CN201310261023A CN103515260B CN 103515260 B CN103515260 B CN 103515260B CN 201310261023 A CN201310261023 A CN 201310261023A CN 103515260 B CN103515260 B CN 103515260B
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semiconductor
semiconductor chip
semiconductor module
couple
chip
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CN103515260A (zh
Inventor
拉尔夫·奥特伦巴
约瑟夫·赫格劳尔
克劳斯·席斯
克萨韦尔·施勒格尔
于尔根·施雷德尔
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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Abstract

本发明涉及封装内封装及其形成方法。根据本发明的实施方式，半导体器件包括具有多个引线和小片焊盘的引线框、以及被连接到所述引线框的小片焊盘的半导体模块。所述半导体模块包括配置在第一密封剂中的第一半导体芯片。所述半导体模块具有耦接到所述第一半导体芯片的多个接触垫。所述半导体器件进一步包括将所述多个接触垫与多个引线耦接的多个互连件、以及被配置在所述半导体模块和引线框的第二密封剂。

Description

封装内封装及其形成方法
技术领域
本发明主要涉及半导体器件，更具体地，涉及封装内封装及其形成方法。
背景技术
半导体器件用于各种电子应用和其他应用。除了其他外，半导体器件包括集成电路或分离器件，其通过在半导体晶圆上沉积一种或多种薄膜材料在半导体晶圆上形成并对薄膜材料图案化以形成集成电路，从而在半导体晶圆上形成。
半导体器件通常封装在陶瓷或塑料壳体内，以保护半导体器件免受物理损坏或腐蚀。该封装也支持电触点，电触点是连接半导体器件(也被称为小片(die)或芯片(chip))与在该封装外的其他器件所需要的。根据半导体器件的类型和被封装半导体器件的预期用途，可采用许多不同封装类型。典型的封装特征(例如封装尺寸、引脚数等)可以符合电子设备工程联合委员会(JEDEC)的开放标准等。封装也可以被称为半导体器件装配或简称为装配。
因此，尽管由于半导体技术的发展，半导体芯片的大小不断改变，但因为需要符合标准的封装尺寸，封装的大小不会改变。进一步地，随着许多应用的增加，单一的封装可能包括多个半导体小片或芯片。不过，常规的封装不能支持多个半导体芯片或微小的半导体芯片。
发明内容
通过本发明的示例性实施方式，通常可解决或避开上述和其他问题，并且实现了技术优势。
根据本发明的实施方式，半导体器件包括具有多个引线(lead)和小片焊盘(diepaddle)的引线框以及被附接到引线框的小片焊盘的半导体模块。半导体模块包括被配置在第一密封剂中的第一半导体芯片。半导体模块具有耦接到第一半导体芯片的多个接触垫。半导体器件进一步包括将多个接触垫与多个引线耦接的多个互连件(interconnect)，以及被配置在所述半导体模块和引线框的第二密封剂(encapsulant)。
根据本发明的实施方式，半导体器件包括具有多个引线和小片焊盘的引线框以及被配置在引线框的小片焊盘上的半导体模块。半导体模块包括第一半导体芯片，以及耦接到第一半导体芯片的多个接触垫。半导体模块是嵌入式的晶圆级封装。密封剂被配置在半导体模块和引线框。
根据本发明的实施方式，半导体器件包括被配置在引线框封装中的半导体封装。在引线框封装是符合标准的标准封装同时，半导体封装是非标准封装。半导体封装和引线框封装具有基本相同的功能。
根据本发明的实施方式，形成半导体器件的方法包括：提供具有多个引线和小片焊盘的引线框。提供包括被配置在第一密封剂中的第一半导体芯片的半导体模块。所述半导体模块具有耦接到第一半导体芯片的多个接触垫。将所述半导体模块附接到引线框的小片焊盘。将多个接触垫电耦接多个引线。用第二密封剂密封(encapsulate)所述半导体模块和引线框。
附图说明
为了更完整地理解本发明及其优势，现在参考结合附图的下列描述，其中：
图1A和图1B示出了根据本发明实施方式的半导体封装，其中图1A示出俯视图，而图1B示出截面图；
图2A和图2B示出了说明前侧再分配线的半导体封装的另一个实施方式，其中图2A示出俯视图，而图2B示出截面图；
图3A至图3D以及图3E-1和图3E-2示出半导体封装的进一步的结构实施方式，其中图3A示出半导体封装的引线框和半导体模块，而图3B至图3E-2示出半导体模块的例子；
图4至图15示出根据本发明的实施方式在制造的各个阶段时的半导体封装的截面图；
图16和图17示出根据本发明的备选实施方式在制造的各个阶段时的半导体封装的截面图；以及
图18示出半导体封装的另一个实施方式，其示出封装内的堆叠半导体封装。
除非有特别声明，否则在不同附图中的对应数字编号和符号通常指的是对应的部件。绘制的图形是为了清楚说明实施方式的相应方面，不一定是按比例绘制。
具体实施方式
各个实施方式的制造和使用在下面详细讨论。不过应当明白，本发明提供能够在各种特定背景下实现的适用于很多应用的发明概念。讨论的具体实施方式仅仅是制造和使用本发明的具体方式的示例，其不限制本发明的范围。
本发明的实施方式能够形成具有标准尺寸的封装，例如，符合JEDEC标准的封装，而且能够在不增加封装成本的情况下，实现多个半导体芯片在封装内的集成。
本发明的结构实施方式将利用图1描述。本发明的备选结构实施方式将利用图2、3和18描述。半导体封装形成的方法将根据本发明实施方式利用图4至图15和图16和图17描述。
图1A和1B示出根据本发明实施方式的半导体封装，其中图1A示出俯视图，而图1B示出截面图。
参考图1A，半导体封装包括具有小片焊盘310和多个引线320的引线框300。半导体模块100被附接到引线框300的小片焊盘310。在不同的实施方式中，半导体模块100可以包括多个半导体芯片20。
在各种不同的实施方式中，多个半导体芯片20可以包括不同类型的小片，小片包括集成电路或分立器件。在一个或多个实施方式中，多个半导体芯片20中的每个可以包括逻辑芯片、存储器芯片、模拟芯片、混合信号芯片以及上述的组合，例如片上系统。多个半导体芯片20可以包括各种类型的有源器件和无源器件，例如二极管、晶体管、闸流管、电容器、电感器、电阻器、光电器件、传感器、微电机系统等。在各种不同的实施方式中，多个半导体芯片20可以是相似类型的半导体芯片或不同类型的半导体芯片。
在各种不同的实施方式中，多个半导体芯片20可以在硅基板上形成。或者，在其他实施方式中，多个半导体芯片20已经在碳化硅(SiC)上形成。在一个实施方式中，多个半导体芯片20已经至少部分地在氮化镓(GaN)上形成。
在各种不同的实施方式中，多个半导体芯片20可以包括功率半导体芯片，在一个实施方式中，其可以是分立器件。在一个实施方式中，所述多个半导体芯片20中的至少部分是两端子器件，例如PIN二极管或肖特基二极管。在一个或多个实施方式中，所述多个半导体芯片20中的至少部分是三端子器件，例如功率金属绝缘体半导体场效应晶体管(MISFET)、结型场效应晶体管(JFET)、双极结型晶体管(BJT)、绝缘栅双极型晶体管(IGBT)或闸流管。
在某些实施方式中，半导体模块100包括用于将半导体模块100安装在电路板上的多个接触垫90。作为示例，多个接触垫90包括第一接触垫110、第二接触垫120、以及第三接触垫130，其用于为多个半导体芯片20中的一个形成触点。多个接触垫90中的第三接触垫130可以耦接(连接)到多个半导体芯片20的后侧。例如，在一个或多个实施方式中，可以利用被配置在第一密封剂50中的穿过基板的通孔260耦接第三接触垫130。类似地，多个半导体芯片20的其他芯片包括第一接触垫110、第二接触垫120和第三接触垫130。
在各种不同的实施方式中，利用接合线(wire bond，焊线)330，多个半导体芯片20可以耦接到多个引线320。在备选实施方式中，多个半导体芯片20可以利用其他类型的互连件(例如夹子(clip)、引线、条带(strip)以及其他合适的连接方式)耦接。
如图1A所示，在半导体模块100内的多个半导体芯片20被嵌入在密封剂50中。半导体模块100自身被嵌入在外部的密封剂350中。
参考图1B，利用小片附接层280，半导体模块100被附接到引线框300的小片焊盘310。在各种不同的实施方式中，小片附接层280可以是绝缘层或导电层。
如图1B的截面图所示，所述多个半导体芯片20被嵌入在密封剂50中。第一接触垫110被配置在多个半导体芯片20上方。后侧填充材料250耦接到多个半导体芯片20的后侧接触区域。利用被嵌入在密封剂50中的穿过基板的通孔260，后侧填充材料250耦接到半导体模块100的前侧。多个半导体芯片20的毗邻芯片被绝缘的密封剂50相互隔离。利用接合线330，包括第一接触垫110和第三接触垫130的多个接触垫90耦接到多个引线320。接合线330可以利用球形或楔形的焊球340接合。
在各种不同的实施方式中，半导体模块100可以是不符合标准(例如JEDEC标准)的封装的模块。不过，在各种不同的实施方式中，形成的引线框封装符合标准(例如JEDEC标准)的封装。不过，半导体模块100和引线框封装具有类似的功能和操作，例如，除了在半导体模块100中的那些半导体器件以外，引线框封装可以不具有额外的半导体器件。
图2A和图2B示出说明前侧再分配线(front side redistribution line)的半导体封装的另一个实施方式，其中图2A示出俯视图，而图2B示出截面图。
除关于图1所述的实施方式之外，多个半导体芯片20可以例如利用前侧再分配线150在半导体模块100内互连。因此，在半导体模块100上的多个接触垫90的垫数量可以和引线框300的多个引线320或引脚(pin)的数量不同。例如，作为图示，半导体模块100具有六个接触垫，而引线框300仅有五个引线。
图3A至图3E示出半导体封装的进一步的结构实施方式，其中图3A示出半导体封装的引线框和半导体模块，而图3B至3E示出半导体模块的例子。
图3A示出具有多个引线320和小片焊盘310的引线框300。引线框300还包括从多个引线320延伸的多个引脚305。半导体模块100被配置在小片焊盘310上。
参考图3B，半导体模块100可以包括多个接触垫90，接触垫90由前侧再分配线150与功能芯片25(例如逻辑芯片、模拟芯片或存储器芯片)隔离。如图所示，利用前侧再分配线150，多个半导体芯片20可以互连，前侧再分配线150还被用于耦接多个接触垫90。
图3C示出本发明的备选实施方式，其包括功率器件，例如高压分立式晶体管。如图所示，多个接触垫90包括第一接触垫110、第二接触垫120、耦接到后侧导体(例如导电填充材料250)的第三接触垫130、以及第四接触垫140。
图3D示出本发明的另一个备选实施方式，其包括低压集成电路。包括图3E-1和3E-2的图3E示出本发明的进一步的实施方式，其包括已利用前侧再分配线互连的多个半导体芯片。在图3E-1中，利用假想线(phantom line)示出接触垫90以突出在接触垫90下面的特征。图3E-2将接触垫90示出作为固体材料，使得在其下面的特征以虚线示出。
图4至图15示出根据本发明的实施方式制造半导体封装的方法。
图4示出根据本发明的实施方式，在制造期间，在将单片化小片放置在载体(carrier)上后的半导体封装。
参考图4，多个半导体芯片20被放置在载体10上。在各种不同的实施方式中，如图4所示，多个半导体芯片20的具有有源区域的第一表面被放置为在面向载体10。
利用常规处理，可以形成多个半导体芯片20，例如在晶圆内，通过切割形成多个半导体芯片20。如上所述，多个半导体芯片20可以在硅基板，例如块状(bulk)硅基板或绝缘体上硅(SOI)基板上形成。可供选择地，半导体芯片20可以是在碳化硅(SiC)上形成的器件。本发明的实施方式还可以包括在化合物半导体基板上形成的器件，以及可以包括异质外延基板上的器件。在一个实施方式中，半导体芯片20是至少部分在氮化镓(GaN)上形成的器件，所述氮化镓可以是蓝宝石或硅基板上的GaN。
在各种不同的实施方式中，多个半导体芯片20可以包括功率芯片，其提取例如大电流(例如大于30安培)。在各种不同的实施方式中，多个半导体芯片20可以包括分立式垂直器件，例如两个或三个端子的功率器件。多个半导体芯片20的例子包括PIN或肖特基二极管、MISFET、JFET、BJT、IGBT、或闸流管。在各种不同的实施方式中，多个半导体芯片20可以包括功率芯片21和功能芯片25(例如逻辑芯片或存储器芯片)的组合。
在各种不同的实施方式中，功率芯片21可以是被配置为在大约20V到大约1000V操作的垂直半导体器件。在一个实施方式中，功率芯片21被配置为在大约20V到大约100V操作。在另一个实施方式中，功率芯片21被配置为在大约100V到大约500V操作。在另一个实施方式中，功率芯片21被配置为在大约500V到大约1000V操作。在一个实施方式中，功率芯片21是NPN晶体管。在另一个实施方式中，功率芯片21是PNP晶体管。在另一个实施方式中，功率芯片21是n沟道MISFET。在进一步实施方式中，功率芯片21是p沟道MISFET。在一个或多个实施方式中，功率芯片21可以包括多个器件，例如垂直MISFET和二极管，或者可供选择地，由绝缘区域分隔的两个MISFET器件。
在各种不同的实施方式中，多个半导体芯片20从其顶面11到其底面12的厚度可以少于50μm。在一个或多个实施方式中，多个半导体芯片20从其顶面11到其底面12的厚度可以少于20μm。在一个或多个实施方式中，多个半导体芯片20从其顶面11到其底面12的厚度可以少于10μm。
接下来，多个半导体芯片20被附接到载体10，载体10提供在处理期间的机械支持和稳定性。在各种不同的实施方式中，载体10可以是由刚性材料(例如像镍、钢或不锈钢的金属、层压体、薄膜或材料堆叠体)制成的平板。载体10可以具有至少一个平坦表面，多个半导体芯片(20)可以被放置在该平坦表面上。在一个或多个实施方式中，载体10可以是圆形或正方形的，不过在各种不同的实施方式中，载体10可以是任意合适的形状。在各种不同的实施方式中，载体10可以具有任何适当的大小。在某些实施方式中，载体10可以包括胶粘带，例如，被层压在载体10上的双面胶带。载体10可以包括框架，在一个实施方式中，其是带有粘合箔的环状结构(环形的)。在一个或多个实施方式中，可以由框架沿着外缘支持粘合箔。
在各种不同的实施方式中，利用粘合层35，多个半导体芯片20可以被附接。在各种不同的实施方式中，粘合层35可以包括胶水或其他粘合型材料。在各种不同的实施方式中，粘合层35可以是薄的，例如在一个实施方式中，少于大约100μm，以及在另一个实施方式中，在大约1μm到大约50μm之间。
图5示出根据本发明的实施方式，在制造期间，在形成重组晶圆(reconstitutedwafer)后的半导体封装。
如图5所示，密封剂50被施加在多个半导体芯片20上，并且部分密封多个半导体芯片20。在一个实施方式中，利用模塑工艺(molding process)(例如压缩模塑、转移模塑工艺、注射模塑、粒化模塑、粉末模塑、液体模塑)以及诸如模板印刷或丝网印刷的印刷工艺施加密封剂50。
在各种不同的实施方式中，密封剂50包括电介质材料，以及在一个实施方式中，可以包括模塑化合物(mold compound)。在其他实施方式中，密封剂50可以包括一个或多个聚合物、共聚物、生物聚合物、纤维浸渍聚合物(例如，在树脂中的碳或玻璃纤维)、粒子填充聚合物、以及其他有机材料。在一个或多个实施方式中，密封剂50包括未利用模塑化合物成形的密封胶(sealant)以及例如环氧树脂和/或硅树脂的材料。在各种不同的实施方式中，密封剂50可以由任何适当的硬质塑料、热塑性塑料、热固性材料或层压体制成。在某些实施方式中，密封剂50的材料可以包括填充材料。在一个实施方式中，密封剂50可以包括环氧树脂材料和填充材料，其中所述填充材料包括小颗粒的玻璃或其他电绝缘矿物填料材料，例如氧化铝或有机填充材料。密封剂50可以被固化，即进行热处理以使其硬化，从而形成气密密封保护的半导体芯片20。固化过程使密封剂50硬化，从而形成保持多个半导体芯片20的单一基板。这样的基板被称为重组晶圆5。
图6示出根据本发明的实施方式，在制造期间，在将重组晶圆与载体分离后的半导体封装。
参考图6，载体10被除去以分离重组晶圆5或人工晶圆。在随后的处理中，密封剂50提供机械和热稳定性。将载体10除去也暴露了半导体芯片20的前侧。在不同的实施方式中，在随后的处理期间，根据密封剂50的热稳定性，重组晶圆5可以经受高达300℃的温度。
图7示出根据本发明的实施方式，在制造期间，显示前侧金属化的半导体封装的放大截面图。与图4至图6不同，图7示出单个半导体封装的放大视图。
参考图7，多个半导体芯片20可以包括前侧金属化层15，例如，可以包括第一接触区域30和第二接触区域40。前侧金属化层15在多个半导体芯片20的顶面11上形成。在各种不同的实施方式中，可以在切割晶圆之前，形成前侧金属化层15。可供选择地，在某些实施方式中，前侧金属化层15可以在这个处理阶段形成。第一接触区域30和第二接触区域40可以包括多个层。在一个实施方式中，硅化物区域可以覆盖多个半导体芯片20的半导体材料。阻挡层可以在硅化物区域上形成，然后形成金属层。在一个实施方式中，第一接触区域30和第二接触区域40可以包括铜。在另一个实施方式中，第一接触区域30和第二接触区域40可以包括铝。在各种不同的实施方式中，第一接触区域30和第二接触区域40可以包括钛、钽、钨、和其氮化物。
图8示出根据本发明的实施方式，在形成前侧再分配层期间的半导体封装的放大视图。
钝化层60可以在前侧金属化层15周围形成，并且图案化形成再分配线和接触垫。在各种不同的实施方式中，钝化层60是绝缘层。在一个或多个实施方式中，钝化层60可以包括氧化层或氧化物/氮化物层堆叠体。在其他实施方式中，钝化层60可以包括氮化硅、氧氮化硅、FTEOS、SiCOH，聚酰亚胺、光电酰亚胺(photoimide)、BCB、或其他有机聚合物、或他们的组合。可选的绝缘衬垫(liner)可以在钝化层60之上形成。在一个实施方式中，可选的绝缘衬垫可以包括氮化物层。在各种不同的实施方式中，可选的绝缘衬垫可以包括FTEOS、二氧化硅、SiCOH、或其他低k材料。利用光刻工艺，钝化层60被图案化以在多个半导体芯片20的最后金属水平(the last metal level)上使接合焊盘形成开口。
图9示出根据本发明的实施方式，在制造期间，在形成前侧再分配层后的半导体封装的放大视图。
参考图9，沉积导电衬垫70。在各种不同的实施方式中，利用沉积工艺沉积导电衬垫70，以形成包括钛、钽、钌、钨、其组合、或其氮化物、硅化物、碳化物的共形层(conformallayer)。这样的组合的例子包括TiN、TaN、和WN、以及TiW。在各种不同的实施方式中，利用化学气相沉积、等离子气相沉积或原子层沉积来沉积导电衬垫70。在各种不同的实施方式中，导电衬垫70具有大约20nm到大约200nm的厚度。导电衬垫70是扩散势垒金属，并且防止前侧金属化层15的最后金属线中铜的向外扩散，以及防止与其他金属层的混合。
如图9进一步所示，沉积导电晶种层80。导电晶种层(conductive seed layer)80覆盖导电衬垫70。在各种不同的实施方式中，利用沉积工艺沉积导电晶种层80以形成共形层。在各种不同的实施方式中，利用化学气相沉积、等离子气相沉积或原子层沉积来沉积导电晶种层80。在各种不同的实施方式中，导电晶种层80具有大约20nm到大约200nm的厚度。导电晶种层80提供在随后的电镀工艺期间用于生长的晶种层。在各种不同的实施方式中，导电晶种层80可以包括铜或其他金属(例如铝、钨、银、金、镍或钯)。
如接下来的图10所示，沉积厚的光致抗蚀层85。在各种不同的实施方式中，光致抗蚀层85是几微米厚，在一个实施方式中，其从大约1μm到大约10μm变化。在沉积后，光致抗蚀层85填充之前在钝化层60中形成的开口。将光致抗蚀层85曝光并显影。图案化的光致抗蚀层85包括用于再分配金属线和接触垫的图案。
接下来参考图11，通过在图案化的光致抗蚀层85之间暴露的导电晶种层80上电镀填充金属，从而形成前侧再分配金属线150和接触垫90。在各种不同的实施方式中，填充金属包括铜，不过在其他实施方式中，使用其他合适的导体。在一个实施方式中，导电晶种层80可以包括与随后的金属线的材料一样的材料以使得能够进行电镀。在各种不同的实施方式中，前侧再分配金属线150可以包括多个层，例如在一个实施方式中，Cu/Ni、Cu/Ni/Pd/Au、Cu/NiMoP/Pd/Au、或Cu/Sn。
图案化的光致抗蚀层85被剥离，以暴露导电晶种层80。例如，利用湿蚀刻化学法，蚀刻除去暴露的导电晶种层80和在下面的导电衬垫70(如箭头所示)。在这个阶段的结构如图11所示，并且包括接触垫90和前侧再分配金属线150。
参考图12，从后侧薄化包括形成的半导体模块100的重组晶圆5，从而暴露多个半导体芯片20。在某些实施方式中，重组晶圆5的薄化也可使多个半导体芯片变薄。在各种不同的实施方式中，利用机械工艺、化学工艺、化学机械工艺进行薄化。
在重组晶圆5的下表面上沉积电介质衬垫210。后侧绝缘层220可以沉积在电介质衬垫210上。抗蚀层240在后侧绝缘层220上结网。在一个或多个实施方式中，可以在后侧绝缘层220上在后侧绝缘层220与抗蚀层240之间沉积硬掩模层230。硬掩膜层230可以是单层或包括多层。在穿过基板开口蚀刻期间，硬掩膜层230保护多个半导体芯片20和后侧绝缘层220。硬掩膜层230可以基于穿过基板开口蚀刻工艺的选择性来选择。例如，在一个实施方式中，具有氟化学特性的高密度等离子体被用于蚀刻穿过基板的开口，以及硬掩膜层230包括SiO2硬掩膜。
将抗蚀层240曝光并图案化。利用作为掩膜的图案化抗蚀层240，蚀刻硬掩膜层230、在下面的后侧绝缘层220和电介质衬垫210以暴露多个半导体芯片20的下表面。穿过基板的开口255在密封剂50内形成，并且接触接触垫90。
如图12所示，在RF等离子体腔室中的高密度等离子体工艺可以被用于形成在密封剂50中形成穿过基板的开口255。利用基于氟的等离子体，实现蚀刻步骤。不过，基于氟的蚀刻是各向同性的，并且会导致非垂直侧壁。因此，通过将聚合物产生气体引入等离子腔室，实现沉积步骤。聚合物产生气体在构成临时蚀刻停止层的暴露侧壁上沉积聚合物层。由于碰撞离子的高能量，聚合物层不在沟道的暴露底表面上形成。沉积在沟道底表面的任何聚合物被碰撞离子的高能量破坏。在连续的蚀刻和沉积步骤中，实现穿过基板的开口工艺。因此，产生垂直的开口。例如，氟蚀刻步骤可以包括SF6蚀刻剂，而聚合物产生气体可以包括C4F8。蚀刻和沉积步骤可以被重复许多次，例如大约100次到大约500次，以形成穿过基板的开口255。在其他实施方式中，可以使用其他类型的反应离子蚀刻工艺。在蚀刻步骤后，穿过基板的开口255可以包括任何合适的垂直形状，例如圆筒形、环形、有小平面的、沟道等。在某些实施方式中，蚀刻工艺的终点可以由蚀刻期间的分析(例如，视觉的)确定，并且可以被定时。
参考图13，移走任何剩余的抗蚀层240和硬掩膜层230，从而暴露后侧绝缘层220。可选的侧壁电介质层可以沉积在穿过基板的开口255的侧壁中。在用导电填充材料填充穿过基板的开口255之前，沉积阻挡衬垫235。阻挡衬垫235是共形的，并且可以包括例如Ta、TaN、W、WN、WCN、WSi、Ti、TiN和/或Ru的单层。阻挡衬垫235可以被用作用于防止金属扩散到下面的多个半导体芯片20和/或密封剂50阻挡层。例如，可以利用RF磁控溅射沉积阻挡衬垫235。后侧晶种层245可以被可选地沉积在阻挡衬垫235上。例如，可以利用PVD溅射或金属有机物CVD(MOCVD)工艺共形沉积后侧晶种层245。
光致抗蚀层265被沉积在重组晶圆5的后侧上。在各种不同的实施方式中，光致抗蚀层265是具有几微米厚的光致抗蚀剂的厚层。利用光刻步骤，光致抗蚀层265被图案化。通过具有后侧再分配线图案的掩膜和穿过基板的开口255，执行光刻步骤。光刻步骤暴露阻挡衬垫235和可选的后侧晶种层245。
如图13所示，例如，利用电镀工艺，通过在后侧晶种层245上沉积后侧导电填充材料250，形成后侧再分配层。由此，后侧导电填充材料250被沉积在图案化的抗蚀层265之间。由此，后侧导电填充材料250被沉积在穿过基板的开口255内以及在后侧再分配线的图案上。在某些实施方式中，后侧导电填充材料250可以部分填充穿过基板的开口255。
在一个实施方式中，后侧导电填充材料250包括铜。在一个或多个实施方式中，后侧导电填充材料250包括铜、银、金、镍、锌、和/或铂。在一个不同的实施方式中，后侧导电填充材料250包括钨。如果后侧导电填充材料250包括钨，优选使用包括CVD氮化钛和硅掺杂的钨双层晶种层。类似地，在某些实施方式中，掺杂的多晶硅、银、金和/或铝可以被沉积在穿过基板的开口255内，以形成穿过基板的通孔260。剥离剩余的光致抗蚀层265，以暴露后侧晶种层245。通过湿法或干法蚀刻移走后侧晶种层245和阻挡衬垫235，从而暴露在下面的后侧绝缘层220。
在备选实施方式中，可以利用消减蚀刻工艺(subtractive etch process)沉积和图案化后侧导电填充材料250。在进一步实施方式中，例如，利用模版印刷或丝网印刷，后侧再分配层可以被直接印刷。
重组晶圆5被单片化，从而形成单独的半导体模块100。半导体模块100包括用于形成外部接触的多个接触垫90。
可以在随后的封装之前测试由此形成的半导体模块100。例如，测试探针可以被施加在接触垫90上，以便识别缺陷单元。
在某些实施方式中，由此形成的半导体模块100可以被直接使用，并且安装在电路板上。在其他实施方式中，半导体模块100可以被封装在引线框、夹子框(clip frame)和其他合适的基板上，以形成半导体封装。本发明的实施方式包括形成任何合适类型的封装，例如，兼容JEDEC标准。例子包括晶体管外形封装(outline package)、小外形封装、薄小外形封装、薄缩小小外形封装(thin shrink small outline package)、单列直插式封装、和其他封装。
参考图14，例如如图13中形成的半导体模块100被放置在引线框300上。利用小片附接层280，半导体模块100可以被附接到引线框300，在一个实施方式中，所述小片附接层280可以是绝缘的。在某些实施方式中，小片附接层280可以是导电的，例如，可以包括纳米导电性软膏。在备选实施方式中，后侧导电填充材料250可以被焊接到引线框300，以便小片附接层280是可焊接的材料。
在一个实施方式中，小片附接层280包括聚合物，例如氰化物酯或环氧树脂材料，以及可以包括银粒子。在一个实施方式中，小片附接层280可以被应用为聚合物基质中的导电粒子，以便在固化后形成复合材料。在备选实施方式中，可以应用例如银纳米软膏的导电纳米软膏(conductive nano-paste)。可供选择地，在另一个实施方式中，小片附接层280包括焊料，例如铅锡材料。在各种不同的实施方式中，包括例如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒的金属或金属合金的任何合适导电粘结材料可以被用于形成小片附接层280。
小片附接层280可以以可控的量被分配在半导体模块100下面。具有聚合物的小片附接层280可以在大约125℃到大约200℃固化，而基于焊料的小片附接层280可以在250℃到大约350℃固化。利用小片附接层280，半导体模块100被附接到引线框300的小片焊盘310。
在一个或多个实施方式中，利用配线接合工艺(wire bonding process)，用接合线330将在半导体模块100上的接触垫90耦接到引线框300。利用焊球340，接合线330可以被焊接到引线框300的引线320和接触垫90。
在一个或多个实施方式中，接合线330可以包括铝或铜。在一个或多个实施方式中，这样的铝线的厚度可以是大约10μm到大约1000μm。在另一个实施方式中，接合线330可以包括金。这样的金线的厚度可以是大约10μm到大约100μm。
在一个或多个实施方式中，高速线接合设备(high-speed wire bond equipment)可以被用于最小化形成接合线330的时间。在某些实施方式中，在配线接合工艺期间，图像识别系统可以被用于定向半导体模块100。
在各种不同的实施方式中，球焊(ball bonding)或楔焊(wedge bonding)可以被用于附接接合线330。在各种不同的实施方式中，可以利用热超声焊接(thermosonicbonding)、超声波焊接(ultrasonic bonding)或热压焊接(thermo-compression bonding)形成接合线330。热超声焊接采用温度、超声波和低冲击力以及球法/楔法(ball/wedgemethod)。超声波焊接采用超声波和低冲击力，以及仅使用楔法。热压焊接采用温度和高冲击力，以及仅使用楔法。
例如，在一种情况下，热超声焊接可以采用金线和铜线。对于每个互连，形成两个线接合，一个在半导体模块100的接触垫90，另一个在引线框300的多个引线320的引线。接合温度、超声波能量以及接合力和时间必须精密控制，以便形成半导体模块100到引线框300的可靠连接。
在一个或多个实施方式中，对于配线接合工艺中可以沉积焊剂和焊接材料。焊接材料可以被电镀，不过在其他实施方式中，可以使用其他工艺，例如无电镀，或沉积工艺，例如气相沉积。焊接材料可以是单层的，或包括具有不同成分的多层。例如，在一个实施方式中，焊接材料可以包括，在铅(Pb)层及之后的锡(Sn)层。在另一个实施方式中，可以沉积SnAg作为焊接材料。其他例子包括SnPbAg、SnPb、PbAg、PbIn、以及无铅材料，例如SnBi、SnAgCu、SnTn和SiZn。在各种不同的实施方式中，可以沉积其他的合适材料。
可以实施热处理，以形成如图14所示的焊球340。热处理回流焊接材料，以及加热形成焊球340。例如，在实施方式中，当沉积Pb/Sb层时，在回流后，形成熔化温度超过300℃的包括95Pb/5Sn(95/5)或90Pb/10Sn(95/10)的高铅合金。在一个不同实施方式中，形成溶化温度为183℃的共晶63Pb/37Sn(63/37)。类似地，可以形成成分为97.5Sn/2.6Ag(97.5/2.5)的无铅焊球340。焊球340包括均质材料并具有明确的熔化温度。例如，高熔铅/锡合金是耐材料疲劳的可靠冶金材料。在某些实施方式中，在热处理期间，接触垫90的金属还可以扩散和混杂。
参考图15，外部密封剂350被应用在半导体模块100和引线框300上。在一个或多个实施方式中，利用压缩模塑工艺，可以施加外部密封剂350。在压缩模塑中，外部密封剂350可以被放置在模塑腔中，接着，被关闭该模塑腔以压缩外部密封剂350。当模塑单个图案时，可以使用压缩模塑。在备选实施方式中，利用转移模塑工艺，可以施加外部密封剂350。在其他实施方式中，可以利用注射模塑、粒化模塑、粉末模塑或液体模塑施加外部密封剂350。可供选择地，可以利用印刷工艺(例如模板印刷或丝网印刷)施加外部密封剂350。可以执行固化工艺以形成引线封装。
图16和图17示出形成半导体封装的备选实施方式。
与在图14和图15中示出的实施方式不同，在本实施方式中，在半导体模块100与引线框300之间的互连件包括夹子370。可以利用夹子粘合层(clip adhesive layer)360(例如焊接材料或导电软膏)将夹子370附接到引线框300的引线320。如之前所述，在附接夹子370后，外部密封剂350在引线框300和半导体模块100上形成。
在进一步的备选实施方式中，可以利用电镀工艺(galvanic process)(电化学沉积)形成半导体模块100与引线框300之间的互连件。
本发明的实施方式还包括形成第一制成品，例如在各种不同的实施方式中描述的半导体模块100。第一制成品可以是不一定符合标准封装模块(例如JEDEC标准)的封装。虽然该第一制成品可以被直接卖给某些客户，但是可以在进一步引线框内封装以形成第二制成品，例如在以上各个不同的实施方式中描述的引线框封装。第二制成品可以符合标准封装，例如JEDEC标准。不过，第一制成品和第二制成品具有相似的功能和操作。例如，除了在半导体模块100中的那些器件以外，引线框封装可以不具有其它的半导体器件。
图18示出半导体封装的另一个实施方式，其示出封装内的堆叠半导体封装。
在本实施方式中，半导体模块100可以包括多个半导体芯片20的堆叠，其可以利用通孔耦接。半导体模块100沉积在引线框300上，并且被封装以形成标准的引线框封装。
虽然已经参考示例性实施方式对本发明进行了描述，但是这个说明书不应被解释为具有限制意义。在参考该说明书后，示例性实施方式的各种修改和组合以及本发明的其他实施方式对于本领域的技术人员来说将是显而易见的。作为示例，在图1至图17中描述的实施方式可以彼此组合。因此，权利要求包括任何这样的修改或实施方式。
虽然已经详细描述了本发明及其优势，但是应当理解，在没有偏离本发明权利要求限定的精神和范围的情况下，可以进行各种改变、替换和变更。例如，本领域的技术人员很容易理解，在本发明的范围内，可以改变本文所述的许多特征、功能、工艺和材料。
而且，本发明的范围不限于在本说明书中描述的工艺、机器、制造、物质成分、手段、方法和步骤的特定实施方式。通过本发明的公开，本领域的普通技术人员应当明白，可以根据本发明采用执行本文所述相应实施方式的相同功能或获得基本相同结果的现有或将来开发的工艺、机器、制造、物质成分、手段、方法或步骤。因此，权利要求包括这样的工艺、机器、制造、物质成分、手段、方法或步骤。

Claims (22)

1.一种半导体器件，包括：
引线框，具有多个引线和小片焊盘；
被附接到所述引线框的所述小片焊盘的半导体模块，所述半导体模块包括被配置在第一密封剂中的第一半导体芯片和第二半导体芯片，所述第一半导体芯片和所述第二半导体芯片并排配置，所述半导体模块具有耦接到所述第一半导体芯片的多个接触垫；
多个互连件，将所述多个接触垫与所述多个引线耦接；以及
第二密封剂，被配置在所述半导体模块和所述引线框上。
2.根据权利要求1所述的器件，其中，所述第一半导体芯片通过被配置在靠近所述半导体模块的第一侧的前侧再分配线耦接到所述第二半导体芯片。
3.根据权利要求2所述的器件，其中，所述第一半导体芯片进一步通过被配置在靠近所述半导体模块的第二侧的后侧再分配线耦接到所述第二半导体芯片。
4.根据权利要求1所述的器件，其中，所述多个引线的总数不同于所述半导体模块的所述多个接触垫的总数。
5.根据权利要求1所述的器件，其中，所述多个引线利用配线接合或引线接合来耦接到所述多个接触垫。
6.根据权利要求1所述的器件，其中，所述多个引线利用夹子接合来耦接到所述多个接触垫。
7.一种半导体器件，包括：
引线框，具有多个引线和小片焊盘；
被配置在所述引线框的所述小片焊盘上的半导体模块，所述半导体模块包括并排配置的第一半导体芯片和第二半导体芯片，所述半导体模块具有耦接到所述第一半导体芯片的多个接触垫，其中，所述半导体模块是嵌入式晶圆级封装；以及
密封剂，被配置在所述半导体模块和所述引线框上。
8.根据权利要求7所述的器件，其中，所述第一半导体芯片通过被配置在靠近所述半导体模块的第一侧的前侧再分配线耦接到所述第二半导体芯片。
9.根据权利要求8所述的器件，其中，所述第一半导体芯片进一步通过被配置在靠近所述半导体模块的第二侧的后侧再分配线耦接到所述第二半导体芯片。
10.根据权利要求7所述的器件，其中，所述第一半导体芯片是分立式功率晶体管。
11.根据权利要求7所述的器件，其中，所述多个接触垫包括源极接触垫、漏极接触垫以及控制接触垫。
12.根据权利要求11所述的器件，其中，所述源极接触垫耦接到所述第一半导体芯片的第一侧，以及其中，所述漏极接触垫耦接到所述第一半导体芯片的相反的第二侧。
13.根据权利要求7所述的器件，其中，所述多个引线的布置独立于所述第一半导体芯片上的所述多个接触垫的布置。
14.根据权利要求7所述的器件，其中，所述多个引线的总数不同于所述半导体模块的所述多个接触垫的总数。
15.根据权利要求7所述的器件，其中，所述多个引线利用配线接合或引线接合来耦接到所述多个接触垫。
16.根据权利要求7所述的器件，其中，所述多个引线利用夹子接合来耦接到所述多个接触垫。
17.一种形成半导体器件的方法，所述方法包括：
提供具有多个引线和小片焊盘的引线框；
提供包括被配置在第一密封剂中的第一半导体芯片和第二半导体芯片的半导体模块，所述第一半导体芯片和所述第二半导体芯片并排配置，所述半导体模块具有耦接到所述第一半导体芯片的多个接触垫；
将所述半导体模块附接到所述引线框的所述小片焊盘；
将所述多个接触垫与所述多个引线电耦接；以及
利用第二密封剂将所述半导体模块和所述引线框密封。
18.根据权利要求17所述的方法，其中，所述电耦接使用配线接合工艺。
19.根据权利要求17所述的方法，其中，所述电耦接使用夹子接合工艺。
20.根据权利要求17所述的方法，其中，所述电耦接使用电镀工艺。
21.根据权利要求17所述的方法，其中，所述半导体模块进一步包括将所述第一半导体芯片耦接到所述第二半导体芯片的前侧再分配线。
22.根据权利要求17所述的方法，其中，所述半导体模块进一步包括将所述第一半导体芯片耦接到所述第二半导体芯片的后侧再分配线，以及其中，所述后侧再分配线被配置在所述半导体模块的前侧再分配线的相反侧。
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