SCR1 is a high-quality open-source RISC-V MCU core in Verilog

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

A Single Cycle Risc-V 32 bit CPU

RISCV CPU implementation in SystemVerilog

A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.

A pipelined, in-order implementation of the RV32I ISA

A repository consisting of all the project files and codes for RISC-V Processor design using Transaction Level Verilog.

Minimalistic RV32I RISC-V Processor in System Verilog

This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

This is a Single Cycle processor running the RV32I implementation, hence a 32-bit CPU, written in SystemVerilog.

Basic RV32I RISC-V CPU Implementation

This is an RV32_IM riscv cpu core. Its a non-pipelined core with MULW instruction alone from M extension.

Processor Design of RV32I Single Cycle CPU

Processor Design of RV32I 5-Stage Pipelined CPU