fpga-soc

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Here are 177 public repositories matching this topic...

lnis-uofu / OpenFPGA

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An Open-source FPGA IP Generator

fpga fpga-soc

Updated Nov 21, 2024
Verilog

trivialmips / nontrivial-mips

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NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.

cpu fpga mips xilinx fpga-soc-linux systemverilog fpga-soc

Updated Jul 7, 2020
SystemVerilog

JunningWu / Learning-NVDLA-Notes

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NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning.wu@ia.ac.cn

deep-learning linux-kernel verilog fpga-soc nerual-network

Updated Dec 18, 2018

timvideos / HDMI2USB-litex-firmware

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A version of the HDMI2USB firmware based around LiteX tools produced by @enjoy-digital (based on misoc+migen created by @m-labs)

video fpga usb hardware verilog webcam hdmi fpga-soc uvc fpga-firmware video-capture hdmi2usb numato-opsis digilent-atlys

Updated Jan 30, 2020
Python

dpretet / axi-crossbar

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An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated Nov 21, 2024
SystemVerilog

ZipCPU / openarty

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An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

Updated Jan 17, 2024
Verilog

azonenberg / antikernel

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The Antikernel operating system project

fpga operating-system research-project security-hardening fpga-soc system-on-chip

Updated Apr 23, 2020
Verilog

esa-tu-darmstadt / tapasco

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The Task Parallel System Composer (TaPaSCo)

fpga hardware hardware-acceleration fpga-soc

Updated Oct 28, 2024
Verilog

ultraembedded / riscv_soc

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Basic RISC-V Test SoC

linux verilog fpga-soc-linux systemc fpga-soc risc-v system-on-chip riscv-linux

Updated Apr 7, 2019
Verilog

trivialmips / TrivialMIPS

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MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support

cpu fpga mips xilinx systemverilog fpga-soc

Updated Apr 29, 2019
SystemVerilog

strath-sdr / rfsoc_qpsk

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PYNQ example of using the RFSoC as a QPSK transceiver.

sdr pynq pynq-hardware-overlay fpga-soc qpsk voila voila-dashboard

Updated May 24, 2023
VHDL

splinedrive / lets_build_a_compiler_for_riscv

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A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw

c computer-science tutorial compiler spike riscv fpga-soc compiler-construction riscv32 riscv-sim riscv-asm crenshaw riscv-assembly

Updated Sep 26, 2022
C

tommythorn / yarvi

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Yet Another RISC-V Implementation

fpga riscv verilog fpga-soc risc-v riscv32

Updated Sep 21, 2024
Roff

michaelehab / AES-Verilog

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Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL

security cryptography encryption fpga aes rtl aes-256 aes-128 aes-192 verilog learn aes-encryption fpga-soc verilog-hdl encryption-decryption fpga-board aes-decryption verilog-project

Updated Jul 31, 2022
Verilog

jingpu / Halide-HLS

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HLS branch of Halide

fpga hls dsl image-processing halide fpga-soc

Updated Jul 6, 2018
C++

Obijuan / Z80-FPGA

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Z80 CPU for OpenFPGAs, with Icestudio

fpga z80 icestudio fpga-soc ice40

Updated Jun 6, 2024
Assembly

strath-sdr / rfsoc_sam

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RFSoC Spectrum Analyser Module on PYNQ.

sdr fft pynq pynq-hardware-overlay fpga-soc spectrum-analyser voila voila-dashboard

Updated Jun 26, 2024
VHDL

micro-FPGA / engine-V

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SoftCPU/SoC engine-V

fpga fpga-soc risc-v riscvcontest

Updated Jun 5, 2023
Verilog

ryuz / jelly

Sponsor

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Original FPGA platform

fpga zynq verilog fpga-soc embedded-rust zynqmp

Updated Nov 14, 2024
Verilog

tommythorn / fpgammix

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Partial implementation of Knuth's MMIX processor (FPGA softcore)

fpga mmix fpga-soc knuth-mmix-processor fpga-softcore

Updated Feb 19, 2020
C

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fpga-soc

Here are 177 public repositories matching this topic...

lnis-uofu / OpenFPGA

trivialmips / nontrivial-mips

JunningWu / Learning-NVDLA-Notes

timvideos / HDMI2USB-litex-firmware

dpretet / axi-crossbar

ZipCPU / openarty

azonenberg / antikernel

esa-tu-darmstadt / tapasco

ultraembedded / riscv_soc

trivialmips / TrivialMIPS

strath-sdr / rfsoc_qpsk

splinedrive / lets_build_a_compiler_for_riscv

tommythorn / yarvi

michaelehab / AES-Verilog

jingpu / Halide-HLS

Obijuan / Z80-FPGA

strath-sdr / rfsoc_sam

micro-FPGA / engine-V

ryuz / jelly

tommythorn / fpgammix

Improve this page

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