VHDL course at Brno University of Technology

Example of how to get started with olofk/fusesoc.

Hardware-side component of Hastlayer for Xilinx FPGAs. See https://hastlayer.com for details.

(Your Own Digital Accelerator) A Smoothing filter by using a Finite Impulse Response (FIR) and a Low Pass Filter (LPF) algorithm. The hardware used is a NEXYS A7 Field Programmable Gate Array (FPGA) programmedin Verilog.

An FPGA-based image acquisition and display system, referred to as FIADS.

Pipelined a real-time edge detection system with a OV7670 camera and Nexys A7 100T FPGA Trainer Board

This accelerator uses a Nexys A7 100T FPGA to overlay an one image over another using an image mask and performing masking operations, with the results being displayed over VGA. The purpose of this project was to utilize the parallel nature of FPGAs to create a hardware accelerator for image masking applications.

Nexys A7 drivers for RISC-V

A collection of code from CDA 4240C: Design of Digital System and Lab

A digital locker made for Nexys A7 using Xilinx Vivado and VHSIC Hardware Description Language

T20 Cricket Game using Verilog coding. Includes a constraint file for implementing on Nexys A7 FPGA board.

Digital Electronics 1 course at Brno University of Technology

This is me playing around with my Nexys A7 and learning verilog. This is the Vivado project directory.

A parallel implementation of an Image Steganography Decode in simulation on a Nexys-A7 FPGA. The decoder expects images encoded with the least significant bit decoder.

Project for the Digilent Nexus A7 development board (Xilinx/AMD Artix-7)

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Team project in BPC-DE1 course on FEEC BUT

A WIP RISC-V CPU implementation. Right now I'm working on implementing RV32I.