32-bit Superscalar RISC-V CPU

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

USB2Sniffer: High Speed USB 2.0 capture (for LambdaConcept USB2Sniffer hardware)

Over-engineered SDR development board

Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-IV board.

A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.

FPGA Camera Parallel & MIPI Verilog

HDU Computer Organization Course Design Beginner Guide - 杭电计组课设新手指南

Library to convert a FASM file into BELs importable into Vivado.

My experiments with Nexys4 DDR Artix-7 FPGA Board

Selected projects from "Applied Digital Logic Exercises using FPGAs", by Kurt Wick.

基于蜂鸟E203的魔改

A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)

Created project using a PCIe root-complex and endpoint on a Xilinx Artix-7.

A simple and scaleable Self Organizing Map implementation written in VHDL. Tested on ARTYA7-35T board.

GRLIB GPL support for Digilent CMOD A7 35T board

Alchitry Au FPGA Board Example Project

This repository contains the Xilinx Vivado project for the Artix-7 (XC7A35T-1FTG256C) FPGA on Virtex.

A tetris-game on screen using verilog.

Here we are implementing Risc-V single cycle microprocessor on Basys3 (Artix-7) .We are testing with Fibonaccie Series and showing on 7 segment display..