NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
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Jul 7, 2020 - SystemVerilog
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fpga-soc
Here are 14 public repositories matching this topic...
RISCV CPU implementation in SystemVerilog
asic
fpga
assembler
riscv
verilog
systemverilog
fpga-soc
risc-v
rv32i
crossbar
axi4
axi4-protocol
asic-design
riscv-cpu
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Oct 8, 2024 - SystemVerilog
ARM single cycle processor on nandland.com go-board
arm
embedded
fpga
assembly
assembler
systemverilog
hdl
fpga-soc
system-architecture
ice40
system-design
fpga-programming
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Oct 23, 2023 - SystemVerilog
An implementation of the RISC stack ISA spec from ISA-docs
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Dec 28, 2023 - SystemVerilog
Designed and implemented a 3x3 Rubik's Cube Simulator on an FPGA and associated NIOS-II Microcontroller as a System-on-Chip. Skills Employed: SystemVerilog, FPGA development, NIOS-II, SoC, USB Protocol.
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Mar 24, 2023 - SystemVerilog
It's a cryptoprocessor that implements de RC4 algorithm
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Jun 3, 2017 - SystemVerilog
I2C Interface RTL description
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May 30, 2019 - SystemVerilog
SPI Interface RTL Description
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May 21, 2019 - SystemVerilog
I made a motion controlled digital synthesizer known as a puppeteer theremin that uses AI to get motion control data from a server hosted on a phone onto an FPGA.
python
ai
fpga
embedded-systems
tesseract-ocr
systemverilog
fpga-soc
audio-processing
pytesseract
ece385
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Dec 15, 2022 - SystemVerilog
Laboratory work project
embedded
fpga
audio-player
audio-codec
hobby-project
fpga-soc
systemverilog-hdl
laboratory-exercises
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May 23, 2019 - SystemVerilog
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