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Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling

Authors:

Radu MarculescuAuthors Info & Claims

ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 21, Issue 3

Article No.: 52, Pages 1 - 38

https://doi.org/10.1145/2870633

Published: 11 May 2016 Publication History

Abstract

In this survey, we review several approaches for predicting performance of Network-on-Chip (NoC)-based multicore systems, starting from the traffic models to the complex NoC models for latency evaluation. We first review typical traffic models to represent the application workloads in NoC. Specifically, we review Markovian and non-Markovian (e.g., self-similar or long-range memory-dependent) traffic models and discuss their applications on multicore platform design. Then, we review the analytical techniques to predict NoC performance under given input traffic. We investigate analytical models for average as well as maximum delay evaluation. We also review the developments and design challenges of NoC simulators. One interesting research direction in NoC performance evaluation consists of combining simulation and analytical models in order to exploit their advantages together. Toward this end, we discuss several newly proposed approaches that use hardware-based or learning-based techniques. Finally, we summarize several open problems and our perspective to address these challenges.

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Narayana SMandal SAyoub RIslam MKishinevsky MOgras U(2023)Fast Analysis Using Finite Queuing Model for Multilayer NoCsIEEE Design & Test10.1109/MDAT.2023.331016740:6(112-124)Online publication date: Dec-2023
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Index Terms

Performance Evaluation of NoC-Based Multicore Systems: From Traffic Analysis to NoC Latency Modeling
1. General and reference
  1. Document types
    1. Surveys and overviews
2. Networks
  1. Network types
    1. Network on chip

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Published In

cover image ACM Transactions on Design Automation of Electronic Systems

ACM Transactions on Design Automation of Electronic Systems Volume 21, Issue 3

Special Section on New Physical Design Techniques for the Next Generation Integration Technology and Regular Papers

July 2016

434 pages

ISSN:1084-4309

EISSN:1557-7309

DOI:10.1145/2926747

Editor:
Naehyuck Chang
Korea Advanced Institute of Science and Technology, Korea

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Copyright © 2016 ACM.

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ACM Journals for the Design of Smart and Connected Systems

Publication History

Published: 11 May 2016

Accepted: 01 December 2015

Revised: 01 October 2015

Received: 01 June 2015

Published in TODAES Volume 21, Issue 3

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Cited By

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https://doi.org/10.1109/TCSII.2023.3258700
Narayana SMandal SAyoub RIslam MKishinevsky MOgras U(2023)Fast Analysis Using Finite Queuing Model for Multilayer NoCsIEEE Design & Test10.1109/MDAT.2023.331016740:6(112-124)Online publication date: Dec-2023
https://doi.org/10.1109/MDAT.2023.3310167
Kullu PYigit-Sert SOzkan-Okay MAr Y(2023)An Artificial Bee Colony Based Mapping Method for Three Dimensional Network-on-Chip2023 International Conference on Emerging Trends in Networks and Computer Communications (ETNCC)10.1109/ETNCC59188.2023.10284966(1-6)Online publication date: 16-Aug-2023
https://doi.org/10.1109/ETNCC59188.2023.10284966
Li YZhou P(2023)Fast NoC Router Latency Estimation Using Machine Learning2023 China Semiconductor Technology International Conference (CSTIC)10.1109/CSTIC58779.2023.10219215(1-3)Online publication date: 26-Jun-2023
https://doi.org/10.1109/CSTIC58779.2023.10219215
Chaurasia ASharma VChowdhary CBasheer SGadekallu T(2023)Non-Gaussian Traffic Modeling for Multicore Architecture Using Wavelet Based Rosenblatt ProcessIEEE Access10.1109/ACCESS.2023.326557211(38523-38533)Online publication date: 2023
https://doi.org/10.1109/ACCESS.2023.3265572
Matoussi O(2021)NoC Performance Model for Efficient Network Latency Estimation2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE51398.2021.9474101(994-999)Online publication date: 1-Feb-2021
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Nalci YKullu PTosun SOzturk O(2021)ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCsThe Journal of Supercomputing10.1007/s11227-020-03365-077:3(2667-2680)Online publication date: 1-Mar-2021
https://dl.acm.org/doi/10.1007/s11227-020-03365-0
Zhezlov KPutrya FBelyaev A(2020)Analysis of Performance Bottlenecks in SoC Interconnect Subsystems2020 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (EIConRus)10.1109/EIConRus49466.2020.9039237(1911-1914)Online publication date: Jan-2020
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Vijaya Bhaskar AVenkatesh T(2020)Performance analysis of network-on-chip in many-core processorsJournal of Parallel and Distributed Computing10.1016/j.jpdc.2020.09.013Online publication date: Sep-2020
https://doi.org/10.1016/j.jpdc.2020.09.013
Fang JLiu SLiu SCheng YYu L(2018)Hybrid Network-on-ChipComplexity10.1155/2018/10408692018Online publication date: 30-Jul-2018
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