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The Superscalar Architecture of the MC68060

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Daniel ChowAuthors Info & Claims

IEEE Micro, Volume 15, Issue 2

Pages 10 - 21

https://doi.org/10.1109/40.372345

Published: 01 April 1995 Publication History

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Abstract

Motorola's MC68060 microprocessor is the newest member of the 68000 microprocessor family, its cost-effective and power-thrifty solution for high performanceembedded processing applications. This article focuses on the MC68060 microarchitecture features, such as its superscalar pipeline implementation, that enable it to achieve its high performance objectives while maintaining 68000 user code compatibility. The first MC68060 implementations, supplied at 50 MHz and 66 MHz, are 3.3V parts that achieve 103 dhrystone mips performance (66MHz).

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Cited By

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Malik AMoyer BZhou RBhattacharyya SMudge TWolf WJerraya A(2002)Embedded cache architecture with programmable write buffer support for power and performance flexibilityProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581646(98-107)Online publication date: 8-Oct-2002
https://dl.acm.org/doi/10.1145/581630.581646
Pan HAsanović KGao GMudge TPalem K(2001)Heads and tailsProceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/502217.502244(168-175)Online publication date: 16-Nov-2001
https://dl.acm.org/doi/10.1145/502217.502244
Malik AMoyer BCermak DThe C(2000)A programmable unified cache architecture for embedded applicationsProceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/354880.354903(165-171)Online publication date: 1-Nov-2000
https://dl.acm.org/doi/10.1145/354880.354903
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Published In

IEEE Micro Volume 15, Issue 2

April 1995

83 pages

ISSN:0272-1732

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IEEE Computer Society Press

Washington, DC, United States

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Published: 01 April 1995

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Malik AMoyer BZhou RBhattacharyya SMudge TWolf WJerraya A(2002)Embedded cache architecture with programmable write buffer support for power and performance flexibilityProceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/581630.581646(98-107)Online publication date: 8-Oct-2002
https://dl.acm.org/doi/10.1145/581630.581646
Pan HAsanović KGao GMudge TPalem K(2001)Heads and tailsProceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/502217.502244(168-175)Online publication date: 16-Nov-2001
https://dl.acm.org/doi/10.1145/502217.502244
Malik AMoyer BCermak DThe C(2000)A programmable unified cache architecture for embedded applicationsProceedings of the 2000 international conference on Compilers, architecture, and synthesis for embedded systems10.1145/354880.354903(165-171)Online publication date: 1-Nov-2000
https://dl.acm.org/doi/10.1145/354880.354903
Malik AMoyer BCermak D(2000)A low power unified cache architecture providing power and performance flexibility (poster session)Proceedings of the 2000 international symposium on Low power electronics and design10.1145/344166.344610(241-243)Online publication date: 1-Aug-2000
https://dl.acm.org/doi/10.1145/344166.344610
Sima D(1997)Superscalar Instruction IssueIEEE Micro10.1109/40.62121117:5(28-39)Online publication date: 1-Sep-1997
https://dl.acm.org/doi/10.1109/40.621211
Merchant AMelamed BSchenfeld ESengupta B(1996)Analysis of a Control Mechanism for a Variable Speed ProcessorIEEE Transactions on Computers10.1109/12.50831845:7(793-801)Online publication date: 1-Jul-1996
https://dl.acm.org/doi/10.1109/12.508318

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Execution cache-based microarchitecture power-efficient superscalar processors

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