Parallel Cycle Based Logic Simulation Using Graphics Processing Units

Graphics Processing Units (GPUs) are gaining popularity for parallelization of general purpose applications. GPUs are massively parallel processors with huge performance in a small and readily available package. At the same time, the emergence of general purpose programming environments for GPUs such as CUDA shorten the learning curve of GPU programming. We present a GPU-based parallelization of logic simulation algorithm for electronic designs. Logic simulation is a crucial component of verification of electronic designs that allows one to check whether the design behaves according to the specifications. Verification of electronic designs consumes more than 60% of the overall design cycle. Any attempts to speedup the verification process (and logic simulation) results in great savings and shorter time-to-market. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations and exploits the massively parallel GPU architecture. We demonstrate several orders of speedups on benchmarks using our system.