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Opportunities for RTL and gate level simulation using GPUs

Authors:

Brucek KhailanyAuthors Info & Claims

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Article No.: 166, Pages 1 - 5

https://doi.org/10.1145/3400302.3415773

Published: 17 December 2020 Publication History

Abstract

This paper summarizes the opportunities in accelerating simulation on parallel processing hardware platforms such as GPUs. First, we give a summary of prior art. Then, we propose the idea that coding frameworks usually used for popular machine learning (ML) topics, such as PyTorch/DGL.ai, can also be used for exploring simulation purposes. We demo a crude oblivious two-value cycle gate-level simulator using the higher level ML framework APIs that exhibits >20X speedup, despite its simplistic construction. Next, we summarize recent advances in GPU features that may provide additional opportunities to further state-of-the-art results. Finally, we conclude and touch upon some potential areas for furthering research into the topic of GPU accelerated simulation.

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Cited By

Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
Lin DOgras UMiguel JHuang T(2024)TaroRTL: Accelerating RTL Simulation Using Coroutine-Based Heterogeneous Task Graph SchedulingEuro-Par 2024: Parallel Processing10.1007/978-3-031-69583-4_11(151-166)Online publication date: 26-Aug-2024
https://doi.org/10.1007/978-3-031-69583-4_11
Wang HBeamer SAamodt TJerger NSwift M(2023)RepCut: Superlinear Parallel RTL Simulation with Replication-Aided PartitioningProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582034(572-585)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582034
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Published In

cover image ACM Conferences

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

November 2020

1396 pages

ISBN:9781450380263

DOI:10.1145/3400302

General Chair:
Yuan Xie
Univ. of California, Santa Barbara, CA

Copyright © 2020 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected].

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SIGDA: ACM Special Interest Group on Design Automation

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New York, NY, United States

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Published: 17 December 2020

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ICCAD '20: IEEE/ACM International Conference on Computer-Aided Design

November 2 - 5, 2020

Virtual Event, USA

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Cited By

Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
Lin DOgras UMiguel JHuang T(2024)TaroRTL: Accelerating RTL Simulation Using Coroutine-Based Heterogeneous Task Graph SchedulingEuro-Par 2024: Parallel Processing10.1007/978-3-031-69583-4_11(151-166)Online publication date: 26-Aug-2024
https://doi.org/10.1007/978-3-031-69583-4_11
Wang HBeamer SAamodt TJerger NSwift M(2023)RepCut: Superlinear Parallel RTL Simulation with Replication-Aided PartitioningProceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 310.1145/3582016.3582034(572-585)Online publication date: 25-Mar-2023
https://dl.acm.org/doi/10.1145/3582016.3582034
Dzaka ELin DHuang T(2023)Parallel And-Inverter Graph Simulation Using a Task-graph Computing System2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)10.1109/IPDPSW59300.2023.00150(923-929)Online publication date: May-2023
https://doi.org/10.1109/IPDPSW59300.2023.00150
Gavier IRussell JPatel DRietman ESiegelmann H(2023)Neural Network Compiler for Parallel High-Throughput Simulation of Digital Circuits2023 IEEE International Parallel and Distributed Processing Symposium (IPDPS)10.1109/IPDPS54959.2023.00067(613-623)Online publication date: May-2023
https://doi.org/10.1109/IPDPS54959.2023.00067
Guo ZZhang ZJiang XLi WLin YWang RHuang R(2023)General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247907(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247907
Emil DHamdy MNagib G(2023)Development an efficient AXI-interconnect unit between set of customized peripheral devices and an implemented dual-core RISC-V processorThe Journal of Supercomputing10.1007/s11227-023-05304-179:15(17000-17019)Online publication date: 5-May-2023
https://doi.org/10.1007/s11227-023-05304-1
Chhabria VKeller BZhang YVollala SPratty SRen HKhailany BFranzon PKahng ALi HLi B(2022)XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine LearningProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3551901.3556483(63-69)Online publication date: 12-Sep-2022
https://dl.acm.org/doi/10.1145/3551901.3556483
Huang GHu JHe YLiu JMa MShen ZWu JXu YZhang HZhong KNing XMa YYang HYu BYang HWang Y(2021)Machine Learning for Electronic Design Automation: A SurveyACM Transactions on Design Automation of Electronic Systems10.1145/345117926:5(1-46)Online publication date: 5-Jun-2021
https://dl.acm.org/doi/10.1145/3451179

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