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GATSPI: GPU accelerated gate-level simulation for power improvement

Authors:

Akshay Sridharan,

Brucek KhailanyAuthors Info & Claims

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

Pages 1231 - 1236

https://doi.org/10.1145/3489517.3530601

Published: 23 August 2022 Publication History

Abstract

In this paper, we present GATSPI, a novel GPU accelerated logic gate simulator that enables ultra-fast power estimation for industry-sized ASIC designs with millions of gates. GATSPI is written in PyTorch with custom CUDA kernels for ease of coding and maintainability. It achieves simulation kernel speedup of up to 1668X on a single-GPU system and up to 7412X on a multiple-GPU system when compared to a commercial gate-level simulator running on a single CPU core. GATSPI supports a range of simple to complex cell types from an industry standard cell library and SDF conditional delay statements without requiring prior calibration runs and produces industry-standard SAIF files from delay-aware gate-level simulation. Finally, we deploy GATSPI in a glitch-optimization flow, achieving a 1.4% power saving with a 449X speedup in turnaround time compared to a similar flow using a commercial simulator.

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Cited By

Basharkhah KNavabi Z(2024)Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00131(684-688)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00131
Fengler PNassif SSchlichtmann U(2024)Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528771(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528771
Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
Show More Cited By

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cover image ACM Conferences

DAC '22: Proceedings of the 59th ACM/IEEE Design Automation Conference

July 2022

1462 pages

ISBN:9781450391429

DOI:10.1145/3489517

General Chair:
Rob Oshana
NXP

Copyright © 2022 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 23 August 2022

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DAC '22: 59th ACM/IEEE Design Automation Conference

July 10 - 14, 2022

California, San Francisco

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Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

Basharkhah KNavabi Z(2024)Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)10.1109/ISVLSI61997.2024.00131(684-688)Online publication date: 1-Jul-2024
https://doi.org/10.1109/ISVLSI61997.2024.00131
Fengler PNassif SSchlichtmann U(2024)Toward Early Stage Dynamic Power Estimation: Exploring Alternative Machine Learning Methods and Simulation Schemes2024 25th International Symposium on Quality Electronic Design (ISQED)10.1109/ISQED60706.2024.10528771(1-8)Online publication date: 3-Apr-2024
https://doi.org/10.1109/ISQED60706.2024.10528771
Tian XYue CPi YLi TQu W(2024)CPGPUSim: A Multi-dimensional Parallel Acceleration Framework for RTL Simulation2024 2nd International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA62518.2024.10618075(272-277)Online publication date: 10-May-2024
https://doi.org/10.1109/ISEDA62518.2024.10618075
He ZYu B(2023)Invited Paper: Heterogeneous Acceleration for Design Rule Checking2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD)10.1109/ICCAD57390.2023.10323957(1-7)Online publication date: 28-Oct-2023
https://doi.org/10.1109/ICCAD57390.2023.10323957
Guo ZZhang ZJiang XLi WLin YWang RHuang R(2023)General-Purpose Gate-Level Simulation with Partition-Agnostic Parallelism2023 60th ACM/IEEE Design Automation Conference (DAC)10.1109/DAC56929.2023.10247907(1-6)Online publication date: 9-Jul-2023
https://doi.org/10.1109/DAC56929.2023.10247907
Chhabria VKeller BZhang YVollala SPratty SRen HKhailany BFranzon PKahng ALi HLi B(2022)XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine LearningProceedings of the 2022 ACM/IEEE Workshop on Machine Learning for CAD10.1145/3551901.3556483(63-69)Online publication date: 12-Sep-2022
https://dl.acm.org/doi/10.1145/3551901.3556483
Lin DRen HZhang YKhailany BHuang T(2022)From RTL to CUDA: A GPU Acceleration Flow for RTL Simulation with Batch StimulusProceedings of the 51st International Conference on Parallel Processing10.1145/3545008.3545091(1-12)Online publication date: 29-Aug-2022
https://dl.acm.org/doi/10.1145/3545008.3545091
Ren HNath SZhang YChen HLiu MMitra TYoung EXiong J(2022)Why are Graph Neural Networks Effective for EDA Problems?Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design10.1145/3508352.3561093(1-8)Online publication date: 30-Oct-2022
https://dl.acm.org/doi/10.1145/3508352.3561093
Chhabria VKeller BZhang YVollala SPratty SRen HKhailany B(2022)XT-PRAGGMA: Crosstalk Pessimism Reduction Achieved with GPU Gate-level Simulations and Machine Learning2022 ACM/IEEE 4th Workshop on Machine Learning for CAD (MLCAD)10.1109/MLCAD55463.2022.9900084(63-69)Online publication date: 12-Sep-2022
https://doi.org/10.1109/MLCAD55463.2022.9900084

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