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On the use of GP-GPUs for accelerating compute-intensive EDA applications

Published: 18 March 2013 Publication History

Abstract

General purpose graphics processing units (GP-GPUs) have recently been explored as a new computing paradigm for accelerating compute-intensive EDA applications. Such massively parallel architectures have been applied in accelerating the simulation of digital designs during several phases of their development -- corresponding to different abstraction levels, specifically: (i) gate-level netlist descriptions, (ii) register-transfer level and (iii) transaction-level descriptions. This embedded tutorial presents a comprehensive analysis of the best results obtained by adopting GP-GPUs in all these EDA applications.

References

[1]
W. Ecker, V. Esen, L. Schonberg, T. Steininger, M. Velten, and M. Hull, "Impact of description language, abstraction layer, and value representation on simulation performance," in Proc. of ACM/IEEE DATE, 2007, pp. 767--772.
[2]
R. Bryant, D. Beatty, K. Brace, K. Cho, and T. Sheffler, "COSMOS: a compiled simulator for MOS circuits," in Proc. ACM/IEEE DAC, 1987, pp. 9--16.
[3]
Z. Barzilai, J. Carter, B. Rosen, and J. Rutledge, "HSS--a high-speed simulator," IEEE Trans. on CAD, vol. 6, no. 4, pp. 601--617, 1987.
[4]
D. Lewis, "A hierarchical compiled code event-driven logic simulator," IEEE Trans. on CAD, vol. 10, no. 6, pp. 726--737, 1991.
[5]
W. Baker, A. Mahmood, and B. Carlson, "Parallel event-driven logic simulation algorithms: tutorial and comparative evaluation," IEEE Journal on Circuits, Devices and Systems, vol. 143, no. 4, pp. 177--185, 1996.
[6]
Y. Matsumoto and K. Taki, "Parallel logic simulation on a distributed memory machine," in Proc. IEEE EDAC, 1992, pp. 76--80.
[7]
N. Manjikian and W. Loucks, "High performance parallel logic simulations on a network of workstations," in Proc. of ACM PADS, 1993, pp. 76--84.
[8]
H. K. Kim and S. M. Chung, "Parallel logic simulation using time warp on shared-memory multiprocessors," in Proc. IEEE International Symposium on Parallel Processing, 1994, pp. 942--948.
[9]
SystemC 2.3.0, Accellera Systems Initiative, 2012, http://www.systemc.org.
[10]
S. A. Sharad and S. K. Shukla, Optimizing system models for simulation efficiency. Norwell, MA, USA: Kluwer Academic Publishers, 2004, pp. 317--330.
[11]
D. R. Cox, "RITSim: distributed SystemC simulation," Ph.D. dissertation, Rochester Institute of Technology, 2005. {Online}. Available: http://hdl.handle.net/1850/1014
[12]
Y. N. Naguib and R. S. Guindi, "Speeding up SystemC simulation through process splitting," in Proc. of ACM/IEEE DATE, 2007, pp. 111--116.
[13]
R. Buchmann and A. Greiner, "A fully static scheduling approach for fast cycle accurate systemc simulation of mpsocs," in Proc. of IEEE Microelectronics, 2007, pp. 101--104.
[14]
P. Combes, E. Caron, F. Desprez, B. Chopard, and J. Zory, "Relaxing synchronization in a parallel systemc kernel," in Proc. of IEEE ISPA, 2008, pp. 180--187.
[15]
C. Schumacher, R. Leupers, D. Petras, and A. Hoffmann, "parSC: synchronous parallel SystemC simulation on multi-core host architectures," in Proc. of ACM/IEEE CODES+ISSS, 2010, pp. 241--246.
[16]
P. Ezudheen, P. Chandran, J. Chandra, B. P. Simon, and D. Ravi, "Parallelizing SystemC kernel for fast hardware simulation on SMP machines," in Proc. of ACM/IEEE PADS, 2009, pp. 80--87.
[17]
A. Mello, I. Maia, A. Greiner, and F. Pecheux, "Parallel simulation of SystemC TLM 2.0 compliant MPSoC on SMP workstations," in Proc. of ACM/IEEE DATE, 2010, pp. 606--609.
[18]
S. Jones, "Optimistic parallelisation of SystemC," Universite Joseph Fourier: MoSiG DEMIPS, Tech. Rep., 2011.
[19]
D. Chatterjee, A. DeOrio, and V. Bertacco, "Event-driven gate-level simulation with GP-GPUs," in Proc. ACM/IEEE DAC, 2009, pp. 557--562.
[20]
D. Chatterjee, A. DeOrio, and V. Bertacco, "GCS: High-performance gate-level simulation with GP-GPUs," in Proc. ACM/IEEE DATE, 2009, pp. 1332--1337.
[21]
D. Chatterjee, A. DeOrio, and V. Bertacco, "High Performance Gate-Level Simulation with GP-GPUs," in GPU Computing Gems. Morgan Kaufmann, 2011, ch. 23.
[22]
A. Sen, B. Aksanli, M. Bozkurt, and M. Mert, "Parallel cycle based logic simulation using graphics processing units," in Proc. of IEEE ISPDC, 2010, pp. 71--78.
[23]
M. Nanjundappa, H. D. Patel, B. A. Jose, and S. K. Shukla, "SCGPSim: A fast SystemC simulator on GPUs," Proc. of ACM/IEEE ASP-DAC, pp. 149--154, 2010.
[24]
S. Vinco, D. Chatterjee, V. Bertacco, and F. Fummi, "SAGA: SystemC acceleration on GPU architectures," Proc. of ACM/IEEE DAC, pp. 115--120, 2012.
[25]
N. Bombieri, F. Fummi, and V. Guarnieri, "FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs," Proc. of ACM/IEEE DATE, pp. 562--565, 2012.
[26]
R. Sinha, A. Prakash, and H. D. Patel, "Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs," Proc. of ACM/IEEE ASP-DAC, pp. 455--460, 2012.
[27]
M. Nanjundappa, A. Kaushik, H. D. Patel, and S. K. Shukla, "Accelerating SystemC simulations on GPUs," Proc. of IEEE HLDVT, pp. 1--8, 2012.
[28]
A. Perinkulam and S. Kundu, "Logic simulation using graphics processors," in Proc. International Test Synthesis Workshop, March 2007.
[29]
N. Bombieri, S. Vinco, D. Chatterjee, and V. Bertacco, "SystemC Simulation on GP-GPUs: CUDA vs. OpenCL," Proc. of ACM/IEEE CODES+ISSS, pp. 343--352, 2012.
[30]
NVIDIA CUDA Compute Unified Device Architecture - Programming Guide, NVIDIA, 2008, http://developer.download.nvidia.com.
[31]
OpenCL - The open standard for parallel programming of heterogeneous systems, Khronos Group, http://www.khronos.org/opencl.

Cited By

View all
  • (2016)An Accurate GPU Performance Model for Effective Control Flow Divergence OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.250130335:7(1165-1178)Online publication date: 1-Jul-2016
  • (2014)Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593208(1-6)Online publication date: 1-Jun-2014

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cover image ACM Conferences
DATE '13: Proceedings of the Conference on Design, Automation and Test in Europe
March 2013
1944 pages
ISBN:9781450321532

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EDA Consortium

San Jose, CA, United States

Publication History

Published: 18 March 2013

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DATE 13
Sponsor:
  • EDAA
  • EDAC
  • SIGDA
  • The Russian Academy of Sciences
DATE 13: Design, Automation and Test in Europe
March 18 - 22, 2013
Grenoble, France

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Overall Acceptance Rate 518 of 1,794 submissions, 29%

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Cited By

View all
  • (2016)An Accurate GPU Performance Model for Effective Control Flow Divergence OptimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.250130335:7(1165-1178)Online publication date: 1-Jul-2016
  • (2014)Run-Time Technique for Simultaneous Aging and Power Optimization in GPGPUsProceedings of the 51st Annual Design Automation Conference10.1145/2593069.2593208(1-6)Online publication date: 1-Jun-2014

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