research-article

Survey of Low-Power Testing of VLSI Circuits

Author:

Patrick GirardAuthors Info & Claims

IEEE Design & Test, Volume 19, Issue 3

Pages 82 - 92

https://doi.org/10.1109/MDT.2002.1003802

Published: 01 May 2002 Publication History

Abstract

The author reviews low-power testing techniques for VLSI circuits. He prefaces this with a discussion of power consumption that gives reasons for and consequences of increased power during test. The article ends with a discussion of the opportunity to use such techniques in varying situations.

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Cited By

Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Ding WHsieh HHan CLi JWen X(2016)Test Pattern Modification for Average IR-Drop ReductionIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2015.239129124:1(38-49)Online publication date: 1-Jan-2016
https://dl.acm.org/doi/10.1109/TVLSI.2015.2391291
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Index Terms

Survey of Low-Power Testing of VLSI Circuits
1. Hardware

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Published In

cover image IEEE Design & Test

IEEE Design & Test Volume 19, Issue 3

May 2002

195 pages

ISSN:0740-7475

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Copyright © Copyright © 2002 IEEE. All Rights Reserved.

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 01 May 2002

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Cited By

Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
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https://dl.acm.org/doi/10.1109/TVLSI.2015.2391291
Liao CTao JZeng XSu YZhou DLi X(2016)Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov TreeIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2015.248186835:6(971-984)Online publication date: 1-Jun-2016
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Juneja KPatel DImmadi RSingh BNaudet SAgarwal PVirazel AGirard P(2016)An Effective Power-Aware At-Speed Test Methodology for IP Qualification and CharacterizationJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5621-132:6(721-733)Online publication date: 1-Dec-2016
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Nebel WAtienza D(2015)DP-fillProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755943(836-841)Online publication date: 9-Mar-2015
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Naeini MOoi C(2015)A novel scan architecture for low power scan-based testingVLSI Design10.1155/2015/2640712015(3-3)Online publication date: 1-Jan-2015
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Potluri STrinadh ACh. SKamakoti VChandrachoodan N(2015)DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed TestingACM Transactions on Design Automation of Electronic Systems10.1145/279029721:1(1-25)Online publication date: 2-Dec-2015
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