research-article

Techniques for minimizing power dissipation in scan and combinational circuits during test application

Authors:

V. Dabholkar,

S. Chakravarty,

I. Pomeranz,

S. ReddyAuthors Info & Claims

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 17, Issue 12

Pages 1325 - 1333

https://doi.org/10.1109/43.736572

Published: 01 November 2006 Publication History

Abstract

Reduction of power dissipation during test application is studied for scan designs and for combinational circuits tested using built-in self-test (BIST). The problems are shown to be intractable. Heuristics to solve these problems are discussed. We show that heuristics with good performance bounds can be derived for combinational circuits tested using BIST. Experimental results show that considerable reduction in power dissipation can be obtained using the proposed techniques

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Trinadh APotluri SCh. SKamakoti VSingh S(2017)Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At TestingACM Transactions on Design Automation of Electronic Systems10.1145/308468423:1(1-26)Online publication date: 31-Aug-2017
https://dl.acm.org/doi/10.1145/3084684
Omaña MPadovani MVeliu KMetra CAlt JGalivanche R(2017)New Approaches for Power Binning of High Performance MicroprocessorsIEEE Transactions on Computers10.1109/TC.2017.265506066:7(1159-1171)Online publication date: 7-Jun-2017
https://dl.acm.org/doi/10.1109/TC.2017.2655060
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
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Techniques for minimizing power dissipation in scan and combinational circuits during test application
1. Hardware

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cover image IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume 17, Issue 12

November 2006

138 pages

ISSN:0278-0070

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IEEE Press

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Published: 01 November 2006

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Trinadh APotluri SCh. SKamakoti VSingh S(2017)Optimal Don’t Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At TestingACM Transactions on Design Automation of Electronic Systems10.1145/308468423:1(1-26)Online publication date: 31-Aug-2017
https://dl.acm.org/doi/10.1145/3084684
Omaña MPadovani MVeliu KMetra CAlt JGalivanche R(2017)New Approaches for Power Binning of High Performance MicroprocessorsIEEE Transactions on Computers10.1109/TC.2017.265506066:7(1159-1171)Online publication date: 7-Jun-2017
https://dl.acm.org/doi/10.1109/TC.2017.2655060
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Karmakar RChattopadhyay S(2017)Temperature and data size trade-off in dictionary based test data compressionIntegration, the VLSI Journal10.1016/j.vlsi.2016.11.00257:C(20-33)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.11.002
Deng DGuo YLi Z(2017)A Parallel Test Application Method towards Power ReductionJournal of Electronic Testing: Theory and Applications10.1007/s10836-017-5656-y33:2(157-169)Online publication date: 1-Apr-2017
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Juneja KPatel DImmadi RSingh BNaudet SAgarwal PVirazel AGirard P(2016)An Effective Power-Aware At-Speed Test Methodology for IP Qualification and CharacterizationJournal of Electronic Testing: Theory and Applications10.1007/s10836-016-5621-132:6(721-733)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10836-016-5621-1
Nebel WAtienza D(2015)DP-fillProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755943(836-841)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755943
Aghaee NPeng ZEles PJones ALi HCoskun AMargala M(2015)Efficient Test Application for Rapid Multi-Temperature TestingProceedings of the 25th edition on Great Lakes Symposium on VLSI10.1145/2742060.2742064(3-8)Online publication date: 20-May-2015
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Aghaee NPeng ZEles P(2015)A Test-Ordering Based Temperature-Cycling Acceleration Technique for 3D Stacked ICsJournal of Electronic Testing: Theory and Applications10.1007/s10836-015-5541-531:5-6(503-523)Online publication date: 1-Dec-2015
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Pomeranz I(2014)Low-power skewed-load tests based on functional broadside testsACM Transactions on Design Automation of Electronic Systems10.1145/256666419:2(1-18)Online publication date: 28-Mar-2014
https://dl.acm.org/doi/10.1145/2566664
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Recommendations

Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time

Multiple Scan Chains for Power Minimization during Test Application in Sequential Circuits

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