Article

Testing High Speed VLSI Devices Using Slower Testers

Authors:

Kwang-Ting (Tim) Cheng,

Srimat T. ChakradharAuthors Info & Claims

VTS '99: Proceedings of the 1999 17TH IEEE VLSI Test Symposium

Page 16

Published: 26 April 1999 Publication History

Abstract

The speed of new VLSI designs is rapidly increasing. Assuring the performance of the circuit requires that the circuit be tested at its intended operating speed. The high cost of high speed testers makes it impossible for the testers to follow the designs in terms of speed increase. This gap between the speed of the new circuits and the speed of the testers is not likely to disappear. In this paper, we focus on at-speed strategies for testing high speed designs on slower testers. Conventional at-speed testing strategies assume that the primary inputs/outputs can be applied/observed at the circuit rated speed. This requires a high speed tester. Our assumption is that a fast clock matching the speed of the designs is available. We describe two classes of at-speed strategies that can be used on a low speed tester. The first class consists of testing schemes for which the test generation procedure is independent of the speed of the tester. These methods apply multiple input patterns in one tester cycle and the test class of at-speed testing schemes integrate the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. We present preliminary experimental results for at-speed schemes for slow testers for transition faults.

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Cited By

Swaminathan SChakrabarty K(2019)On Using Twisted-Ring Counters for Test Set Embedding in BISTJournal of Electronic Testing: Theory and Applications10.1023/A:101287270612317:6(529-542)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1012872706123
Girard P(2002)Survey of Low-Power Testing of VLSI CircuitsIEEE Design & Test10.1109/MDT.2002.100380219:3(82-92)Online publication date: 1-May-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1003802
Girard P(2000)Low Power Testing of VLSI CircuitsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855857Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855857

Index Terms

Testing High Speed VLSI Devices Using Slower Testers
1. Hardware
2. Software and its engineering
  1. Software creation and management
    1. Software verification and validation
      1. Software defect analysis
        Software testing and debugging

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Information

Published In

cover image Guide Proceedings

VTS '99: Proceedings of the 1999 17TH IEEE VLSI Test Symposium

April 1999

ISBN:076950146X

Copyright © Copyright (c) 1998 Institute of Electrical and Electronics Engineers, Inc. All rights reserved.

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IEEE Computer Society

United States

Publication History

Published: 26 April 1999

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Cited By

Swaminathan SChakrabarty K(2019)On Using Twisted-Ring Counters for Test Set Embedding in BISTJournal of Electronic Testing: Theory and Applications10.1023/A:101287270612317:6(529-542)Online publication date: 1-Jun-2019
https://dl.acm.org/doi/10.1023/A%3A1012872706123
Girard P(2002)Survey of Low-Power Testing of VLSI CircuitsIEEE Design & Test10.1109/MDT.2002.100380219:3(82-92)Online publication date: 1-May-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1003802
Girard P(2000)Low Power Testing of VLSI CircuitsProceedings of the 1st International Symposium on Quality of Electronic Design10.5555/850998.855857Online publication date: 20-Mar-2000
https://dl.acm.org/doi/10.5555/850998.855857

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