Successful deployment of autonomous systems in a wide range of societal applications depends on error-free operation of the underlying signal processing and control functions. Real-time error detection in nonlinear systems has mostly relied on redundancy ...

Resilience to errors in the underlying hardware is a key design objective for a large class of computing systems, from embedded systems all the way to the cloud. Sources of hardware errors include radiation, circuit aging, variability induced by ...

We present cross-layer exploration for architecting resilience, a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal ...

A multi-band low noise amplifier (LNA) is designed to operate over a wide range of frequencies (with center frequencies at 1.2, 1.7 and 2.2 GHz respectively) using an area efficient switchable $$\pi$$ź network. The LNA can be tuned to different gain and ...

We present a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by ...

A duty-cycle correction technique using a novel pulsewidth modification cell is demonstrated across a frequency range of 100 MHz–3.5 GHz. The technique works at frequencies where most digital techniques implemented in the same technology node fail. An ...

Modern real-time systems encompassing signal processing, communications and control are being increasingly designed in ways that allow them to dynamically adapt to changing workload conditions for reasons of minimizing power consumption and extending ...

We describe a methodology to model the low power and voltage behavior of multi-voltage custom memories in processors. These models facilitate early power-aware verification by abstracting the transistor-level representation of the memory to its power-...

Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ...

Analyzing design vulnerability for soft errors has become a challenging process in large systems with a large number of memory elements. Error injection in a complex system with a sufficiently large sample of error candidates for reasonable accuracy ...

Bounded Model Checking (BMC), as a formal method of verifying VLSI circuits, shows violation of a given circuit property by finding a counter-example to the property along bounded state paths of the circuit. In this paper, we present an emulation ...

Long test times and the use of conventional automatic test equipment (ATE) makes conventional mixed-signal linearity performance testing costly. Diminishing test time of linearity test significantly reduces system-on-a-chip production test costs and, ...

The advent of sensor networks, robots, autonomous vehicles and the smart grid have made the dependability of circuits and systems that control them critical to society and national defense. While significant advances in the design of linear and ...

We present here a report produced by a workshop on 'Addressing failures in exascale computing' held in Park City, Utah, 4-11 August 2012. The charter of this workshop was to establish a common taxonomy about resilience across all the levels in a ...

The rapid shrinking of device geometries in the nanometer regime requires new technology-aware design methodologies. These must be able to evaluate the resilience of the circuit throughout all System on Chip (SoC) abstraction levels. To successfully ...

This paper presents a novel low power 11-bit hybrid ADC using flash and delay line architectures, where a 4-bit flash ADC is followed by a 7-bit delay-line ADC. This hybrid ADC inherits accuracy and power efficiency from flash ADCs and delay-line ADCs, ...

Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay line ADCs are ...

Circuit timing is becoming more and more uncertain under greater process variation as technology scales. Given the fault probability of each timing path and their statistical correlation from a statistical timing framework, the path selection problem ...

Choosing the correct error injection technique is of primary importance in simulation-based design and evaluation of robust systems that are resilient to soft errors. Many low-level (e.g., flip-flop-level) error injection techniques are generally used ...

At the 1999 ITC, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. ...