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Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction

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Abstract

Delay line ADCs are becoming increasingly attractive with technology scaling to smaller dimensions with lower voltages. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. In this paper, we first present a technique which extends harmonic distortion correction techniques to digital calibration of a delay-line ADC. In our simulation results, digital calibration improves SNDR and SFDR to 42.5 dB and 45.4 dB, respectively, compared with the original SNDR of 25.6 dB and the original SFDR of 25.7 dB. In order to reduce the convergence time of the calibration, we inject a periodic 3-bit gray code sequence instead of three pseudorandom numbers for harmonic distortion correction to digitally calibrate an 8-bit delay line ADC. In our simulation results, the SNDR is significantly improved from 25.6 dB to 42.5 dB, with a calibration time of 13.5 milliseconds, which is 64X faster than harmonic distortion correction with the pseudorandom numbers.

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References

  1. Abo AM, Gray PR (1999) A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. In: IEEE J Solid-State Circ, vol 34, no 5, pp 599–606

  2. Boulemnakher M, Andre E, Roux J, Paillardet F (2008) A 1.2 V 4.5 mW 10b 100MS/s pipeline ADC in a 65nm CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers. (ISSCC 08). IEEE, pp 250–611

  3. Chai Y, Wu JT (2012) A 5.37 mW 10b 200MS/s dual-path pipelined ADC. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers. (ISSCC 12), pp 462–464

  4. Chiu Y, Tsang CW, Nikolic B, Gray PR (2004) Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. In: IEEE Trans Circ Syst I: Regular Papers, vol 51, no 1, pp 38–46

  5. Chu J, Brooks L, Lee HS (2010) A zero-crossing based 12b 100MS/s pipelined ADC with decision boundary gap estimation calibration. In: IEEE International VLSI Circuits (VLSIC 10)

  6. Lee H-C, Abraham JA (2013) Digital calibration for 8-bit delay line ADC using harmonic distortion correction. In: 22nd Asian Test Symposium. (ATS 13), pp 128–133

  7. Lee H-C, Abraham JA (2014) Harmonic distortion correction for 8-bit delay line ADC using gray code distortion correction. In: 15th Latin American Test Workshop. (LATW 14), pp 1–4

  8. Henzler S, Koeppe S, Lorenz D, Kamp W, Kuenemund R, Schmitt-Landsiedel D (2008) A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion. In: IEEE J Solid-State Circ, vol 43, no 7, pp 1666– 1676

  9. Li G, Tousi Y, Hassibi A, Afshari E (2009) Delay-line-based analog-to-digital converters. In: IEEE Trans Circ Syst II: Express Briefs, vol 56, no 6, pp 464–468

  10. Liu C-C, Chang SJ, Huang GY, Lin YZ (2010) A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure. In: IEEE J Solid-State Circ, vol 45, no 4, pp 731– 740

  11. Liu C-C, Chang SJ, Huang GY, Lin YZ, Huang CM, Huang CH, Bu L, Tsai CC (2010) A 10b 100MS/s 1.13 mW SAR ADC with binary-scaled error compensation. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers. (ISSCC 10), pp 386–387

  12. Panigada A, Galton I (2006) Digital background correction of harmonic distortion in pipelined ADCs. In: IEEE Trans Circ Syst I: Regular Papers, vol 53, no 9, pp 1885–1895

  13. Panigada A, Galton I (2009) A 130 mw 100 ms/s pipelined ADC with 69 db sndr enabled by digital harmonic distortion correction. In: IEEE J Solid-State Circ, vol 44, no 12, pp 3314–3328

  14. Rabaey J, Chandrakasan A, Nikolić B (2003) Digital integrated circuits. Prentice Hall

  15. Siragusa E, Galton I (2004) A digitally enhanced 1.8 v 15 b 40 ms/s CMOS pipelined ADC. In: IEEE International Solid-State Circuits, Digest of Technical Papers. (ISSCC 04), pp 452– 538

  16. Song H, Jeong DK (2010) Analysis and design of fast settling voltage-controlled delay line with dual-input interpolating delay cells. In: Electron Lett, vol 46, no 11, pp 749–750

  17. Tousi Y, Afshari E (2011) A Miniature 2 mW 4 bit 1.2 GS/s Delay-Line-Based ADC in 65 nm CMOS. In: IEEE J Solid-State Circ, vol 46, no 10, pp 2312–2325

  18. Verbruggen B, Craninckx J, Kuijk M, Wambacq P, Van der Plas G (2008) A 2.2 mW 5b 1.75 GS/s folding flash ADC in 90nm digital CMOS. In: IEEE International Solid-State Circuits Conference, Digest of Technical Papers. (ISSCC 08), pp 252– 611

  19. Verbruggen B, Iriguchi M, Craninckx J (2012) A 1.7 mW 11b 250MS/s 2 × interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers. (ISSCC 12), pp 466–468

  20. Watanabe T, Mizuno T, Makino Y (2003) An all-digital analog-to-digital converter with 12- μV/LSB using moving-average filtering. In: IEEE J Solid-State Circ, vol 38, no 1, pp 120–125

  21. Yoshioka M, Ishikawa K, Takayama T, Tsukamoto S (2010) A 10b 50MS/s 820 μW SAR ADC with on-chip digital calibration. In: IEEE International Solid-State Circuits Conference Digest of Technical Papers. (ISSCC 10), pp 384–385

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  1. Computer Engineering Research Center, The University of Texas at Austin, Austin, TX, 78712, USA

    Hsun-Cheng Lee & Jacob A. Abraham

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  1. Hsun-Cheng Lee
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  2. Jacob A. Abraham
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Correspondence to Hsun-Cheng Lee.

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Responsible Editor: J.-L. Huang

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Lee, HC., Abraham, J.A. Digital Calibration for 8-bit Delay Line ADC Using Harmonic Distortion Correction. J Electron Test 31, 127–138 (2015). https://doi.org/10.1007/s10836-015-5516-6

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