The use of functional vectors has been an industry standard for speed binning purposes of high performance ICs. This practice can be prohibitively expensive as the ICs become faster and more complex. In comparison, structural patterns can target ...

The use of functional vectors has been an industry standard for speed binning of high-performance ICs. This practice can be prohibitively expensive as ICs become faster and more complex. In comparison, structural patterns target performance related ...

This paper describes a novel technique to reuse the existing scanpaths in a chip for delay fault testing and silicon debug. Efficient test and debug techniques for VLSI chips are indispensable in Deep Submicron technologies. A systematic debug scheme is ...

Our method extracts the linearity of on-chip high speed data converters with minimum area overhead. With a loop-back setup in the presence of noise, differential nonlinearities (DNLs) and integral nonlinearities (INLs) of analog-to-digital converters (...

This paper presents a new analog BIST scheme using a slope detection technique. In test mode, a circuit under test (CUT) is stimulated with a periodic rectangular pulse generated from a Linear Feed-Back Shift Register (LFSR) and a periodic invariant ...

Efficient test and debug techniques are indispensable for performance characterization of large complex integrated circuits in deep-submicron and nanometer technologies. Performance characterization of such chips requires on-chip hardware and efficient ...

Oscillation Based Test (OBT) is a low-cost and vectorlesstest technique for analog and mixed-signal integratedcircuits. Previous research with OBT has focussed primarilyon structural issues with an emphasis on fault detectionrather than determining the ...

A successive approximation analog-to-digital converter using a non-binary capacitor array is presented. A perceptron learning rule is used as the capacitor calibration algorithm. The nonlinearity is analyzed using the Volterra series. The effects of ...

This paper presents a novel technique for abstracting designsin order to increase the efficiency of formal propertychecking. Bounded Model Checking (BMC), using Satisfiability(SAT) techniques, are beginning to be widely usedfor checking properties of ...

This paper presents the reasoning behind eliminatingfull-chip gate/switch-level simulations for microprocessors/digital system designs and utilizing RTL models forthe purpose, provided formal boolean equivalence betweenRTL and gate/switch-level models ...

This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Tripple Modular ...

Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the ...

The design and modeling of a high performance successive approximation analog-to-digital converter (ADC) using non-binary capacitor array are presented in this paper. A non-binary capacitor array with 20 capacitors is used to design a 16-bit, 1.5 mega ...

We propose a DSP-based statistical self test approach fortesting on-chip data converters. Analog to digital converters(ADCs) and digital to analog converters (DACs) can betested in a loop-back mode, providing a go/no-go result;however, such tests focus ...

Sequential Automatic Test Pattern Generation is extremely computation intensive and produces acceptable results only on relatively small designs. Hierarchical approaches that target one module at a time and use ad-hoc abstractions for the rest of the ...

This paper presents an efficient approach to testing on-chip Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs) in loop-back mode. On-chip digital signal processing units can be used to generate stimuli. With this methodology, ...

Existing delay test generation techniques focus on testgeneration for combinational blocks, and assume the inputsand outputs of the block to be unconstrained. Test applicationfor delay tests is done by means of enhanced scan, scanshifting or functional ...

Industry is beginning to use Satisfiability (SAT)solvers extensively for formally verifying the correctnessof digital designs. In this paper we compare theperformance of SAT solvers with sequential AutomaticTest Pattern Generation (ATPG) techniques for ...

Systems-on-a-chip (SOCs) with many complex intellectual property (IP) cores require a large number of test patterns and a large volume of data. The computing power of the embedded processor in an SOC can be used to test the cores within the chip ...

This paper develops a novel approach for formally verifying both safety and liveness properties of designs using sequential ATPG tools. The properties are automatically mapped into a monitor circuit with a target fault so that finding a test for the ...