Register coalescing techniques for heterogeneous register architecture with copy sifting
Article No.: 16, Pages 1 - 37
Abstract
Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modified algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.
References
[1]
Ahn, M., Lee, J., Jung, S., Yoon, J. W., and Paek, Y. 2007. A code generation approach for Heterogeneous register architectures. In Proceedings of the 11th Annual Workshop on the Interaction between Compilers and Computer Architecture. IEEE, Los Alamitos, CA.
[2]
Araujo, G. and Malik, S. 1998. Code generation for fixed-point DSPs. ACM Trans. Des. Automat. Electr. Syst. (TODAES) 3, 2, 136--161.
[3]
Bergner, P. E. 1997. Spill Code Minimization Techniques for Graph Coloring Register Allocators. PhD thesis, Minnesota University, Minneapolis, Minnesota.
[4]
Briggs, P. 1992. Register allocation via graph coloring. PhD thesis, Rice University, Houston, TX.
[5]
Chaitin, G. J. 1982. Register allocation and spilling via graph coloring. In Proceedings of the SIGPLAN Symposium on Compiler Construction. ACM, New York, 98--105.
[6]
Daveau, J-M., Thery, T., Lepley, T., and Santana, M. 2004. A retargetable register allocation framework for embedded processors. In Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems. ACM, New York, 202--210.
[7]
Feuerhahn, H. 1988. A data-flow driven resource allocation in a retargetable microcode compiler. In Proceedings of the 21th Annual Workshop on Microprogramming and Microarchitecture. IEEE, Los Alamitos, CA, 105--107.
[8]
George, L. and Appel, A. W. 1996. Iterated register coalescing. ACM Trans. Program. Lang. Syst. 18, 3, 300--324.
[9]
Koes, D. and Goldstein, S. C. 2005. A progressive register allocator for irregular architectures. In Proceedings of the International Symposium on Code Generation and Optimization. ACM, New York, 269--280.
[10]
Kong, T. and Wilken, K. D. 1998. Precise register allocation for irregular architectures. In Proceedings of the 31th Annual ACM/IEEE International Symposium on Microarchitecture. ACM, New York, 297--307.
[11]
Lee, C., Potkonjak M., and Mangione-Smith, W. H. 1997. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture. IEEE, Los Alamitos, CA, 330--335.
[12]
Lee, J. K., Chen, S. Y., and Wu, C. J. 2006. Copy propagation optimizations for VLIW DSP processors with distributed register files. In Proceedings of the 19th International Workshop on Languages and Compilers for Parallel Computing (LCPC). Springer, Berlin, Germany.
[13]
Liem C., May T., and Paulin P. G. 1994. Register assignment through resource classification for ASIP microcode generation. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design. IEEE, Los Alamitos, CA, 397--402.
[14]
Park, J. and Moon, S-M. 2004. Optimistic register coalescing. ACM Trans. Program. Lang. Syst. 26, 4, 735--765.
[15]
Paulin P. G., Liem, C., May, T. C., and Sutarwala, S. 1995. DSP design tool requirements for embedded systems: a telecommunications industrial perspective. J. VLSI Signal Process. Syst. 9, 1-2, 23--47.
[16]
Stallman, R. M. 1994. Using and Porting GNU CC. Free Software Foundation, Cambridge, MA.
[17]
Scholz, B. and Eckstein, E. 2002. Register allocation for irregular architectures. In Proceedings of the Joint Conference on Languages, Compilers and Tools for Embedded Systems: Software and Compilers for Embedded Systems. ACM, New York, 139--148.
[18]
Smith, M. D., Ramsey N., and Ramsey G. 2004. A generalized algorithm for graph-coloring register allocation. In Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation. ACM, New York, 277--288.
[19]
Zivojnovic, V., Velarde, J. M., and Schlager, C. 1994. DSPstone: A DSP-oriented benchmarking methodology. In Proceedings of the International Conference on Signal Processing and Technology. IEEE, Los Alamitos, CA.
[20]
Zivojnovic, V., Pees, S., Schlager, C., Willems, M., Schoenen, R., and Meyr, H. 1996. DSP processor/compiler co-design: a quantitative approach. In Proceedings of the 9th International Symposium on System Synthesis. IEEE, Los Alamitos, CA,108.
Index Terms
- Register coalescing techniques for heterogeneous register architecture with copy sifting
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Publication History
Published: 09 February 2009
Accepted: 01 July 2008
Received: 01 October 2007
Published in TECS Volume 8, Issue 2
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