Coarse Grained Task Parallelization by Dynamic Profiling for Heterogeneous SoC Based Embedded System
In this study, we introduce a methodology for automatically transforming user applications written in C/C++ to a parallel representation consisting of coarse-grained tasks based on dynamic profiling. Such a parallel representation is suitable for mapping ...
TreeHouse: An MLIR-based Compilation Flow for Real-Time Tree-based Inference
Tree-based ensembles stand as the prominent resource-efficient approaches for real-time inference. To optimize their performance, researchers have developed several solutions to accommodate their unique program structure, i.e., consecutive branches and ...
PEak: A Single Source of Truth for Hardware Design and Verification
Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage design space ...
End-To-End Latency of Cause-Effect Chains: A Tutorial
In many applications of cyber-physical systems, a sequence of tasks is necessary to perform a certain functionality. For example, from a sensor to an actuator, the first task reads the sensor value (cause), the second task processes the data, and the ...
Time-Series Forecasting and Sequence Learning Using Memristor-based Reservoir System
Pushing the frontiers of time-series information processing in the ever-growing domain of edge devices with stringent resources has been impeded by the systems’ ability to process information and learn locally on the device. Local processing and learning ...
RTPL: A Real-Time Communication Protocol for LoRa Network
The industrial Internet of Things (IIoT) is prominently emerging in applications of large-scale and wide-area applications, such as oilfield management, smart grid management, real-time equipment monitoring, and integration of traffic management systems ...
Towards a Rust-Like Borrow Checker for C
Memory safety issues in C are the origin of various vulnerabilities that can compromise a program’s correctness or safety from attacks. We propose an approach to tackle memory safety by replicating Rust’s Mid-level Intermediate Representation (MIR) Borrow ...
Hardware Area Efficiently and Real-Time FPGA Implementation of PHMMRGB
For encryption applications on embedded systems, operating in real-time while using minimal system resources is essential. It is expected that efficient and rapid encryption of high-resolution images is to be accomplished with limited hardware resources. ...
Application-Level Evaluation of IEEE 802.1AS Synchronized Time and Linux for Distributed Real-Time Systems
The use of Ethernet and Linux is becoming common in industrial applications, even for those with real-time requirements, although neither of them were originally designed for this purpose. The emergence of Industry 4.0 (also known as Industrial Internet ...
Efficient Deep Learning Infrastructures for Embedded Computing Systems: A Comprehensive Survey and Future Envision
Deep neural networks (DNNs) have recently achieved impressive success across a wide range of real-world vision and language processing tasks, spanning from image classification to many other downstream vision tasks, such as object detection, tracking, and ...
A Proof System for the SMrCaIT Calculus
The rapid development of the Internet of Things (IoT) spurs strong global demand for related applications and technologies, especially in enhancing system reliability and security. Communication security, mobility, and real-time are the three vital ...
ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer
Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of ...
AttackDefense Framework (ADF): Enhancing IoT Devices and Lifecycles Threat Modeling
- Tommaso Sacchetti,
- Marton Bognar,
- Jesse De Meulemeester,
- Benedikt Gierlichs,
- Frank Piessens,
- Volodymyr Bezsmertnyi,
- Maria Chiara Molteni,
- Stefano Cristalli,
- Arianna Gringiani,
- Olivier Thomas,
- Daniele Antonioli
Threat modeling (TM) is essential to manage, prevent, and fix security and privacy issues in our society. TM requires a data model to represent threats and tools to exploit such data. Current TM data models and tools have significant limitations ...
Leveraging HLS to Design a Versatile & High-Performance Classic McEliece Accelerator
By harnessing fundamental quantum properties, a large-scale quantum computer could undermine currently deployed public-key algorithms. The post-quantum, code-based cryptosystem Classic McEliece (CM) addresses this security concern. However, its large ...
Unleashing OpenTitan's Potential: a Silicon-Ready Embedded Secure Element for Root of Trust and Cryptographic Offloading
- Maicol Ciani,
- Emanuele Parisi,
- Alberto Musa,
- Francesco Barchi,
- Andrea Bartolini,
- Ari Kulmala,
- Rafail Psiakis,
- Angelo Garofalo,
- Andrea Acquaviva,
- Rossi Davide
The rapid advancement and exploration of open-hardware RISC-V platforms are catalyzing substantial changes across critical sectors, including autonomous vehicles, smart-city infrastructure, and medical devices. Within this technological evolution, ...
Tutorial: A Novel Runtime Environment for Accelerator-Rich Heterogeneous Architectures
As the landscape of computing advances, system designers are increasingly exploring methodologies that leverage higher levels of heterogeneity to enhance performance within constrained size, weight, power, and cost parameters. CEDR stands as an ecosystem ...
Software Optimization and Design Methodology for Low Power Computer Vision Systems
This tutorial paper addresses a low power computer vision system as an example of a growing application domain of neural networks, exploring various technologies developed to enhance accuracy within the resource and performance constraints imposed by the ...
APB-tree: An Adaptive Pre-built Tree Indexing Scheme for NVM-based IoT Systems
With the proliferation of sensors and the emergence of novel applications, IoT data has grown exponentially in recent years. Given this trend, efficient data management is crucial for a system to easily access vast amounts of information. For decades, B+-...
Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process
Cryptographic competitions played a significant role in stimulating the development and release of open hardware for cryptography. The primary reason was the focus of standardization organizations and other contest organizers on transparency and fairness ...
Performance and Communication Cost of Hardware Accelerators for Hashing in Post-Quantum Cryptography
SPHINCS+ is a signature scheme included in the first NIST post-quantum standard, that bases its security on the underlying hash primitive. As most of the runtime of SPHINCS+ is caused by the evaluation of several hash- and pseudo-random functions, ...
LiteHash: Hash Functions for Resource-Constrained Hardware
The global paradigm shift towards edge computing has led to a growing demand for efficient integrity verification. Hash functions are one-way algorithms which act as a zero-knowledge proof of a datum’s contents. However, it is infeasible to compute hashes ...
Implementing Privacy Homomorphism with Random Encoding and Computation Controlled by a Remote Secure Server
Remote IoT devices face significant security risks due to their inherent physical vulnerability. An adversarial actor with sufficient capability can monitor the devices or exfiltrate data to access sensitive information. Remotely deployed devices such as ...
Customized FPGA Implementation of Authenticated Lightweight Cipher Fountain for IoT Systems
Authenticated Encryption with Associated-Data (AEAD) can ensure both confidentiality and integrity of information in encrypted communication. Distinctive variants are customized from AEAD to satisfy various requirements. In this paper, we take a 128-bit ...
Securing Pacemakers using Runtime Monitors over Physiological Signals
Wearable and implantable medical devices (IMDs) are increasingly deployed to diagnose, monitor, and provide therapy for critical medical conditions. Such medical devices are safety-critical cyber-physical systems (CPSs). These systems support wireless ...
A Design Flow for Scheduling Spiking Deep Convolutional Neural Networks on Heterogeneous Neuromorphic System-on-Chip
Neuromorphic systems-on-chip (NSoCs) integrate CPU cores and neuromorphic hardware accelerators on the same chip. These platforms can execute spiking deep convolutional neural networks (SDCNNs) with a low energy footprint. Modern NSoCs are heterogeneous ...
IoV-Fog-Assisted Framework for Accident Detection and Classification
The evolution of vehicular research into an effectuating area like the Internet of Vehicles (IoV) was verified by technical developments in hardware. The integration of the Internet of Things (IoT) and Vehicular Ad-hoc Networks (VANET) has significantly ...
Reachability Analysis of Sigmoidal Neural Networks
This paper extends the star set reachability approach to verify the robustness of feed-forward neural networks (FNNs) with sigmoidal activation functions such as Sigmoid and TanH. The main drawbacks of the star set approach in Sigmoid/TanH FNN ...
Evolution Function Based Reach-Avoid Verification for Time-varying Systems with Disturbances
In this work, we investigate the reach-avoid problem of a class of time-varying analytic systems with disturbances described by uncertain parameters. Firstly, by proposing the concepts of maximal and minimal reachable sets, we connect the avoidability and ...
AMULET: a Mutation Language Enabling Automatic Enrichment of SysML Models
SysML models are widely used for designing and analyzing complex systems. Model-based design methods often require successive modifications of the models, whether for incrementally refining the design (e.g. in agile development methods) or for testing ...
Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to Practice
- Alexandre Honorat,
- Hai Nam Tran,
- Thierry Gautier,
- Loïc Besnard,
- Shuvra S. Bhattacharyya,
- Jean-Pierre Talpin
The major drawback of using static schedules to execute dataflow applications is their high inflexibility. In real-time systems, periodic schedules make it easier to assert safety guarantees and to decrease the schedule size, but their characteristics ...