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Register assignment through resource classification for ASIP microcode generation

Authors:

Pierre PaulinAuthors Info & Claims

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Pages 397 - 402

Published: 06 November 1994 Publication History

Abstract

Application Specific Instruction-Set Processors (ASIPs) offer designers the ability for high-speed data and control processing with the added flexibility needed for late design specifications, accommodation of design errors, and product evolution. However, code generation for ASIPs is a complex problem and new techniques are needed for its success. The register assignment task can be a critical phase, since often in ASIPs, the number and functionality of available registers is limited, as the designer has opted for simplicity, speed, and low area. Intelligent use of register files is critical to the program execution time, program memory usage and data memory usage. This paper describes a methodology utilizing register classes as a basis for assignment for a particular style of ASIP architectures. The approach gives preference to special purpose registers which are the scarce resources. This naturally leads to the objectives of high speed and low program memory usage. The approach has been implemented in a system called CodeSyn and used on custom ASIP architectures.

References

[1]

E Paulin, C. Liem, T. May, S. Sutarwala, "DSP Design Tool Requirements for Embedded Systems: A Telecommunications Industrial Perspective", to appear in Journal of VLSI Signal Processing (special isssue on synthesis for real-time DSP), Kluwer Academic Publishers, 1994.

Digital Library

[2]

H. Feuerhahn, "Data-Flow Driven Resource Allocation in a Retargetable Microde Compiler", 21st Int. Symposium on Microarchitecture, 1988, pp. 105-107.

Digital Library

[3]

R. Stallman, "Using and Porting GNU CC, version 2.4", distributed with GNU gcc, Free Software Foundation, June 1993

[4]

C. Liem, T. May, E Paulin, "Instruction-Set Matching and Selection for DSP and ASIP Code Generation", Eu~vpean Design & Test Conf. Feb 1994, pp. 31-37.

[5]

S. Sutarwala, E Paulin, Y. Kumar, "Insulin: An Instruction Set Simulation Environment", Proc. of CHDL-93, April 1993, pp. 355-362.

Digital Library

[6]

J. Rabaey, H. DeMan, J. Vanhoof, G. Goossens, and E Catthoor, "CATHEDRAL-II: a sysnthesis system for multiprocessor DSP systems", in D. Gajski (ed.), Silicon Compilation, Addison-Wesley, 1988, pp. 311-360.

[7]

E Marwedel, "A new synthesis algorithm for the MIMO- LA software system", 23rd Design Automation Conf., June 1986, pp. 271-277.

Digital Library

[8]

C. Gebotys, M. Elmasry, "Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis", 28th Design Automation Conf., June 1991, San Francisco, pp. 2-7.

Digital Library

[9]

K. Kucukcakar, A. Parker, "Data path design tradeoffs using MABAL", the International Workshop on High-level Synthesis, Kennebunkport, ME, October 1989.

[10]

G.J. Chaitin, "Register Allocation and Spilling via Graph Coloring", ACM Sigplan Notices, 17, pp. 98-105.

Digital Library

[11]

L.J. Hendren, G.R. Gao, E.R. Altman, C. Mukerji, "A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs", Int. Conf. on Compiler Construction, 1992.

Digital Library

[12]

F.J. Kurdahi, A.C. Parker, "REAL: A Program for Register Allocation", 24th Design Automation Conf., 1987, pp. 210-215.

Digital Library

[13]

F. Depuydt, "Register Optimization and Scheduling for Real-Time Digital Signal Processing Architectures", Ph. D. thesis, Katholieke Universiteit Leuven, Nov. 1993.

[14]

D. Lanneer, M. Cornero, G. Goossens, H. DeMan, "Data Routing: a Paradigm for Efficient Data-path Synthesis and Code Generation", Int. High-Level Synthesis Symposium, May 1994, pp. 17-22.

Digital Library

[15]

F. Franssen, L. Nachtergaele, H. Samsom, F. Catthoor, H. De Man, "Control flow optimizatioin for fast system simulation and storage minimization", Eur. Design and Test Conf., 1994, pp. 20-24.

[16]

W. Verhaegh, E Lippens, E. Aarts, J. Korst, J. van Meerbergen, A. van der Werf, "Modelling Periodicity by PHIDEO Streams", Int. Workshop on High-Level Synthesis, 1992.

Cited By

Ahn MPaek Y(2009)Register coalescing techniques for heterogeneous register architecture with copy siftingACM Transactions on Embedded Computing Systems10.1145/1457255.14572638:2(1-37)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457263
Wang SYang HHu JZiavras S(2008)Asymmetrically banked value-aware register files for low-energy and high-performanceMicroprocessors & Microsystems10.1016/j.micpro.2007.10.00432:3(171-182)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1016/j.micpro.2007.10.004
Ahn MLee JPaek Y(2007)Optimistic coalescing for heterogeneous register architecturesACM SIGPLAN Notices10.1145/1273444.125478142:7(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254781
Show More Cited By

Index Terms

Register assignment through resource classification for ASIP microcode generation
1. Computer systems organization
  1. Embedded and cyber-physical systems
    1. Embedded systems
2. Software and its engineering
  1. Software notations and tools
    1. Compilers
      1. Source code generation

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Information

Published In

cover image ACM Conferences

ICCAD '94: Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

November 1994

771 pages

ISBN:0897916905

Chairmen:
Jochen A. G. Jess
Eindhoven Univ. of Technology, Eindhoven, The Netherlands
,
Richard Rudell
Synopsys, Inc., Mountain View, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS: Computer Society

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IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 06 November 1994

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ICCAD '94

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SIGDA
IEEE-CS

ICCAD '94: International Conference on Computer Aided Design

November 6 - 10, 1994

California, San Jose, USA

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Overall Acceptance Rate 457 of 1,762 submissions, 26%

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Cited By

Ahn MPaek Y(2009)Register coalescing techniques for heterogeneous register architecture with copy siftingACM Transactions on Embedded Computing Systems10.1145/1457255.14572638:2(1-37)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457263
Wang SYang HHu JZiavras S(2008)Asymmetrically banked value-aware register files for low-energy and high-performanceMicroprocessors & Microsystems10.1016/j.micpro.2007.10.00432:3(171-182)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1016/j.micpro.2007.10.004
Ahn MLee JPaek Y(2007)Optimistic coalescing for heterogeneous register architecturesACM SIGPLAN Notices10.1145/1273444.125478142:7(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254781
Ahn MLee JPaek YPande SLi Z(2007)Optimistic coalescing for heterogeneous register architecturesProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254781(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254781
Liem CBreant FJadhav SO'Farrell RRyan RLevia O(2002)Embedded Tools for a Configurable and Customizable DSP ArchitectureIEEE Design & Test10.1109/MDT.2002.104774119:6(27-35)Online publication date: 1-Nov-2002
https://dl.acm.org/doi/10.1109/MDT.2002.1047741
Edwards SLavagno LLee ESangiovanni-Vincentelli A(2001)Design of embedded systemsReadings in hardware/software co-design10.5555/567003.567011(86-107)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/567003.567011
Liem CPaulin PJerraya A(1997)Compilation Methods for the Address Calculation Units of Embedded Processor SystemsDesign Automation for Embedded Systems10.1023/A:10088625108772:1(61-77)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.1023/A%3A1008862510877
Wilberg JCamposano R(1997)VLIW Processor Codesign for Video ProcessingDesign Automation for Embedded Systems10.1023/A:10088187117862:1(79-119)Online publication date: 1-Jan-1997
https://dl.acm.org/doi/10.1023/A%3A1008818711786
van Praet JLanneer DGoossens GGeurts Wde Man H(1996)A Graph Based Processor Model for Retargetable Code GenerationProceedings of the 1996 European conference on Design and Test10.5555/787259.787577Online publication date: 11-Mar-1996
https://dl.acm.org/doi/10.5555/787259.787577
Kolson DNicolau ADutt NKennedy K(1996)A Method for Register Allocation to Loops in Multiple Register File ArchitecturesProceedings of the 10th International Parallel Processing Symposium10.5555/645606.660861(28-33)Online publication date: 15-Apr-1996
https://dl.acm.org/doi/10.5555/645606.660861
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