article

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

Authors:

Pierre G. Paulin,

Shailesh SutarwalaAuthors Info & Claims

Journal of VLSI Signal Processing Systems, Volume 9, Issue 1-2

Pages 23 - 47

Published: 11 January 1995 Publication History

Abstract

This paper describes the trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR)1 and the tools needed to address them. The paper is in three parts: First, we present the results of a three month survey of DSP design practices at BNR. We briefly describe the characteristics of the designs, as well as the DSP design tools used. However, the emphasis is on the main bottlenecks in the design process, and the tools required to address them in the future. Then, we present a proposal for a next generation DSP design environment for telecommunication applications, based on the survey results. Particular emphasis will be given to code generation, system-level simulation, and behavioral synthesis, the three most requested design tools. Finally, we provide a description of FlexWare, an embedded software development system which is being developed internally. This system addresses one important aspect of this next generation environment, namely design tools for application-specific instruction-set processors (ASIP). FlexWare is composed of two main components: CodeSyn, a retargetable microcode synthesis system; and Insulin, a VHDL-based instruction set simulation system.

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Cited By

Ahn MPaek Y(2009)Register coalescing techniques for heterogeneous register architecture with copy siftingACM Transactions on Embedded Computing Systems10.1145/1457255.14572638:2(1-37)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457263
Ahn MLee JPaek Y(2007)Optimistic coalescing for heterogeneous register architecturesACM SIGPLAN Notices10.1145/1273444.125478142:7(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254781
Ahn MLee JPaek YPande SLi Z(2007)Optimistic coalescing for heterogeneous register architecturesProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254781(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254781
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DSP design tool requirements for embedded systems: A telecommunications industrial perspective

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Information & Contributors

Information

Published In

cover image Journal of VLSI Signal Processing Systems

Journal of VLSI Signal Processing Systems Volume 9, Issue 1-2

Special issue on design environments for DSP

Jan. 1995

135 pages

ISSN:0922-5773

Editors:
Ingrid Verbauwhede
Univ. of California at Berkeley, Berkeley
,
Jan Rabaey
Univ. of California at Berkeley, Berkeley
,
Earl E. Swartzlander
Univ. of Texas at Austin, Austin
,
S. Y. Kung
Princeton Univ., Princeton, NJ

Issue’s Table of Contents

Copyright © Copyright © 1995 Kluwer Academic Publishers.

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Kluwer Academic Publishers

United States

Publication History

Published: 11 January 1995

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Cited By

Ahn MPaek Y(2009)Register coalescing techniques for heterogeneous register architecture with copy siftingACM Transactions on Embedded Computing Systems10.1145/1457255.14572638:2(1-37)Online publication date: 9-Feb-2009
https://dl.acm.org/doi/10.1145/1457255.1457263
Ahn MLee JPaek Y(2007)Optimistic coalescing for heterogeneous register architecturesACM SIGPLAN Notices10.1145/1273444.125478142:7(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1273444.1254781
Ahn MLee JPaek YPande SLi Z(2007)Optimistic coalescing for heterogeneous register architecturesProceedings of the 2007 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems10.1145/1254766.1254781(93-102)Online publication date: 13-Jun-2007
https://dl.acm.org/doi/10.1145/1254766.1254781
Salice FVecchio LPomante LFornaciari WLamont GHaddad HPapadopoulos GPanda B(2003)Partitioning of embedded applications onto heterogeneous multiprocessor architecturesProceedings of the 2003 ACM symposium on Applied computing10.1145/952532.952662(661-665)Online publication date: 9-Mar-2003
https://dl.acm.org/doi/10.1145/952532.952662
Mesman BTimmer Avan Meerbergen JJess J(2001)Constraint analysis for DSP code generationReadings in hardware/software co-design10.5555/567003.567045(485-498)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/567003.567045
Edwards SLavagno LLee ESangiovanni-Vincentelli A(2001)Design of embedded systemsReadings in hardware/software co-design10.5555/567003.567011(86-107)Online publication date: 1-Jun-2001
https://dl.acm.org/doi/10.5555/567003.567011
Chiou DJain PRudolph LDevadas SDe Micheli G(2000)Application-specific memory management for embedded systems using software-controlled cachesProceedings of the 37th Annual Design Automation Conference10.1145/337292.337523(416-419)Online publication date: 1-Jun-2000
https://dl.acm.org/doi/10.1145/337292.337523
Hadjiyiannis GHanono SDevadas S(2000)ISDLDesign Automation for Embedded Systems10.1023/A:10089374250646:1(39-69)Online publication date: 1-Sep-2000
https://dl.acm.org/doi/10.1023/A%3A1008937425064
Mesman BStrik MTimmer Avan Meerbergen JJess JDewilde PRammig FMusgrave G(1998)A constraint driven approach to loop pipelining and register bindingProceedings of the conference on Design, automation and test in Europe10.5555/368058.368187(377-383)Online publication date: 23-Feb-1998
https://dl.acm.org/doi/10.5555/368058.368187
Kalavade ASubrahmanyam POtten RYasuura H(1997)Hardware/software partitioning for multi-function systemsProceedings of the 1997 IEEE/ACM international conference on Computer-aided design10.5555/266388.266543(516-521)Online publication date: 13-Nov-1997
https://dl.acm.org/doi/10.5555/266388.266543
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