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An efficient resource-constrained global scheduling technique for superscalar and VLIW processors

Authors:

Soo-Mook Moon,

Kemal EbcioğluAuthors Info & Claims

ACM SIGMICRO Newsletter, Volume 23, Issue 1-2

Pages 55 - 71

https://doi.org/10.1145/144965.145000

Published: 10 December 1992 Publication History

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Porpodas VCintra M(2014)Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW ProcessorsLanguages and Compilers for Parallel Computing10.1007/978-3-319-09967-5_16(275-291)Online publication date: 1-Oct-2014
https://doi.org/10.1007/978-3-319-09967-5_16
Porpodas VCintra MRabbah RRaghunathan A(2013)CAeSaRProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555738(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555738
Porpodas VCintra M(2013)CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662513(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662513
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An efficient resource-constrained global scheduling technique for superscalar and VLIW processors

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Association for Computing Machinery

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Published: 10 December 1992

Published in SIGMICRO Volume 23, Issue 1-2

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Porpodas VCintra M(2014)Aligned Scheduling: Cache-Efficient Instruction Scheduling for VLIW ProcessorsLanguages and Compilers for Parallel Computing10.1007/978-3-319-09967-5_16(275-291)Online publication date: 1-Oct-2014
https://doi.org/10.1007/978-3-319-09967-5_16
Porpodas VCintra MRabbah RRaghunathan A(2013)CAeSaRProceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems10.5555/2555729.2555738(1-10)Online publication date: 29-Sep-2013
https://dl.acm.org/doi/10.5555/2555729.2555738
Porpodas VCintra M(2013)CAeSaR: Unified cluster-assignment scheduling and communication reuse for clustered VLIW processors2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)10.1109/CASES.2013.6662513(1-10)Online publication date: Sep-2013
https://doi.org/10.1109/CASES.2013.6662513
Govindarajan R(2010)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420040579.ch17Online publication date: 7-Mar-2010
https://doi.org/10.1201/9781420040579.ch17
Govindarajan R(2009)Instruction SchedulingThe Compiler Design Handbook10.1201/9781420043839.ch19(19-1-19-57)Online publication date: 7-Dec-2009
https://doi.org/10.1201/9781420043839.ch19
Altman EGao G(2005)Optimal software pipelining through enumeration of schedulesEuro-Par'96 Parallel Processing10.1007/BFb0024784(833-840)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0024784
Novack SNicolau A(2005)Resource-Directed Loop PipeliningLanguages and Compilers for Parallel Computing10.1007/BFb0017253(192-206)Online publication date: 10-Jun-2005
https://doi.org/10.1007/BFb0017253
Mahadevan URamakrishnan S(2005)Instruction scheduling over regions: A framework for scheduling across basic blocksCompiler Construction10.1007/3-540-57877-3_28(419-434)Online publication date: 30-May-2005
https://doi.org/10.1007/3-540-57877-3_28
Novack SNicolau A(2005)VISTA: The Visual Interface for Scheduling Transformations and AnalysisLanguages and Compilers for Parallel Computing10.1007/3-540-57659-2_26(449-460)Online publication date: 31-May-2005
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Gupta SDutt NGupta RNicolau A(2003)SPARKProceedings of the 16th International Conference on VLSI Design10.5555/832285.835535Online publication date: 4-Jan-2003
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