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Hardware implementation of a general multi-way jump mechanism

Authors:

Soo-Mook Moon,

Scott D. Carson,

Ashok K. AgrawalaAuthors Info & Claims

MICRO 23: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture

Pages 38 - 45

Published: 30 November 1990 Publication History

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Abstract

A VLIW architecture capable of testing multiple conditions in one cycle must support effective multiway (conditional) jumps. In this paper, a hardware-implemented, fast, and space-efficient multi-way jump mechanism is developed that speeds up the execution of multiple conditional jumps and reduces wasted storage. A cluster of multiple conditional jumps packed in an instruction can form an arbitrary rooted DAG (Directed Acyclic Graph), where each node corresponds to a condition. Our scheme provides a hardware device called an M-unit, which can combinationally produce the next target address using an encoded description of the DAG and the actual test bits. A technique to reduce the number of different configurations is introduced, along with a memory packing scheme that minimizes wasted memory.

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Cited By

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Moon SCarson S(1995)Generalized Multiway Branch Unit for VLIW MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.4069616:8(850-862)Online publication date: 1-Aug-1995
https://dl.acm.org/doi/10.1109/71.406961
Moon SEbcioğlu KWolfe AMangione-Smith W(1993)A study on the number of memory ports in multiple instruction issue machinesProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255251(49-59)Online publication date: 1-Dec-1993
https://dl.acm.org/doi/10.5555/255235.255251
Moon SEbcioğlu KHwu W(1992)An efficient resource-constrained global scheduling technique for superscalar and VLIW processorsProceedings of the 25th annual international symposium on Microarchitecture10.5555/144953.145000(55-71)Online publication date: 10-Dec-1992
https://dl.acm.org/doi/10.5555/144953.145000
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Information & Contributors

Information

Published In

MICRO 23: Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture

November 1990

299 pages

ISBN:0897914139

Publisher

IEEE Computer Society Press

Washington, DC, United States

Publication History

Published: 30 November 1990

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MICRO90

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SIGMICRO
IEEE-CS

MICRO90: 23nd Annual Workshop on Microprogramming and Microarchitecture

November 27 - 29, 1990

Florida, Orlando, USA

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Overall Acceptance Rate 484 of 2,242 submissions, 22%

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Cited By

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Moon SCarson S(1995)Generalized Multiway Branch Unit for VLIW MicroprocessorsIEEE Transactions on Parallel and Distributed Systems10.1109/71.4069616:8(850-862)Online publication date: 1-Aug-1995
https://dl.acm.org/doi/10.1109/71.406961
Moon SEbcioğlu KWolfe AMangione-Smith W(1993)A study on the number of memory ports in multiple instruction issue machinesProceedings of the 26th annual international symposium on Microarchitecture10.5555/255235.255251(49-59)Online publication date: 1-Dec-1993
https://dl.acm.org/doi/10.5555/255235.255251
Moon SEbcioğlu KHwu W(1992)An efficient resource-constrained global scheduling technique for superscalar and VLIW processorsProceedings of the 25th annual international symposium on Microarchitecture10.5555/144953.145000(55-71)Online publication date: 10-Dec-1992
https://dl.acm.org/doi/10.5555/144953.145000
Moon SEbcioğlu K(1992)An efficient resource-constrained global scheduling technique for superscalar and VLIW processorsACM SIGMICRO Newsletter10.1145/144965.14500023:1-2(55-71)Online publication date: 10-Dec-1992
https://dl.acm.org/doi/10.1145/144965.145000

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Special- or General-Purpose Hardware for Prolog: A Comparison

An Improved Pipelined Processor Architecture Eliminating Branch and Jump Penalty

Delay-dependent H∞ filtering for singular Markovian jump systems with general uncomplete transition probabilities