Typical embedded processors, such as Digital Signal Processors (DSPs), usually adopt Very Long Instruction Word (VLIW) architecture to improve computing efficiency. The performance of VLIW processors heavily relies on Instruction-Level Parallelism (ILP). ...

The simulation of biological neural networks holds immense promise for advancing both neuroscience and artificial intelligence. Due to its high complexity, it requires powerful computers. However, the high proportion of communication and routing ...

This paper presents a novel modulo scheduling method, which is called Expanded Modulo Scheduling (EMS). Unlike existing methods which regard loop unrolling and scheduling respectively, EMS supports adaptive loop expansion, and provides a unified ...

Code generation for VLIW processors includes several optimization problems like code optimization, instruction scheduling, and register allocation. The high complexity of these problems usually does not allow the computation of the optimal ...

This paper proposes an EPIC (Explicitly Parallel Instruction Computing Architecture) type processor based on MIPS. VLIW processors can execute multiple instructions simultaneously, but due to dependency of instructions, it is often impossible to ...

Microcontroller units used in harsh environmental conditions are manufactured using large semiconductor technology nodes in order to provide reliable operation, even at high temperatures or increased radiation exposition. These large technology ...

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities--several dozens of GOPs for real-time HD 1080p video streams. ...

Instruction Level Parallelism (ILP) is the number of instructions that can be executed in simultaneously a program in a clock cycle. The microprocessors exploit ILP by means of several techniques that have been implemented in the last decades and ...

Because most traditional homogeneous and heterogeneous processors have a fixed design that limits its runtime adaptability, they are not able to cope with the varying application behavior when one considers the axes of fault tolerance, performance, and ...

We propose automatic synthesis of application specific instruction set processors (ASIPs). We use pipeline execution of multi-op machine-instructions, e.g., $$*({ reg}1*{ reg}2) = (*{ reg}3)+(*{ reg}4)$$ź(reg1źreg2)=(źreg3)+(źreg4) (C-syntax) an ...

In the past years, the Internet of Things (IoT) is changing our working mode and life. In order to address the demand of massive data, low latency and low power consumption in IoT applications, the wireless industry is moving to its fifth generation (5G)...

Specialized Digital Signal Processors (DSPs), which can be found in a wide range of modern devices, play an important role in power-efficient, high-performance image processing. Applications including camera sensor post-processing and computer vision ...

High-performance and flexible configurable SHIFT instructions targeted at symmetrical cipher processing are proposed in this paper, in order to dispel the bottleneck of symmetrical cipher algorithms realized by universal processors. Through analyzing ...

Compressed Sensing (CS) methods impact is important in the health care systems. The acquisition and the processing speed of many medical imaging applications is highly improved using this technique. Orthogonal Matching Pursuit (OMP) is one of the widely ...

Because of technology scaling, the soft error rate has been increasing in digital circuits, which affects system reliability. Therefore, modern processors, including VLIW architectures, must have means to mitigate such effects to guarantee reliable ...

Wireless standards are evolving rapidly due to the exponential growth in the number of portable devices along with the applications with high data rate requirements. Adaptable software based signal processing implementations for these devices can make ...

Loop retiming has been extensively studied to maximize instruction-level parallelism (ILP) of multiple function units by rearranging the dependence delays in a uniform loop. Recently loop retiming technique has been proposed to mitigate the migration ...

The design philosophy of VLIW processors is to maximize instruction level parallelism (ILP) starting from compiler and machine code level to all the way down to memory and computational blocks. For this purpose, VLIW tailoring has been an important ...

OpenCL is a standard for parallel programming of heterogeneous systems. The benefits of a common programming standard are clear; multiple vendors can provide support for application descriptions written according to the standard, thus reducing the ...

General-purpose graphic processing units (GP-GPUs) offer high computational throughput using thousands of integrated processing elements (PEs). These PEs are stressed during workload execution, and negative bias temperature instability (NBTI) adversely ...