Article

Optimization objectives and models of variation for statistical gate sizing

Authors:

Matthew R. Guthaus,

Natesan Venkateswaran,

Vladimir Zolotov,

Dennis Sylvester,

Richard B. BrownAuthors Info & Claims

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

Pages 313 - 316

https://doi.org/10.1145/1057661.1057736

Published: 17 April 2005 Publication History

Get Access

Abstract

This paper approaches statistical optimization by examining gate delay variation models and optimization objectives. Most previous work on statistical optimization has focused exclusively on the optimization algorithms without considering the effects of the variation models and objective functions. This work empirically derives a simple variation model that is then used to optimize for robustness. Optimal results from example circuits used to study the effect of the statistical objective function on parametric yield.

References

[1]

A. Agarwal, D. Blaauw, and V. Zolotov. Statistical timing analysis for intra-die process variations with spatial correlations. In ICCAD, pages 900--907, 2003.

Digital Library

Google Scholar

[2]

A. Agarwal, V. Zolotov, and D. T. Blaauw. Statistical timing analysis using bounds and selective enumeration. TCAD, 22(9):1243--1260, September 2003.

Digital Library

Google Scholar

[3]

X. Bai, C. Visweswariah, P. N. Strenski, and D. J. Hathaway. Uncertainty-aware circuit optimization. In DAC, pages 58--63, June 2002.

Digital Library

Google Scholar

[4]

H. Chang and S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In ICCAD, pages 621--625, 2003.

Digital Library

Google Scholar

[5]

J. P. Fishburn and A. E. Dunlop. TILOS: a posynomial programming approach to transistor sizing. In ICCAD, pages 326--328, 1985.

Google Scholar

[6]

K. Okada, K. Yamaoka, and H. Onodera. A statistical gate-delay model considering intra-gate variability. In ICCAD, pages 908--913, November 2003.

Digital Library

Google Scholar

[7]

K. Okada, K. Yamaoka, and H. Onodera. A statistical gate delay model for intra-chip and inter-chip variabilities. In ASPDAC, pages 31--36, January 2003.

Digital Library

Google Scholar

[8]

M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers. Matching properties of MOS transistors. JSSC, 24(5):1433--1440, October 1989.

Google Scholar

[9]

A. Srivastava, D. Sylvester, and D. Blaauw. Statistical optimization of leakage power considering process variations using dual-vth and sizing. In DAC, pages 773--779, June 2004.

Digital Library

Google Scholar

[10]

I. Sutherland, B. Sproull, and D. Harris. Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann Publisher, 1999.

Digital Library

Google Scholar

[11]

C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan. First-order incremental block-based statistical timing analysis. In DAC, pages 331--336, 2004.

Digital Library

Google Scholar

Cited By

View all

Beece DVisweswariah CXiong JZolotov V(2013)Transistor sizing of custom high-performance digital circuits with parametric yield considerationsOptimization and Engineering10.1007/s11081-012-9208-015:1(217-241)Online publication date: 16-Jan-2013
https://doi.org/10.1007/s11081-012-9208-0
Andrus CGuthaus MBrunvard EStevens KCavallaro JZhang T(2012)Lithography-aware layout compactionProceedings of the great lakes symposium on VLSI10.1145/2206781.2206818(147-152)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206818
Cong JGupta PLee J(2010)Evaluating statistical power optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206139029:11(1750-1762)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061390
Show More Cited By

Index Terms

Optimization objectives and models of variation for statistical gate sizing
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design

Recommendations

Statistical gate sizing for timing yield optimization
ICCAD '05: Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Variability in the chip design process has been relatively increasing with technology scaling to smaller dimensions. Using worst case analysis for circuit optimization severely over-constrains the system and results in solutions with excessive ...
Statistical timing yield optimization by gate sizing

In this paper, we propose a statistical gate sizing approach to maximize the timing yield of a given circuit, under area constraints. Our approach involves statistical gate delay modeling, statistical static timing analysis, and gate sizing. Experiments ...
Handling multiple objectives with particle swarm optimization

This paper presents an approach in which Pareto dominance is incorporated into particle swarm optimization (PSO) in order to allow this heuristic to handle problems with several objective functions. Unlike other current proposals to extend PSO to solve ...

Comments

Please enable JavaScript to view thecomments powered by Disqus.

Information & Contributors

Information

Published In

GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI

April 2005

518 pages

ISBN:1595930574

DOI:10.1145/1057661

General Chair:
John Lach
University of Virginia
,
Program Chairs:
Gang Qu
University of Maryland, College Park
,
Yehea Ismail
Northwestern University

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 17 April 2005

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Article

Conference

GLSVLSI05

Sponsor:

GLSVLSI05: Great Lakes Symposium on VLSI 2005

April 17 - 19, 2005

Illinois, Chicago, USA

Acceptance Rates

Overall Acceptance Rate 312 of 1,156 submissions, 27%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

7
Total Citations
View Citations
222
Total Downloads

Downloads (Last 12 months)0
Downloads (Last 6 weeks)0

Reflects downloads up to 24 Sep 2024

Other Metrics

View Author Metrics

Citations

Cited By

View all

Beece DVisweswariah CXiong JZolotov V(2013)Transistor sizing of custom high-performance digital circuits with parametric yield considerationsOptimization and Engineering10.1007/s11081-012-9208-015:1(217-241)Online publication date: 16-Jan-2013
https://doi.org/10.1007/s11081-012-9208-0
Andrus CGuthaus MBrunvard EStevens KCavallaro JZhang T(2012)Lithography-aware layout compactionProceedings of the great lakes symposium on VLSI10.1145/2206781.2206818(147-152)Online publication date: 3-May-2012
https://dl.acm.org/doi/10.1145/2206781.2206818
Cong JGupta PLee J(2010)Evaluating statistical power optimizationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2010.206139029:11(1750-1762)Online publication date: 1-Nov-2010
https://dl.acm.org/doi/10.1109/TCAD.2010.2061390
Cong JGupta PLee JWakabayashi K(2009)On the futility of statistical power optimizationProceedings of the 2009 Asia and South Pacific Design Automation Conference10.5555/1509633.1509686(167-172)Online publication date: 19-Jan-2009
https://dl.acm.org/doi/10.5555/1509633.1509686
Cong JGupta PLee J(2009)On the futility of statistical power optimization2009 Asia and South Pacific Design Automation Conference10.1109/ASPDAC.2009.4796475(167-172)Online publication date: Jan-2009
https://doi.org/10.1109/ASPDAC.2009.4796475
Guthaus MVenkateswarant NVisweswariaht CZolotov V(2005)Gate sizing using incremental parameterized statistical timing analysisProceedings of the 2005 IEEE/ACM International conference on Computer-aided design10.5555/1129601.1129746(1029-1036)Online publication date: 31-May-2005
https://dl.acm.org/doi/10.5555/1129601.1129746
Guthaus MVenkateswaran NVisweswariah CZolotov V(2005)Gate sizing using incremental parameterized statistical timing analysisICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.10.1109/ICCAD.2005.1560213(1029-1036)Online publication date: 2005
https://doi.org/10.1109/ICCAD.2005.1560213

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Cited By

Index Terms

Recommendations

Statistical gate sizing for timing yield optimization

Statistical timing yield optimization by gate sizing

Handling multiple objectives with particle swarm optimization