Article

Statistical optimization of leakage power considering process variations using dual-Vth and sizing

Authors:

Ashish Srivastava,

Dennis Sylvester,

David BlaauwAuthors Info & Claims

DAC '04: Proceedings of the 41st annual Design Automation Conference

Pages 773 - 778

https://doi.org/10.1145/996566.996775

Published: 07 June 2004 Publication History

Abstract

Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variability in performance and leakage of a design. While extensive work has been performed in the past on statistical analysis methods, circuit optimization is still largely performed using deterministic methods. We show in this paper that deterministic optimization quickly looses effectiveness for stringent performance and leakage constraints in designs with significant variability. We then propose a statistically aware dual-Vt and sizing algorithm where both delay constraints and sensitivity computations are performed in a statistical manner. We demonstrate that using this statistically aware optimization, leakage power can be reduced by 15-35% compared to traditional deterministic analysis. The improvements increase for strict delay constraints making statistical optimization especially important for high performance designs.

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Cited By

Ebrahimipour SGhavami BRaji M(2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
https://doi.org/10.1049/iet-cds.2018.5616
Yao ZMaoxiang YKeke WQingwu WLi DHuaguo L(2017)Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff2017 13th IEEE International Conference on Electronic Measurement & Instruments (ICEMI)10.1109/ICEMI.2017.8265748(146-151)Online publication date: Oct-2017
https://doi.org/10.1109/ICEMI.2017.8265748
S RVasudevan V(2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2896819
Show More Cited By

Index Terms

Statistical optimization of leakage power considering process variations using dual-Vth and sizing
1. Hardware
  1. Integrated circuits
    1. Logic circuits

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Published In

cover image ACM Conferences

DAC '04: Proceedings of the 41st annual Design Automation Conference

June 2004

1002 pages

ISBN:1581138288

DOI:10.1145/996566

General Chair:
Sharad Malik
Princeton University, Princeton, NJ
,
Program Chairs:
Limor Fix
Intel Semiconductors Ltd., Haifa, Israel
,
Andrew B. Kahng
University of California at San Diego, La Jolla, CA

Copyright © 2004 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 07 June 2004

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June 7 - 11, 2004

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Cited By

Ebrahimipour SGhavami BRaji M(2019)Adjacency criticality: a simple yet effective metric for statistical timing yield optimisation of digital integrated circuitsIET Circuits, Devices & Systems10.1049/iet-cds.2018.561613:7(979-987)Online publication date: 22-Oct-2019
https://doi.org/10.1049/iet-cds.2018.5616
Yao ZMaoxiang YKeke WQingwu WLi DHuaguo L(2017)Multi-Vth technique based on potential critical paths for NBTI effect and leakage tradeoff2017 13th IEEE International Conference on Electronic Measurement & Instruments (ICEMI)10.1109/ICEMI.2017.8265748(146-151)Online publication date: Oct-2017
https://doi.org/10.1109/ICEMI.2017.8265748
S RVasudevan V(2016)Efficient Algorithms for Discrete Gate Sizing and Threshold Voltage Assignment Based on an Accurate Analytical Statistical Yield GradientACM Transactions on Design Automation of Electronic Systems10.1145/289681921:4(1-27)Online publication date: 18-May-2016
https://dl.acm.org/doi/10.1145/2896819
Wang NZhong WHao CChen SYoshimura TZhu Y(2016)Leakage-Power-Aware Scheduling With Dual-Threshold Voltage DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2016.253522124:10(3067-3079)Online publication date: Oct-2016
https://doi.org/10.1109/TVLSI.2016.2535221
Abbas ZOlivieri MRipp A(2016)Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradationsJournal of Computational Electronics10.1007/s10825-016-0878-215:4(1424-1439)Online publication date: 1-Dec-2016
https://dl.acm.org/doi/10.1007/s10825-016-0878-2
Abbas ZOlivieri M(2016)Optimal transistor sizing for maximum yield in variation-aware standard cell designInternational Journal of Circuit Theory and Applications10.1002/cta.216744:7(1400-1424)Online publication date: 1-Jul-2016
https://dl.acm.org/doi/10.1002/cta.2167
Casagrande TRanganathan NNebel WAtienza D(2015)GTFUZZProceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition10.5555/2755753.2755908(677-682)Online publication date: 9-Mar-2015
https://dl.acm.org/doi/10.5555/2755753.2755908
Wei SZheng JPotkonjak MHutchings BBetz V(2013)Low power FPGA design using post-silicon device aging (abstract only)Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays10.1145/2435264.2435340(277-277)Online publication date: 11-Feb-2013
https://dl.acm.org/doi/10.1145/2435264.2435340
Zhuo CChang YSylvester DBlaauw DLin Y(2010)Design time body bias selection for parametric yield improvementProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899880(681-688)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899880
Seomun JPaik SShin YLin Y(2010)Bounded potential slackProceedings of the 2010 Asia and South Pacific Design Automation Conference10.5555/1899721.1899859(581-586)Online publication date: 18-Jan-2010
https://dl.acm.org/doi/10.5555/1899721.1899859
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