Article

A statistical gate delay model for intra-chip and inter-chip variabilities

Authors:

Hidetoshi OnoderaAuthors Info & Claims

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Pages 31 - 36

https://doi.org/10.1145/1119772.1119779

Published: 21 January 2003 Publication History

Abstract

This paper proposes a model to calculate statistical gate-delay variation caused by intra-chip and inter-chip variabilities. Our model consists of a statistical transistor model and a gate-delay model. We present a modeling and extracting method of transistor characteristics for the intra-chip variability and the inter-chip variability. In the modeling of the intra-chip variability, it is important to consider a gate-size dependence by which the amount of intra-chip variation is affected. This effect is not captured in a statistical delay analysis reported so far. Our gate-delay model characterizes a statistical gate delay variation using a response surface method (RSM) according to the intra-chip and inter-chip variability of each transistor in a gate. We evaluate the accuracy of our model, and we show some simulated results of a circuit delay variation characterized by the measured variances of transistor currents.

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Cited By

Liu TChen CMilor L(2015)Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splinesSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085438(272-279)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085438
Shinkai KHashimoto MOnoye T(2013)A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variationsIntegration, the VLSI Journal10.1016/j.vlsi.2013.01.00346:4(345-358)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1016/j.vlsi.2013.01.003
Ni CAl Tarawneh ZRussell GBystrov A(2013)Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural LevelIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-36157-9_2(11-20)Online publication date: 2013
https://doi.org/10.1007/978-3-642-36157-9_2
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A statistical gate delay model for intra-chip and inter-chip variabilities
1. Computing methodologies
  1. Modeling and simulation
    1. Model development and analysis

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Published In

cover image ACM Conferences

ASP-DAC '03: Proceedings of the 2003 Asia and South Pacific Design Automation Conference

January 2003

865 pages

ISBN:0780376609

DOI:10.1145/1119772

General Chair:
Hiroto Yasuura

Copyright © 2003 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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IPSJ: Information Processing Society of Japan
IEEE Circuits and Systems Society
SIGDA: ACM Special Interest Group on Design Automation
IEICE: Institute of Electronics, Information and Communication Engineers

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2003

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Overall Acceptance Rate 466 of 1,454 submissions, 32%

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Citations

Cited By

Liu TChen CMilor L(2015)Accurate standard cell characterization and statistical timing analysis using multivariate adaptive regression splinesSixteenth International Symposium on Quality Electronic Design10.1109/ISQED.2015.7085438(272-279)Online publication date: Mar-2015
https://doi.org/10.1109/ISQED.2015.7085438
Shinkai KHashimoto MOnoye T(2013)A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variationsIntegration, the VLSI Journal10.1016/j.vlsi.2013.01.00346:4(345-358)Online publication date: 1-Sep-2013
https://dl.acm.org/doi/10.1016/j.vlsi.2013.01.003
Ni CAl Tarawneh ZRussell GBystrov A(2013)Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural LevelIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-642-36157-9_2(11-20)Online publication date: 2013
https://doi.org/10.1007/978-3-642-36157-9_2
Aghababa HForouzandeh BAfzali-Kusha A(2012)High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobilityJournal of Zhejiang University SCIENCE C10.1631/jzus.C110027313:6(460-471)Online publication date: 2-Jun-2012
https://doi.org/10.1631/jzus.C1100273
Zhang WSinghee AXiong JHabitz PJoshi AVisweswariah CSundquist JHu A(2012)A dynamic method for efficient random mismatch characterization of standard cellsProceedings of the International Conference on Computer-Aided Design10.1145/2429384.2429419(180-186)Online publication date: 5-Nov-2012
https://dl.acm.org/doi/10.1145/2429384.2429419
Alioto MPalumbo GPennisi M(2010)Understanding the effect of process variations on the delay of static and domino logicIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.201545518:5(697-710)Online publication date: 1-May-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2015455
TAKAHASHI STSUKIYAMA S(2009)A New Statistical Timing Analysis Using Gaussian Mixture Models for Delay and Slew Propagated TogetherIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences10.1587/transfun.E92.A.900E92-A:3(900-911)Online publication date: 2009
https://doi.org/10.1587/transfun.E92.A.900
Goel AVrudhula STaraporevala FGhanta P(2009)Statistical Timing Models for Large Macro Cells and IP Blocks Considering Process VariationsIEEE Transactions on Semiconductor Manufacturing10.1109/TSM.2008.201162922:1(3-11)Online publication date: Feb-2009
https://doi.org/10.1109/TSM.2008.2011629
da Silva DReis ARibas R(2009)CMOS logic gate performance variability related to transistor network arrangementsMicroelectronics Reliability10.1016/j.microrel.2009.07.02349:9-11(977-981)Online publication date: Sep-2009
https://doi.org/10.1016/j.microrel.2009.07.023
Goel ABhardwaj SGhanta PVrudhula S(2007)Computation of Joint Timing Yield of Sequential Networks Considering Process VariationsIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation10.1007/978-3-540-74442-9_13(125-137)Online publication date: 2007
https://doi.org/10.1007/978-3-540-74442-9_13
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