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Transistor sizing of custom high-performance digital circuits with parametric yield considerations

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Abstract

Transistor sizing is a classic computer-aided design problem that has received much attention in the literature. Given the increasing importance of process variation in deep sub-micron circuits and the wide-spread use of statistical methods, the sizing problem for such circuits warrants revisiting. This paper addresses transistor sizing as one that can be solved via interior point nonlinear optimization with an objective function that is directly dependent on statistical process variation. Our technique automatically adjusts transistor sizes to maximize parametric yield at a given timing performance, or to maximize performance at a required parametric yield. Our results show that for process variation sensitive circuits, consisting of thousands of independently tunable transistors, a statistically aware tuner can give more robust, higher yield solutions when compared to deterministic circuit tuning and is thus an attractive alternative to the Monte Carlo methods that are typically used to size transistors in such circuits. To the best of our knowledge, this is the first working system to optimize transistor sizes in custom circuits using a process variation aware tuner.

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Authors and Affiliations

  1. IBM Thomas J. Watson Research Center, Yorktown Heights, NY, 10598, USA

    Daniel K. Beece, Chandu Visweswariah, Jinjun Xiong & Vladimir Zolotov

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  1. Daniel K. Beece
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  2. Chandu Visweswariah
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  3. Jinjun Xiong
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  4. Vladimir Zolotov
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Correspondence to Daniel K. Beece.

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Beece, D.K., Visweswariah, C., Xiong, J. et al. Transistor sizing of custom high-performance digital circuits with parametric yield considerations. Optim Eng 15, 217–241 (2014). https://doi.org/10.1007/s11081-012-9208-0

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