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Linxiao Shen
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2020 – today
- 2024
- [j22]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-layout simulation driven analog circuit sizing. Sci. China Inf. Sci. 67(4) (2024) - [j21]Heyi Li
, Kaixuan Du
A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. IEEE J. Solid State Circuits 59(2): 435-448 (2024) - [j20]Kaixuan Du, Maoqiang Liu, Zhixuan Wang, Heyi Li, Yuanxin Bao, Linxiao Shen, Le Ye:
A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4713-4717 (2024) - [c33]Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye:
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. CICC 2024: 1-2 - [c32]Ao Shi, Yizhou Zhang, Lixia Han, Zheng Zhou, Yiyang Chen, Lifeng Liu, Linxiao Shen, Peng Huang, Xiaoyan Liu, Jinfeng Kang:
Low Quantization Error Readout Circuit with Fully Charge-Domain Calculation for Computation-in-Memory Deep Neural Network. ISCAS 2024: 1-5 - [c31]Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye:
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. ISSCC 2024: 72-74 - [c30]Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang:
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. ISSCC 2024: 168-170 - [c29]Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang:
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. ISSCC 2024: 174-176 - 2023
- [j19]Le Ye, Zhixuan Wang
Research progress on low-power artificial intelligence of things (AIoT) chip design. Sci. China Inf. Sci. 66(10) (2023) - [j18]Xiaohan Gao
Interactive Analog Layout Editing With Instant Placement and Routing Legalization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 698-711 (2023) - [j17]Xin Xin
A Power-Efficient 13-Tap FIR Filter and an IIR Filter Embedded in a 10-Bit SAR ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 70(6): 2293-2305 (2023) - [j16]Ying Liu
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3075-3088 (2023) - [c28]Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye:
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. ESSCIRC 2023: 121-124 - [c27]Yiqi Jing, Zhixuan Wang
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. ISCAS 2023: 1-4 - [c26]Yihan Zhang, You You, Wenjie Ren
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. ISSCC 2023: 68-69 - [c25]Peiyu Chen
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. ISSCC 2023: 140-141 - [c24]Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye:
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. ISSCC 2023: 346-347 - [i2]Xiaohan Gao, Haoyi Zhang, Siyuan Ye, Mingjie Liu, David Z. Pan, Linxiao Shen, Runsheng Wang, Yibo Lin, Ru Huang:
Post-Layout Simulation Driven Analog Circuit Sizing. CoRR abs/2310.14049 (2023) - 2022
- [j15]Xiyuan Tang
Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 69(6): 2249-2262 (2022) - [c23]Hao Zhang
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. CICC 2022: 1-2 - [c22]Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye:
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. ISCAS 2022: 1973-1977 - [c21]Yihan Zhang
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. ISSCC 2022: 184-186 - [c20]Ying Liu, Zhixuan Wang
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. ISSCC 2022: 372-374 - 2021
- [j14]Abhishek Mukherjee
A 74.5-dB Dynamic Range 10-MHz BW CT-ΔΣ ADC With Distributed-Input VCO and Embedded Capacitive-π Network in 40-nm CMOS. IEEE J. Solid State Circuits 56(2): 476-487 (2021) - [j13]Zhixuan Wang
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. IEEE J. Solid State Circuits 56(9): 2804-2816 (2021) - [j12]Zhixuan Wang
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. IEEE J. Solid State Circuits 56(11): 3274-3288 (2021) - [j11]Heyi Li
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. IEEE J. Solid State Circuits 56(12): 3560-3572 (2021) - [j10]Le Ye
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 4821-4834 (2021) - [c19]Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun:
10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC 2021: 170-172 - [c18]Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun:
A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC 2021: 382-384 - 2020
- [j9]Yi Zhong
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS. IEEE J. Solid State Circuits 55(2): 356-368 (2020) - [j8]Wenda Zhao
A 0.025-mm2 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure. IEEE J. Solid State Circuits 55(3): 666-679 (2020) - [j7]Yi Shen
A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique. IEEE J. Solid State Circuits 55(3): 680-692 (2020) - [j6]Xiyuan Tang
An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits 55(4): 1011-1022 (2020) - [j5]Xiyuan Tang
An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter. IEEE J. Solid State Circuits 55(11): 3064-3075 (2020) - [j4]Xiyuan Tang
A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits 55(12): 3248-3259 (2020) - [j3]Jiaxin Liu
A 13-bit 0.005-mm2 40-MS/s SAR ADC With kT/C Noise Cancellation. IEEE J. Solid State Circuits 55(12): 3260-3270 (2020) - [c17]Mingjie Liu, Wuxi Li, Keren Zhu
S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity. ASP-DAC 2020: 193-198 - [c16]Xin Xin, Linxiao Shen, Xiyuan Tang, Yi Shen, Jueping Cai, Nan Sun:
A Power-Efficient 13-Tap FIR filter and an IIR Filter Embedded in a 10-bit SAR ADC. A-SSCC 2020: 1-4 - [c15]Hanrui Wang, Kuan Wang, Jiacheng Yang
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. DAC 2020: 1-6 - [c14]Mingjie Liu, Keren Zhu
Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning. DATE 2020: 496-501 - [c13]Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun:
9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC 2020: 162-164 - [c12]Jiaxin Liu, Xiyuan Tang, Wenda Zhao, Linxiao Shen, Nan Sun:
16.5 A 13b 0.005mm2 40MS/s SAR ADC with kT/C Noise Cancellation. ISSCC 2020: 258-260 - [c11]Zhelu Li, Arnab Dutta, Abhishek Mukherjee, Xiyuan Tang, Linxiao Shen, Lenian He, Nan Sun:
A SAR ADC with Reduced kT/C Noise by Decoupling Noise PSD and BW. VLSI Circuits 2020: 1-2 - [i1]Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han:
GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. CoRR abs/2005.00406 (2020)
2010 – 2019
- 2019
- [j2]Linxiao Shen
A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits 54(12): 3375-3385 (2019) - [c10]Shaolan Li, Wenda Zhao, Biying Xu, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Nanshu Lu, David Z. Pan, Nan Sun:
A 0.025-mm2 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure. CICC 2019: 1-3 - [c9]Xiyuan Tang, Yi Shen, Linxiao Shen, Wenda Zhao, Zhangming Zhu, Visvesh Sathe, Nan Sun:
A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique. CICC 2019: 1-4 - [c8]Biying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan:
WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout. DAC 2019: 66 - [c7]Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan:
Device Layer-Aware Analytical Placement for Analog Circuits. ISPD 2019: 19-26 - [c6]Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun:
A 0.01mm2 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor. ISSCC 2019: 64-66 - [c5]Xiyuan Tang, Shaolan Li, Linxiao Shen, Wenda Zhao, Xiangxing Yang, Randy Williams
A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter. ISSCC 2019: 296-297 - [c4]Xiyuan Tang, Begum Kasap
An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits 2019: 140- - [c3]Linxiao Shen, Abhishek Mukherjee, Shaolan Li, Xiyuan Tang, Nanshu Lu, Nan Sun:
A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 PEF. VLSI Circuits 2019: 144- - 2018
- [j1]Linxiao Shen
A 1-V 0.25-µW Inverter Stacking Amplifier With 1.07 Noise Efficiency Factor. IEEE J. Solid State Circuits 53(3): 896-905 (2018) - [c2]Yi Zhong
A Second-Order Purely VCO-Based CT Δ∑ ADC Using a Modified DPLL in 40-nm CMOS. A-SSCC 2018: 93-94 - 2017
- [c1]Hyoyoung Jeong
NFC-enabled, tattoo-like stretchable biosensor manufactured by "cut-and-paste" method. EMBC 2017: 4094-4097
Coauthor Index
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