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Tianyu Jia
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2020 – today
- 2024
- [j13]Yu-Shun Hsiao
, Zishen Wan
Silent Data Corruption in Robot Operating System: A Case for End-to-End System-Level Fault Analysis Using Autonomous UAVs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(4): 1037-1050 (2024) - [j12]Ying Liu
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2660-2673 (2024) - [j11]Yufei Ma
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2735-2748 (2024) - [j10]Jingyao Sun
Multiscale Canonical Coherence for Functional Corticomuscular Coupling Analysis. IEEE J. Biomed. Health Informatics 28(2): 812-822 (2024) - [c43]Tiange Yang, Yuanyuan Zou, Jinfeng Liu, Tianyu Jia, Shaoyuan Li:
Time Robust Model Predictive Control for Heterogeneous Multi-Agent Systems Under Global Temporal Logic Tasks. ACC 2024: 2440-2445 - [c42]Yikan Qiu, Yufei Ma, Meng Wu
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. CICC 2024: 1-2 - [c41]Meng Wu
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. CICC 2024: 1-2 - [c40]Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia:
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. DAC 2024: 137:1-137:6 - [c39]Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye:
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. DAC 2024: 145:1-145:6 - [c38]Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang:
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. DAC 2024: 245:1-245:6 - [c37]Martin Cochet, Karthik Swaminathan, Erik Jens Loscalzo, Joseph Zuckerman, Maico Cassel dos Santos, Davide Giri, Alper Buyuktosunoglu, Tianyu Jia, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
BlitzCoin: Fully Decentralized Hardware Power Management for Accelerator-Rich SoCs. ISCA 2024: 801-817 - [c36]Maico Cassel dos Santos, Tianyu Jia, Joseph Zuckerman, Martin Cochet, Davide Giri, Erik Jens Loscalzo, Karthik Swaminathan, Thierry Tambe, Jeff Jun Zhang, Alper Buyuktosunoglu, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca Piccolboni, Gabriele Tombesi, David Trilla, John-David Wellman, En-Yu Yang, Aporva Amarnath, Ying Jing, Bakshree Mishra, Joshua Park, Vignesh Suresh, Sarita V. Adve, Pradip Bose, David Brooks, Luca P. Carloni, Kenneth L. Shepard, Gu-Yeon Wei:
14.5 A 12nm Linux-SMP-Capable RISC-V SoC with 14 Accelerator Types, Distributed Hardware Power Management and Flexible NoC-Based Data Orchestration. ISSCC 2024: 262-264 - [c35]Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. ISSCC 2024: 484-486 - [c34]Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia:
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. VLSI Technology and Circuits 2024: 1-2 - [c33]Erik Jens Loscalzo, Martin Cochet, Joseph Zuckerman, Samira Zalias, Michael Lekas, Stephen Cahill, Tianyu Jia, Karthik Swaminathan, Maico Cassel dos Santos, Davide Giri, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, David Brooks, Gu-Yeon Wei, Luca P. Carloni, Pradip Bose, Kenneth L. Shepard:
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j9]Le Ye, Zhixuan Wang
Research progress on low-power artificial intelligence of things (AIoT) chip design. Sci. China Inf. Sci. 66(10) (2023) - [j8]Gabriele Tombesi
SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs. IEEE Des. Test 40(6): 64-75 (2023) - [j7]Yiran Zhang, Xin Tong, Tingxi Liu, Limin Duan
Spatio-Temporal Evolution of Inland Lakes and Their Relationship with Hydro-Meteorological Factors in Horqin Sandy Land, China. Remote. Sens. 15(11): 2719 (2023) - [j6]Georgios Zacharopoulos
Trireme: Exploration of Hierarchical Multi-level Parallelism for Hardware Acceleration. ACM Trans. Embed. Comput. Syst. 22(3): 53:1-53:23 (2023) - [c32]Xi Chen, Aly Shoukry, Tianyu Jia, Xin Zhang
A 65nm Fully-integrated Fast-switching Buck Converter with Resonant Gate Drive and Automatic Tracking. CICC 2023: 1-2 - [c31]Ying Liu, Zhiyuan Chen, Zhixuan Wang
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. CICC 2023: 1-2 - [c30]Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang:
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. DAC 2023: 1-6 - [c29]Yu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi:
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. DATE 2023: 1-6 - [c28]Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang:
ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. ICCAD 2023: 1-9 - [c27]Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. ISLPED 2023: 1-6 - [c26]Peiyu Chen
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. ISSCC 2023: 140-141 - [c25]Thierry Tambe
A 12nm 18.1TFLOPs/W Sparse Transformer Processor with Entropy-Based Early Exit, Mixed-Precision Predication and Fine-Grained Power Management. ISSCC 2023: 342-343 - [i6]Tiange Yang, Yuanyuan Zou, Jinfeng Liu, Tianyu Jia, Shaoyuan Li:
Multi-Agent Robust Control Synthesis from Global Temporal Logic Tasks. CoRR abs/2309.11477 (2023) - 2022
- [c24]Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury:
FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. DATE 2022: 430-435 - [c23]Tianyu Jia, En-Yu Yang, Yu-Shun Hsiao, Jonathan J. Cruz, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi:
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge. DATE 2022: 909-914 - [c22]Yuhao Ju, Shiyu Guo, Zixuan Liu, Tianyu Jia, Jie Gu:
A Differentiable Neural Computer for Logic Reasoning with Scalable Near-Memory Computing and Sparsity Based Enhancement. ESSCIRC 2022: 93-96 - [c21]Tianyu Jia, Paolo Mantovani, Maico Cassel dos Santos, Davide Giri, Joseph Zuckerman, Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Chandramoorthy, John-David Wellman, Kevin Tien, Luca P. Carloni, Kenneth L. Shepard, David Brooks, Gu-Yeon Wei, Pradip Bose:
A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC. ESSCIRC 2022: 269-272 - [c20]Maico Cassel dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth L. Shepard, Luca P. Carloni, Pradip Bose:
A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components. ICCAD 2022: 20:1-20:9 - [i5]Georgios Zacharopoulos, Adel Ejjeh, Ying Jing, En-Yu Yang, Tianyu Jia, Iulian Brumar, Jeremy Intan, Muhammad Huzaifa, Sarita V. Adve, Vikram S. Adve, Gu-Yeon Wei, David Brooks:
Trireme: Exploring Hierarchical Multi-Level Parallelism for Domain Specific Hardware Acceleration. CoRR abs/2201.08603 (2022) - [i4]Zishen Wan, Aqeel Anwar, Abdulrahman Mahmoud, Tianyu Jia, Yu-Shun Hsiao, Vijay Janapa Reddi, Arijit Raychowdhury:
FRL-FI: Transient Fault Analysis for Federated Reinforcement Learning-Based Navigation Systems. CoRR abs/2203.07276 (2022) - [i3]Tianyu Jia, En-Yu Yang, Yu-Shun Hsiao, Jonathan J. Cruz, David Brooks, Gu-Yeon Wei, Vijay Janapa Reddi:
OMU: A Probabilistic 3D Occupancy Mapping Accelerator for Real-time OctoMap at the Edge. CoRR abs/2205.03325 (2022) - 2021
- [j5]Tianyu Jia
A Dynamic Timing Enhanced DNN Accelerator With Compute-Adaptive Elastic Clock Chain Technique. IEEE J. Solid State Circuits 56(1): 55-65 (2021) - [c19]En-Yu Yang, Tianyu Jia, David Brooks, Gu-Yeon Wei:
FlexACC: A Programmable Accelerator with Application-Specific ISA for Flexible Deep Neural Network Inference. ASAP 2021: 266-273 - [c18]Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury:
Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. DAC 2021: 841-846 - [c17]Tianyu Jia
5 Hz rTMS improves motor-imagery based BCI classification performance. EMBC 2021: 6116-6120 - [c16]Thierry Tambe
EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference. MICRO 2021: 830-844 - [i2]Yu-Shun Hsiao, Zishen Wan
MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial Vehicles. CoRR abs/2105.12882 (2021) - [i1]Zishen Wan, Aqeel Anwar, Yu-Shun Hsiao, Tianyu Jia, Vijay Janapa Reddi, Arijit Raychowdhury:
Analyzing and Improving Fault Tolerance of Learning-Based Navigation Systems. CoRR abs/2111.04957 (2021) - 2020
- [j4]Tianyu Jia
Small-Dimension Feature Matrix Construction Method for Decoding Repetitive Finger Movements From Electroencephalogram Signals. IEEE Access 8: 56060-56071 (2020) - [j3]Tianyu Jia
An Adaptive Clock Scheme Exploiting Instruction-Based Dynamic Timing Slack for a GPGPU Architecture. IEEE J. Solid State Circuits 55(8): 2259-2269 (2020) - [c15]Tianyu Jia, Yuhao Ju, Jie Gu:
31.3 A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators. ISSCC 2020: 482-484 - [c14]Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu:
NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance. MICRO 2020: 1097-1109
2010 – 2019
- 2019
- [j2]Tianyu Jia
An Instruction-Driven Adaptive Clock Management Through Dynamic Phase Scaling and Compiler Assistance for a Low Power Microprocessor. IEEE J. Solid State Circuits 54(8): 2327-2338 (2019) - [c13]Tianyu Jia, Yue Liu:
Words in Kitchen: An Instance of Leveraging Virtual Reality Technology to Learn Vocabulary. ISMAR Adjunct 2019: 150-155 - [c12]Tianyu Jia, Russ Joseph, Jie Gu:
An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purpose Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution. ISSCC 2019: 318-320 - [c11]Todd Takken, Andrew Ferencz, Chung-Shiang Wu, Liam McAuliffe, Tianyu Jia, Xin Zhang:
A 48 V Input 0.75 V Output DC-DC Converter Power Block for HPC Systems and Datacenters (invited paper). VLSI Circuits 2019: 168- - 2018
- [j1]Tianyu Jia
A Fully Integrated Buck Regulator With 2-GHz Resonant Switching for Low-Power Applications. IEEE J. Solid State Circuits 53(9): 2663-2674 (2018) - [c10]Tianyu Jia, Jie Gu:
A Fully-integrated LC-Oscillator Based Buck Regulator with Autonomous Resonant Switching for Low-Power Applications. A-SSCC 2018: 179-182 - [c9]Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph:
Compiler-guided instruction-level clock scheduling for timing speculative processors. DAC 2018: 40:1-40:6 - [c8]Tianyu Jia, Russ Joseph, Jie Gu:
An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor. ESSCIRC 2018: 94-97 - [c7]Kofi Otseidu, Tianyu Jia, Joshua Bryne, Levi J. Hargrove, Jie Gu:
Design and optimization of edge computing distributed neural processor for biomedical rehabilitation with sensor fusion. ICCAD 2018: 120 - [c6]Josiah D. Hester, Tianyu Jia, Jie Gu:
Holistic Energy Management with μProcessor Co-Optimization in Fully Integrated Battery-Less IoTs. SoCC 2018: 7-12 - 2017
- [c5]Tianyu Jia, Russ Joseph, Jie Gu:
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. DAC 2017: 48:1-48:6 - [c4]Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu:
(Invited) Software-guided greybox design methodology with integrated power and clock management. MWSCAS 2017: 894-897 - 2016
- [c3]Tianyu Jia, Xiaomeng Zhao, Zheng Wang, Dahan Gong, Guiguang Ding:
Model Transformation and Data Migration from Relational Database to MongoDB. BigData Congress 2016: 60-67 - [c2]Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu:
Exploration of associative power management with instruction governed operation for ultra-low power design. DAC 2016: 152:1-152:6 - 2015
- [c1]Yue Wu, Tianyu Jia, Bo Xia, Xinlong Ma, Li Kang, Xiaodong Yang:
Suppression of VCO pulling effects using even-harmonic quiet transmitting circuits. ESSCIRC 2015: 128-131
Coauthor Index
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last updated on 2024-11-14 00:55 CET by the dblp team
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