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2020 – today
- 2024
- [j25]Heyi Li
, Kaixuan Du
A 0.39-mm2 Stacked Standard-CMOS Humidity Sensor Using a Charge-Redistribution Correlated Level Shifting Floating Inverter Amplifier and a VCO-Based Zoom CDC. IEEE J. Solid State Circuits 59(2): 435-448 (2024) - [j24]Ying Liu
Sparsity-Aware In-Memory Neuromorphic Computing Unit With Configurable Topology of Hybrid Spiking and Artificial Neural Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2660-2673 (2024) - [j23]Yufei Ma
DCIM-GCN: Digital Computing-in-Memory Accelerator for Graph Convolutional Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(6): 2735-2748 (2024) - [j22]Kaixuan Du, Maoqiang Liu, Zhixuan Wang, Heyi Li, Yuanxin Bao, Linxiao Shen, Le Ye:
A Single-Ended SAR ADC With Fully Differential DAC Switching Scheme for IoT Applications. IEEE Trans. Circuits Syst. II Express Briefs 71(11): 4713-4717 (2024) - [c51]Jie Li, Linxiao Shen, Siyuan Ye, Jihang Gao, Jiajia Cui, Xinhang Xu, Zhuoyi Chen, Yaohui Luan, Yuanxin Bao, Ru Huang, Le Ye:
An 8b 1GS/s SAR ADC with Metastability-Based Resolution/Speed Enhancement and Self-Tuning Delay Achieving 47.2dB SNDR at Nyquist Input. CICC 2024: 1-2 - [c50]Yikan Qiu, Yufei Ma, Meng Wu
Quartet: A 22nm 0.09mJ/lnference Digital Compute-in-Memory Versatile AI Accelerator with Heterogeneous Tensor Engines and Off-Chip-Less Dataflow. CICC 2024: 1-2 - [c49]Meng Wu
S2D-CIM: A 22nm 128Kb Systolic Digital Compute-in-Memory Macro with Domino Data Path for Flexible Vector Operation and 2-D Weight Update in Edge AI Applications. CICC 2024: 1-2 - [c48]Mingxuan Li, Qinzhe Zhi, Yanchi Dong, Le Ye, Tianyu Jia:
SPARK: An Efficient Hybrid Acceleration Architecture with Run-Time Sparsity-Aware Scheduling for TinyML Learning. DAC 2024: 137:1-137:6 - [c47]Yiqi Jing, Meng Wu, Jiaqi Zhou, Yiyang Sun, Yufei Ma, Ru Huang, Tianyu Jia, Le Ye:
AIG-CIM: A Scalable Chiplet Module with Tri-Gear Heterogeneous Compute-in-Memory for Diffusion Acceleration. DAC 2024: 145:1-145:6 - [c46]Zhiyuan Chen, Yufei Ma, Keyi Li, Yifan Jia, Guoxiang Li, Meng Wu, Tianyu Jia, Le Ye, Ru Huang:
An In-Memory Computing Accelerator with Reconfigurable Dataflow for Multi-Scale Vision Transformer with Hybrid Topology. DAC 2024: 245:1-245:6 - [c45]Xinhang Xu, Siyuan Ye, Yaohui Luan, Jihang Gao, Jie Li, Jiajia Cui, Hao Zhang, Ru Huang, Linxiao Shen, Le Ye:
3.10 A 0.69/0.58-PEF 1.6nW/24nW Capacitively Coupled Chopper Instrumentation Amplifier with an Input-Boosted First Stage in 22nm/180nm CMOS. ISSCC 2024: 72-74 - [c44]Siyuan Ye, Linxiao Shen, Jihang Gao, Jie Li, Zhuoyi Chen, Xinhang Xu, Jiajia Cui, Hao Zhang, Xing Zhang, Le Ye, Ru Huang:
9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting. ISSCC 2024: 168-170 - [c43]Zhuoyi Chen, Linxiao Shen, Siyuan Ye, Jihang Gao, Jie Li, Jiajia Cui, Xinhang Xu, Yaohui Luan, Hao Zhang, Le Ye, Ru Huang:
9.4 A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique. ISSCC 2024: 174-176 - [c42]Ying Liu, Yufei Ma, Ninghui Shang, Tianhao Zhao, Peiyu Chen
30.2 A 22nm 0.26nW/Synapse Spike-Driven Spiking Neural Network Processing Unit Using Time-Step-First Dataflow and Sparsity-Adaptive In-Memory Computing. ISSCC 2024: 484-486 - [c41]Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia:
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. VLSI Technology and Circuits 2024: 1-2 - 2023
- [j21]Le Ye, Zhixuan Wang
Research progress on low-power artificial intelligence of things (AIoT) chip design. Sci. China Inf. Sci. 66(10) (2023) - [j20]Lingxin Meng, Yaopeng Hu, Yibo Zhao
A 1.2-V 2.87-μ W 94.0-dB SNDR Discrete-Time 2-0 MASH Delta-Sigma ADC. IEEE J. Solid State Circuits 58(6): 1636-1645 (2023) - [j19]Yuyan Liu
A 4.96-μW 15-bit Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC. IEEE J. Solid State Circuits 58(6): 1646-1656 (2023) - [j18]Zhaonan Lu
A 1 V 1.07 μW 15-Bit Pseudo-Pseudo-Differential Incremental Zoom ADC. IEEE J. Solid State Circuits 58(9): 2575-2584 (2023) - [j17]Ying Liu
An 82-nW 0.53-pJ/SOP Clock-Free Spiking Neural Network With 40-μs Latency for AIoT Wake-Up Functions Using a Multilevel-Event-Driven Bionic Architecture and Computing-in-Memory Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(8): 3075-3088 (2023) - [c40]Renjie Wei, Kaifeng Wang, Zhixuan Wang
A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications. ASICON 2023: 1-4 - [c39]Peiyu Chen, Meng Wu, Yufei Ma, Le Ye, Ru Huang:
RIMAC: An Array-Level ADC/DAC-Free ReRAM-Based in-Memory DNN Processor with Analog Cache and Computation. ASP-DAC 2023: 228-233 - [c38]Ying Liu, Zhiyuan Chen, Zhixuan Wang
A A 22nm 0.43pJ/SOP Sparsity-Aware In-Memory Neuromorphic Computing System with Hybrid Spiking and Artificial Neural Network and Configurable Topology. CICC 2023: 1-2 - [c37]Yanchi Dong, Tianyu Jia, Kaixuan Du, Yiqi Jing, Qijun Wang, Pixian Zhan, Yadong Zhang, Fengyun Yan, Yufei Ma, Yun Liang, Le Ye, Ru Huang:
A Model-Specific End-to-End Design Methodology for Resource-Constrained TinyML Hardware. DAC 2023: 1-6 - [c36]Xinhang Xu, Linxiao Shen, Siyuan Ye, Jiayi Wu, Zhuoyi Chen, Jihang Gao, Jiajia Cui, Yihan Zhang, Ru Huang, Le Ye:
A 12.5-ppm/°C 1.086-nW/kHz Relaxation Oscillator with Clock-Gated Discrete-Time Comparator in 22nm CMOS Technology. ESSCIRC 2023: 121-124 - [c35]Mengyu Li, Shuang Song
A 1.2V 62.2dB SNDR SAR-Assisted Event-Driven Clockless Level-Crossing ADC for Time-Sparse Signal Acquisition. ESSCIRC 2023: 289-292 - [c34]Kaifeng Wang, Yongqin Wu, Ye Ren, Renjie Wei, Zerui Chen, Jianfeng Hang, Zhixuan Wang
First Foundry Platform Demonstration of Hybrid Tunnel FET and MOSFET Circuits Based on a Novel Laminated Well Isolation Technology. ESSDERC 2023: 13-16 - [c33]Xiuping Cui, Size Zheng, Tianyu Jia, Le Ye, Yun Liang:
ARES: A Mapping Framework of DNNs Towards Diverse PIMs with General Abstractions. ICCAD 2023: 1-9 - [c32]Yiqi Jing, Zhixuan Wang
An Information-Aware Adaptive Data Acquisition System using Level-Crossing ADC with Signal-Dependent Full Scale and Adaptive Resolution for IoT Applications. ISCAS 2023: 1-4 - [c31]Yiqi Jing, Yiyang Sun, Xiao Wang, Wentao Zhao, Meng Wu
DCIM-3DRec: A 3D Reconstruction Accelerator with Digital Computing-in-Memory and Octree-Based Scheduler. ISLPED 2023: 1-6 - [c30]Yihan Zhang, You You, Wenjie Ren
A 0.954nW 32kHz Crystal Oscillator in 22nm CMOS with Gm-C-Based Current Injection Control. ISSCC 2023: 68-69 - [c29]Peiyu Chen
A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing. ISSCC 2023: 140-141 - [c28]Jihang Gao, Linxiao Shen, Heyi Li, Siyuan Ye, Jie Li, Xinhang Xu, Jiajia Cui, Yunhung Gao, Ru Huang, Le Ye:
A 7.9fJ/Conversion-Step and 37.12aFrms Pipelined-SAR Capacitance-to-Digital Converter with kT/C Noise Cancellation and Incomplete-Settling-Based Correlated Level Shifting. ISSCC 2023: 346-347 - 2022
- [j16]Menglian Zhao, Yibo Zhao, Huajun Zhang
A 4-μW Bandwidth/Power Scalable Delta-Sigma Modulator Based on Swing-Enhanced Floating Inverter Amplifiers. IEEE J. Solid State Circuits 57(3): 709-718 (2022) - [j15]Yuanxin Bao, Le Ye:
A 16-bit 300-kS/s foreground calibration SAR ADC with single-ended/differential configurable input modes. Microelectron. J. 128: 105563 (2022) - [j14]Yuanxin Bao, Le Ye:
A power-efficient acquisition front end for the Li-ion battery management systems. Microelectron. J. 129: 105598 (2022) - [c27]Hao Zhang
A 77μW 115dB-Dynamic-Range 586fA-Sensitivity Current-Domain Continuous-Time Zoom ADC with Pulse-Width-Modulated Resistor DAC and Background Offset Compensation Scheme. CICC 2022: 1-2 - [c26]Yikan Qiu, Yufei Ma, Wentao Zhao, Meng Wu, Le Ye, Ru Huang:
DCIM-GCN: Digital Computing-in-Memory to Efficiently Accelerate Graph Convolutional Networks. ICCAD 2022: 46:1-46:9 - [c25]Chang Xue, Yihan Zhang, Peiyu Chen
Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET. ISCAS 2022: 595-599 - [c24]Xinhang Xu, Siyuan Ye, Jihang Gao, Yihan Zhang, Linxiao Shen, Le Ye:
A 32-ppm/°C 0.9-nW/kHz Relaxation Oscillator with Event-Driven Architecture and Charge Reuse Technique. ISCAS 2022: 1973-1977 - [c23]Yu-Yan Liu, Menglian Zhao, Yibo Zhao, Xiaopeng Yu, Nianxiong Nick Tan, Le Ye, Zhichao Tan:
A 4.96µW 15b Self-Timed Dynamic-Amplifier-Based Incremental Zoom ADC. ISSCC 2022: 170-172 - [c22]Yihan Zhang
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. ISSCC 2022: 184-186 - [c21]Ying Liu, Zhixuan Wang
An 82nW 0.53pJ/SOP Clock-Free Spiking Neural Network with 40µs Latency for AloT Wake-Up Functions Using Ultimate-Event-Driven Bionic Architecture and Computing-in-Memory Technique. ISSCC 2022: 372-374 - [c20]Yaopeng Hu, Yibo Zhao, Wanyuan Qu, Le Ye, Menglian Zhao, Zhichao Tan:
A 2.87μW 1kHz-BW 94.0dB-SNDR 2-0 MASH ADC Using FIA with Dynamic-Body-Biasing Assisted CLS Technique. ISSCC 2022: 410-412 - 2021
- [j13]Zhixuan Wang
A Software-Defined Always-On System With 57-75-nW Wake-Up Function Using Asynchronous Clock-Free Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. IEEE J. Solid State Circuits 56(9): 2804-2816 (2021) - [j12]Zhixuan Wang
A 148-nW Reconfigurable Event-Driven Intelligent Wake-Up System for AIoT Nodes Using an Asynchronous Pulse-Based Feature Extractor and a Convolutional Neural Network. IEEE J. Solid State Circuits 56(11): 3274-3288 (2021) - [j11]Heyi Li
Energy-Efficient CMOS Humidity Sensors Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. IEEE J. Solid State Circuits 56(12): 3560-3572 (2021) - [j10]Zhixuan Wang
Ultra-Low-Power and Performance-Improved Logic Circuit Using Hybrid TFET-MOSFET Standard Cells Topologies and Optimized Digital Front-End Process. IEEE Trans. Circuits Syst. I Regul. Pap. 68(3): 1160-1170 (2021) - [j9]Zhixuan Wang
Re-Assessment of Steep-Slope Device Design From a Circuit-Level Perspective Using Novel Evaluation Criteria and Model-Less Method. IEEE Trans. Circuits Syst. I Regul. Pap. 68(4): 1624-1635 (2021) - [j8]Le Ye
The Challenges and Emerging Technologies for Low-Power Artificial Intelligence IoT Systems. IEEE Trans. Circuits Syst. I Regul. Pap. 68(12): 4821-4834 (2021) - [c19]Yibo Zhao, Huajun Zhang
A 94.1 dB DR 4.1 nW/Hz Bandwidth/Power Scalable DTDSM for IoT Sensing Applications Based on Swing-Enhanced Floating Inverter Amplifiers. CICC 2021: 1-2 - [c18]Yufei Ma, Gokul Krishnan, Yu Cao, Le Ye, Ru Huang:
SWIFT: Small-World-based Structural Pruning to Accelerate DNN Inference on FPGA. FPGA 2021: 148 - [c17]Heyi Li, Zhichao Tan, Yuanxin Bao, Han Xiao, Hao Zhang, Kaixuan Du, Yihan Zhang, Le Ye, Ru Huang:
5.1 A 1.5μW 0.135pJ·%RH2 CMOS Humidity Sensor Using Adaptive Range-Shift Zoom CDC and Power-Aware Floating Inverter Amplifier Array. ISSCC 2021: 72-74 - [c16]Zhixuan Wang
12.1 A 148nW General-Purpose Event-Driven Intelligent Wake-Up Chip for AIoT Devices Using Asynchronous Spike-Based Feature Extractor and Convolutional Neural Network. ISSCC 2021: 436-438 - 2020
- [j7]Zhiting Lin
Challenges and Solutions of the TFET Circuit Design. IEEE Trans. Circuits Syst. 67-I(12): 4918-4931 (2020) - [c15]Xiaolong Chen, Enbin Gong, Hao Zhang, Le Ye, Ru Huang:
A 1μW-to-158μW Output Power Pseudo Open-Loop Boost DC-DC with 86.7% Peak Efficiency using Frequency-Programmable Oscillator and Hybrid Zero Current Detection. ISCAS 2020: 1-4 - [c14]Enbin Gong, Hao Zhang, Xiaolong Chen, Le Ye, Ru Huang:
2.4-GHz 16-QAM Passive Backscatter Transmitter for Wireless Self-Power Chips in IoT. ISCAS 2020: 1-5 - [c13]Zhixuan Wang
20.2 A 57nW Software-Defined Always-On Wake-Up Chip for IoT Devices with Asynchronous Pipelined Event-Driven Architecture and Time-Shielding Level-Crossing ADC. ISSCC 2020: 314-316
2010 – 2019
- 2019
- [c12]Zhixuan Wang
Ultra-Low Power Hybrid TFET-MOSFET Topologies for Standard Logic Cells with Improved Comprehensive Performance. ISCAS 2019: 1-5 - 2018
- [c11]Libo Yang, Jiadi Zhu
Combinational Access Tunnel FET SRAM for Ultra-Low Power Applications. ISCAS 2018: 1-5 - 2017
- [j6]Yongan Zheng, Le Ye, Xiucheng Hao
A tunable transformer-based CMOS directional coupler for UHF RFID readers. IEICE Electron. Express 14(6): 20161261 (2017) - [c10]Lingyi Guo, Le Ye, Cheng Chen, Qianqian Huang, Libo Yang, Zhu Lv, Xia An, Ru Huang:
Benchmarking TFET from a circuit level perspective: Applications and guideline. ISCAS 2017: 1-4 - 2015
- [j5]Yixiao Wang, Le Ye, Huailin Liao, Ru Huang, Yangyuan Wang:
Highly Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 62-II(3): 296-300 (2015) - 2014
- [j4]Long Chen, Yixiao Wang, Chuan Wang, Jiayi Wang, Congyin Shi
A 4.2 mm2 72 mW Multistandard Direct-Conversion DTV Tuner in 65 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 280-292 (2014) - [c9]Ying Guo, Long Chen, Tao Xia, Le Ye, Xing Zhang, Huailin Liao:
A UHF RFID reader transmitter with digital CMOS power amplifier. ISCAS 2014: 702-705 - 2013
- [j3]Junhua Liu, Chen Li, Long Chen, Congyin Shi
A 65 mW fully integrated UHF-band CMMB tuner in 65 nm CMOS process. Sci. China Inf. Sci. 56(1): 1-5 (2013) - [j2]Le Ye, Congyin Shi
Highly Power-Efficient Active-RC Filters With Wide Bandwidth-Range Using Low-Gain Push-Pull Opamps. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(1): 95-107 (2013) - [c8]Yongan Zheng, Le Ye, Long Chen, Huailin Liao, Ru Huang:
SAW-less GNSS front-end amplifier with 80.4-dB GSM blocker suppression using CMOS directional coupler notch filter. ISCAS 2013: 749-752 - 2012
- [c7]Long Chen, Chuan Wang, Chen Li, Le Ye, Huailin Liao, Ru Huang:
A +21.2 dBm out-of-band IIP3 0.2-3GHz RF front-end using impedance translation technique. ISCAS 2012: 468-471 - [c6]Le Ye, Yixiao Wang, Long Chen, Huailin Liao, Ru Huang:
Widely reconfigurable 8th-order chebyshev analog baseband IC with proposed push-pull op-amp for Software-Defined Radio in 65nm CMOS. ISCAS 2012: 672-675 - [c5]Yixiao Wang, Le Ye, Huailin Liao, Ru Huang:
Cost-efficient CMOS RF tunable bandpass filter with active inductor-less biquads. ISCAS 2012: 2139-2142 - 2011
- [c4]Le Ye, Congyin Shi
A 0.47mW 6th-order 20MHz active filter using highly power-efficient Opamp. ISCAS 2011: 1640-1643 - [c3]Congyin Shi
-99dBc/Hz@10kHz 1MHz-step dual-loop integer-N PLL with anti-mislocking frequency calibration for global navigation satellite system receiver. ISCAS 2011: 1876-1879 - 2010
- [j1]Le Ye, Huailin Liao, Fei Song, Jiang Chen, Chen Li, Jinshu Zhao, Ruiqiang Liu, Chuan Wang, Congyin Shi
A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications. IEEE J. Solid State Circuits 45(7): 1316-1329 (2010) - [c2]Jinshu Zhao, Marcus Hellfeld, Thomas Wolf, Frank Ellinger, Le Ye:
A 17-tap 3.5 Gbps finite impulse response pulse shaping filter for 60 GHz transmitter with QPSK modulation. ESSCIRC 2010: 194-197
2000 – 2009
- 2009
- [c1]Le Ye, Huailin Liao, Fei Song, Jiang Chen, Congyin Shi
A single-chip CMOS UHF RFID Reader transceiver for mobile applications. ESSCIRC 2009: 228-231
Coauthor Index
[j25] [j24] [j23] [c51] [c50] [c49] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [j21] [j17] [c40] [c39] [c38] [c37] [c36] [c34] [c30] [c29] [c28] [c27] [c26] [c22] [c21] [j13] [j12] [j11] [j10] [j9] [j8] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [j5] [j3] [j2] [c8] [c7] [c6] [c5] [c4] [j1] [c1]
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