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3DIC 2010: Munich, Germany
- IEEE International Conference on 3D System Integration, 3DIC 2010, Munich, Germany, 16-18 November 2010. IEEE 2010, ISBN 978-1-4577-0526-7
- Montserrat Fernandez-Bolaños, Adrian M. Ionescu:
3D heterogeneous integration for novel functionality. 1-19 - Jeff Burns:
3D integration - A server perspective. 1-20 - Christophe Zinck:
3D integration infrastructure & market status. 1-34 - Kenzo Inagaki:
3D R&D technology for the future voyage in Japan. 1-42 - Christophe Zinck:
Keynote speakers day 1: 3D integration with TSV interconnects: Technology trends & market analysis. 1-2 - Dimitrios Velenis, Erik Jan Marinissen
, Eric Beyne
Cost effectiveness of 3D integration options. 1-6 - Lan Peng, Hongyu Li, Dau Fatt Lim, Riko I. Made, Guo-Qiang Lo, Dim-Lee Kwong, Chuan Seng Tan
Fine-pitch bump-less Cu-Cu bonding for wafer-on-wafer stacking and its quality enhancement. 1-5 - Vance Tyree:
3DIC multi-project-wafer program: A collaboration to provide fabrication access. 1-17 - Kholdoun Torki
Design platform and tools for 3D IC integration. 1-25 - Steve Lipa, Thorlindur Thorolfsson, Paul D. Franzon
The NCSU Tezzaron design kit. 1-15 - Grzegorz Deptuch
3DIC multi-project fabrication run being organized by CMC/CMP/MOSIS and Tezzaron. 1-10 - Valerio Re
3D ICs and pixel sensors: The Italian VIPIX project and the European AIDA WP3 project. 1-6 - Jean-François Pratte
High sensitivity fully digital photodetector. 1-9 - Weng Hong Teh, C. Deeb, J. Burggraf, D. Arazi, R. Young, C. Senowitz, A. Buxbaum:
Post-bond sub-500 nm alignment in 300 mm integrated face-to-face wafer-to-wafer Cu-Cu thermocompression, Si-Si fusion and oxideoxide fusion bonding. 1-6 - Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Design and early evaluation of a 3-D die stacked chip multi-vector processor. 1-8 - Harry Hedler, Thomas Scheiter, Markus Schieber, Armin Klumpp, Peter Ramm:
High performance 3D interconnects based on electrochemical etch and liquid metal fill. 1-7 - Erik Jan Marinissen
3D DfT architecture for pre-bond and post-bond testing. 1-8 - Thorlindur Thorolfsson, Guojie Luo, Jason Cong, Paul D. Franzon
Logic-on-logic 3D integration and placement. 1-4 - Paul D. Franzon
Thermal isolation in 3D chip stacks using vacuum gaps and capacitive or inductive communications. 1-4 - Mariappan Murugesan, Yuki Ohara, Jichoel Bea, Kang Wook Lee, Takafumi Fukushima
Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. 1-5 - Xiang Hu, Thomas Toms, Riko Radojcic, Matt Nowak, Nick Yu, Chung-Kuan Cheng:
Enabling power distribution network analysis flows for 3D ICs. 1-4 - Jason D. Reed, Scott H. Goodwin, Christopher Gregory, Dorota Temple:
Reliability testing of high aspect ratio through silicon vias fabricated with atomic layer deposition barrier, seed layer and direct plating and material properties characterization of electrografted insulator, barrier and seed layer for 3-D integration. 1-8 - Akihiro Noriki, Kang Wook Lee, Jichoel Bea, Takafumi Fukushima
Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. 1-4 - Takafumi Fukushima
Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. 1-5 - Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai:
3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. 1-4 - Fumihiro Inoue
All-wet fabrication technology for high aspect ratio TSV using electroless barrier and seed layers. 1-5 - Ladislav Andricek
Application of the SLID-ICV interconnection technology for the ATLAS pixel upgrade at SLHC. 1-4 - Kiyoto Ito
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 1-6 - Negin Golshani, Jaber Derakhshandeh, Ryoichi Ishihara, C. I. M. Beenakker, Michael Robertson, Thomas Morrison:
Monolithic 3D integration of SRAM and image sensor using two layers of single grain silicon. 1-4 - Matthias Gulbins, Fabian Hopsch, Peter Schneider
Developing digital test sequences for through-silicon vias within 3D structures. 1-6 - Dean Malta, Erik Vick, Scott H. Goodwin, Christopher Gregory, Matthew Lueck, Alan Huffman, Dorota Temple:
Fabrication of TSV-based silicon interposers. 1-6 - Young-Joon Lee, Sung Kyu Lim
Timing analysis and optimization for 3D stacked multi-core microprocessors. 1-7 - Rebha El Farhane, Myriam Assous, Patrick Leduc, Aurélie Thuaire
A successful implementation of dual damascene architecture to copper TSV for 3D high density applications. 1-4 - Tao Zhang, Kui Wang, Yi Feng, Yan Chen, Qun Li, Bing Shao, Jing Xie, Xiaodi Song, Lian Duan, Yuan Xie, Xu Cheng, Youn-Long Lin:
A 3D SoC design for H.264 application with on-chip DRAM stacking. 1-6 - Hanhua Qian, Xiwei Huang, Hao Yu, Chip-Hong Chang
Real-time thermal management of 3D multi-core system with fine-grained cooling control. 1-6 - Mayu Aoki, Kazuyuki Hozawa, Kenichi Takeda:
Wafer-level hybrid bonding technology with copper/polymer co-planarization. 1-4 - Kouji Kiyoyama, Kang Wook Lee, Takafumi Fukushima
A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. 1-4 - Yann Civale, Marcel Gonzalez, Deniz Sabuncuoglu Tezcan, Youssef Travaly, Philippe Soussan, Eric Beyne
A novel concept for ultra-low capacitance via-last TSV. 1-4 - Grzegorz Deptuch
Pixel detectors in 3D technologies for high energy physics. 1-4 - Gregory Riou, Gweltaz Gaudin, Didier Landru, Catherine Tempesta, Ionut Radu
Pre bonding metrology solutions for 3D integration. 1-5 - Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila
CMIT - A novel cluster-based topology for 3D stacked architectures. 1-5 - Yusuke Funaya, Ryusuke Egawa, Hiroyuki Takizawa
Cache partitioning strategies for 3-D stacked vector processors. 1-6 - Ionut Radu
Recent Developments of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. 1-6 - Sangwook Han, David D. Wentzloff:
Wireless power transfer using resonant inductive coupling for 3D integrated ICs. 1-5 - Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai:
A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems. 1-4 - Nicolas Lietaer, Anand Summanwar, Thor Bakke, Maaike Taklo, Per Dalsjø:
TSV development for miniaturized MEMS acceleration switch. 1-4 - Naoto Miyamoto, Yohei Matsumoto, Hanpei Koike, Tadayuki Matsumura, Kenichi Osada, Yaoko Nakagawa, Tadahiro Ohmi:
Development of a CAD tool for 3D-FPGAs. 1-6 - Mauro Scandiuzzo, Roberto Cardu, Salvatore Cani, Simone Spolzino, Luca Perugini, Eleonora Franchi, Roberto Canegallo, Roberto Guerrieri:
3D system on chip memory interface based on modeled capacitive coupling interconnections. 1-4 - Akihiro Horibe, Kuniaki Sueoka, Katsuyuki Sakuma
High density 3D integration by pre-applied Inter Chip Fill. 1-5 - Moongon Jung, Sung Kyu Lim
A study of IR-drop noise issues in 3D ICs with through-silicon-vias. 1-7 - Cheng-Ta Ko, Kuan-Neng Chen
Wafer-level 3D integration using hybrid bonding. 1-4 - Manuel Suarez, Víctor M. Brea
In-pixel ADC for a vision architecture on CMOS-3D technology. 1-7 - Shashikanth Bobba, Ashutosh Chakraborty, Olivier Thomas, Perrine Batude, Vasilis F. Pavlidis, Giovanni De Micheli:
Performance analysis of 3-D monolithic integrated circuits. 1-4 - Jing Xie, Xiangyu Dong, Yuan Xie:
3D memory stacking for fast checkpointing/restore applications. 1-6 - Nauman H. Khan, Sherief Reda, Soha Hassoun:
Early estimation of TSV area for power delivery in 3-D integrated circuits. 1-6 - Anne Jourdain, Thibault Buisson, Alain Phommahaxay, Mark Privett, Dan Wallace, Sumant Sood, Peter Bisson, Eric Beyne
300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications. 1-4 - Robert Wieland, Kai Zoschke, Nils Jurgensen, Karl-Reinhard Merkel, Lars Nebrich
Silicon-interposer with high density Cu-filled TSVs. 1-4 - Chuichi Miyazaki, Haruo Shimamoto, Toshihide Uematsu, Yoshiyuki Abe, Kosuke Kitaichi, Tadahiro Morifuji, Shoji Yasunaga:
Development of high accuracy wafer thinning and pickup technology for thin wafer. 1-4 - Gweltaz Gaudin, Gregory Riou, Didier Landru, Catherine Tempesta, Ionut Radu
Low temperature direct wafer to wafer bonding for 3D integration: Direct bonding, surface preparation, wafer-to-wafer alignment. 1-4 - D. Le Cunff, A. Pravdivtsev, K. Le Chao, C. Euvrard, Emilie Deloffre, A. Cailean:
Use of optical metrology for wafer level packaging of CMOS image sensor. 1-6 - Peter Schneider
Integration of multi physics modeling of 3D stacks into modern 3D data structures. 1-6 - Pratyush Singh, R. Sankar, Xiang Hu, Weize Xie, Aveek Sarkar, Thomas Toms:
Power delivery network design and optimization for 3D stacked die designs. 1-6 - Robert Fischbach
Solution space investigation and comparison of modern data structures for heterogeneous 3D designs. 1-8 - Zheng Xu, Adam Beece, Dingyou Zhang, Qianwen Chen, Kuan-Neng Chen
Crosstalk evaluation, suppression and modeling in 3D through-strata-via (TSV) network. 1-8 - Markus Gabriel, Thomas Knauer, Peter Bisson, Sumant Sood, Wilfried Bair, Jim Hermanowski:
Equipment challenges and solutions for diverse temporary bonding and de-bonding processes in 3D integration. 1-5 - Gerrit Oosterhuis, Bert Huis in 't Veld, Gerald Ebberink, Daniël Arnaldo del Cerro, Edwin van den Eijnden, Peter Chall, Ben van der Zon:
Additive interconnect fabrication by picosecond Laser Induced Forward Transfer. 1-5
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