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Makoto Saen
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2010 – 2019
- 2017
- [j3]Makoto Saen, Tadanobu Toba, Yusuke Kanno:
Soft-Error-Tolerant Dual-Modular-Redundancy Architecture with Repair and Retry Scheme for Memory-Control Circuit on FPGA. IEICE Trans. Electron. 100-C(4): 382-390 (2017) - 2012
- [c6]Kiyoto Ito
, Makoto Saen, Kenichi Osada:
Scalable robotic-hand control system based on a hierarchical multi-processor architecture adopting a large number of tactile sensors. IROS 2012: 14-19 - 2010
- [j2]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [j1]Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi:
A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS. IEEE J. Solid State Circuits 45(11): 2312-2320 (2010) - [c5]Kiyoto Ito
Hierarchical 3D interconnection architecture with tightly-coupled processor-memory integration. 3DIC 2010: 1-6
2000 – 2009
- 2009
- [c4]Kiichi Niitsu
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2007
- [c3]Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie:
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. ISSCC 2007: 296-604 - 2005
- [c2]Makoto Saen, Hiroshi Ueda, Masaru Hase, Eiji Yamamoto, Yoshihiro Mori, Hiroshi Hatae, Yuki Kondo, Seiji Miura, Itaru Nonomura, Naohiko Irie, Hiromi Watanabe:
Elastic shared resource scheduling SOC interconnect architecture for real-time system. CICC 2005: 787-790 - 2004
- [c1]Makoto Saen, Motohiro Nakagawa, Junichi Nishimoto, Tomoyuki Kodama, Fumio Arakawa:
Transparent SOC: on-chip analyzing techniques and implementation for embedded processor. SoCC 2004: 51-54
Coauthor Index
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