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VTS 2015: Napa, CA, USA
- 33rd IEEE VLSI Test Symposium, VTS 2015, Napa, CA, USA, April 27-29, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-7597-6
- Claude Thibeault:
Foreword. 1 - Yankin Tanurhan:
Keynote address: New opportunities in the internet of things. 1 - Kai Hu, Bhargab B. Bhattacharya, Krishnendu Chakrabarty
:
Fault diagnosis for flow-based microfluidic biochips. 1-6 - Christopher Jaress, Philip Brisk
Rapid online fault recovery for cyber-physical digital microfluidic biochips. 1-6 - Yong-Xiao Chen, Jin-Fu Li:
Fault modeling and testing of 1T1R memristor memories. 1-6 - Li Xu, Yan Duan, Degang Chen:
A low cost jitter separation and characterization method. 1-5 - Tao Chen
Ultrafast stimulus error removal algorithm for ADC linearity test. 1-5 - Navankur Beohar, Priyanka Bakliwal, Sidhanto Roy, Debashis Mandal, Philippe Adell, Bert Vermeire, Bertan Bakkaloglu
Disturbance-free BIST for loop characterization of DC-DC buck converters. 1-6 - Paul Tracey:
Innovative practices session 1C: New technologies, new challenges - 1 [3 presentations]. 1 - Hsunwei Hsiung, Sandeep K. Gupta:
A multi-layered methodology for defect-tolerance of datapath modules in processors. 1-6 - Da Cheng, Sandeep K. Gupta:
PPB: Partially-working processors binning for maximizing wafer utilization. 1-6 - Shahrzad Mirkhani, Balavinayagam Samynathan, Jacob A. Abraham:
In-depth soft error vulnerability analysis using synthetic benchmarks. 1-6 - Sk Subidh Ali
TMO: A new class of attack on cipher misusing test infrastructure. 1-4 - Jennifer Dworak, Al Crouch:
A call to action: Securing IEEE 1687 and the need for an IEEE test Security Standard. 1-4 - Doohwang Chang, Bertan Bakkaloglu
Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance. 1-4 - Suraj Sindia:
Innovative practices session 2C: New technologies, new challenges - 2. 1 - Sreekumar Vadakke Kodakara, Mehul V. Sagar, Joel Yuen:
Extracting effective functional tests from commercial programs. 1-6 - Harry H. Chen, Shih-Hua Kuo, Jonathan Tung, Mango Chia-Tso Chao:
Statistical techniques for predicting system-level failure using stress-test data. 1-6 - Ali Ahmadi, Ke Huang, Amit Nahar, Bob Orr, Michael Pas, John M. Carulli, Yiorgos Makris
Yield prognosis for fab-to-fab product migration. 1-6 - Dominique Drouin, Mohamed Amine-Bounouar, Gabriel Droulers
3D microelectronic with BEOL compatible devices. 1 - Mike Ricchetti:
Innovative practices session 3C: Advances in silicon debug & diagnosis. 1 - Valeria Bertacco:
Panel: When will the cost of dependability end innovation in computer design? 1 - Manuel J. Barragán, Gildas Léger
Special session: Hot topics: Statistical test methods. 1-2 - Ran Wang, Guoliang Li, Rui Li, Jun Qian, Krishnendu Chakrabarty
ExTest scheduling for 2.5D system-on-chip integrated circuits. 1-6 - Chang Hao, Huaguo Liang:
Pulse shrinkage based pre-bond through silicon vias test in 3D IC. 1-6 - Rajit Karmakar, Aditya Agarwal, Santanu Chattopadhyay:
Testing of 3D-stacked ICs with hard- and soft-dies - a Particle Swarm Optimization based approach. 1-6 - Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
Improving diagnosis resolution of a fault detection test set. 1-6 - Irith Pomeranz:
Improving the accuracy of defect diagnosis by considering reduced diagnostic information. 1-6 - Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Signature oriented model pruning to facilitate multi-threaded processors debugging. 1-6 - M. Enamul Amyeen:
Innovative practices session 5C: Advancements in test -keeping moore moving! 1 - Kohki Taniguchi, Noriyuki Miura, Taisuke Hayashi, Makoto Nagata
At-Product-Test Dedicated Adaptive supply-resonance suppression. 1-6 - Xian Wang, Debashis Banerjee, Abhijit Chatterjee:
Low cost high frequency signal synthesis: Application to RF channel interference testing. 1-6 - Anthony Coyette, Baris Esen, Ronny Vanhooren, Wim Dobbelaere, Georges G. E. Gielen
Automated testing of mixed-signal integrated circuits by topology modification. 1-6 - Gurgen Harutyunyan, Grigor Tshagharyan, Yervant Zorian:
Impact of parameter variations on FinFET faults. 1-4 - Michael Nicolaidis, Panagiota Papavramidou:
Memory repair for high defect densities. 1-4 - Richun Fei, Jocelyn Moreau, Salvador Mir, Alexis Marcellin, C. Mandier, E. Huss, G. Palmigiani, P. Vitrou, Thomas Droniou:
Horizontal-FPN fault coverage improvement in production test of CMOS imagers. 1-6 - Ashkan Eghbal, Pooria M. Yaghini, Nader Bagherzadeh
Capacitive Coupling Mitigation for TSV-based 3D ICs. 1-6 - Xuanle Ren, Mitchell Martin, Ronald D. Blanton:
Improving accuracy of on-chip diagnosis via incremental learning. 1-6 - Rob Aitken, Ethan H. Cannon, Mondira Pant, Mehdi Baradaran Tahoori:
Resiliency challenges in sub-10nm technologies. 1-4 - Suriya Natarajan:
Innovative practices session 7C: Mixed signal test and debug. 1 - Sule Ozev, Linda Milor
Panel: Analog/RF BIST: Are we there yet? 1 - Erik Larsson
No Fault Found: The root cause. 1 - Michele Portolan
Special session 8C: E.J. McCluskey doctoral thesis award semi-final. 1-2 - Kelson Gent, Michael S. Hsiao:
Abstraction-based relation mining for functional test generation. 1-6 - Hao-Yu Yang, Shih-Hua Kuo, Tzu-Hsuan Huang, Chi-Hung Chen, Chris Lin, Mango Chia-Tso Chao:
Random pattern generation for post-silicon validation of DDR3 SDRAM. 1-6 - Reza Sharafinejad, Bijan Alizadeh, Masahiro Fujita:
UPF-based formal verification of low power techniques in modern processors. 1-6 - Woongrae Kim, Chang-Chih Chen, Soonyoung Cha, Linda Milor
MBIST and statistical hypothesis test for time dependent dielectric breakdowns due to GOBD vs. BTDDB in an SRAM array. 1-6 - Andres F. Gomez, Leticia B. Poehls, Fabian Vargas, Víctor H. Champac:
An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging. 1-6 - Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Halil Kukner, Pieter Weckx, Praveen Raghavan, Francky Catthoor:
Integral impact of BTI and voltage temperature variation on SRAM sense amplifier. 1-6 - Mehdi Sadi, LeRoy Winemberg, Mark M. Tehranipoor:
A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs. 1-6 - Sushmita Kadiyala Rao, Bharath Shivashankar, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Scalability study of PSANDE: Power supply analysis for noise and delay estimation. 1-6 - Fengchao Zhang, Andrew Hennessy, Swarup Bhunia
Robust counterfeit PCB detection exploiting intrinsic trace impedance variations. 1-6 - Nathan DeBardeleben, Sean Blanchard, David R. Kaeli, Paolo Rech
Field, experimental, and analytical data on large-scale HPC systems and evaluation of the implications for exascale system design. 1-2 - Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker
Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. 1-6 - Irith Pomeranz:
Test vector omission with minimal sets of simulated faults. 1-6 - Irith Pomeranz:
Test compaction by test cube merging for four-way bridging faults. 1-6 - Rob Aitken:
Panel: Is design-for-security the new DFT? 1 - Janusz Rajski, Nilanjan Mukherjee:
Innovative practices session 11C: Advanced scan methodologies [3 presentations]. 1 - Chao Han, Adit D. Singh:
Testing cross wire opens within complex gates. 1-6 - Irith Pomeranz:
A definition of the number of detections for faults with single tests in a compact scan-based test set. 1-6 - Ben Niewenhuis, Ronald D. Blanton:
Efficient built-in self test of regular logic characterization vehicles. 1-6 - Sreekumar V. Kodakara, Suriya Natarajan:
Special session 12B: Panel: IOT - Reliable? Secure? Or death by a billion cuts? 1
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