default search action
ISIC 2014: Singapore
- 2014 International Symposium on Integrated Circuits (ISIC), Singapore, December 10-12, 2014. IEEE 2014, ISBN 978-1-4799-4833-8
- Chia-Lun Chang, Tai-Cheng Lee:
A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability. 1-4 - Wen-Yaw Chung, Pei-Shan Yu, Angelito A. Silverio
:
A maximum power point tracking and voltage regulated dual-chip system for single-cell photovoltaic energy harvesting. 5-8 - Yuen-Haw Chang, Yu-Jhang Chen:
Modeling and implementation of high-gain switched-inductor switched-capacitor converter. 9-12 - Hendika Fatkhi Nurhuda, Yongkui Yang, Wang Ling Goh:
A three-topology based, wide input range switched-capacitor DC-DC converter with low-ripple and enhanced load line regulations. 13-16 - Zhekai Xiao, Chiang Liang Kok
Triple boundary multiphase with predictive interleaving technique for switched capacitor DC-DC converter regulation. 17-20 - Robert Specht
Investigating measurement methods for high-resolution electromagnetic field side-channel analysis. 21-24 - Benedikt Heinz, Johann Heyszl, Frederic Stumpf:
Side-channel analysis of a high-throughput AES peripheral with countermeasures. 25-29 - Marc Stöttinger
Zero collision attack and its countermeasures on Residue Number System multipliers. 30-33 - Alexander Herrmann, Marc Stöttinger
Constructive side-channel analysis for secure hardware design. 34-37 - Dirmanto Jap, Jakub Breier
Overview of machine learning based side-channel analysis methods. 38-41 - Amin Ojani, Behzad Mesgarzadeh, Atila Alvandpour:
A low-power direct IQ upconversion technique based on duty-cycled multi-phase sub-harmonic passive mixers for UWB transmitters. 42-45 - Ameya Bhide, Atila Alvandpour:
Timing challenges in high-speed interleaved ΔΣ DACs. 46-49 - Markus Törmänen:
mm-Wave pulse-generation circuits in 65nm CMOS. 50-53 - Therese Forsberg, Henrik Sjöland
A 65 nm CMOS varactorless mm-wave VCO. 54-57 - Tobias Tired, Henrik Sjöland
A 28 GHz SiGe QVCO with an I/Q phase error detector for an 81-86 GHz E-band transceiver. 58-61 - David Lin, Subhasish Mitra:
QED post-silicon validation and debug: Invited abstract. 62 - Tulika Mitra
Energy-efficient computing with heterogeneous multi-cores. 63-66 - Yu Pan, Santhosh Kumar Pilakkat, Kay-Chuan Benny Tan, Wai-Meng Mok:
A user's reflections on the art of high level synthesis. 67-70 - Wei Zuo, Hongbin Zheng, Swathi T. Gurumani, Kyle Rupnow
New solutions for system-level and high-level synthesis (Invited paper). 71-74 - Pyoungwon Park, Dipankar Nag, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu:
Digital compensation method for the path delay mismatches in GRO-TDC. 75-78 - Younghoon Kim, Min-Ki Jeon, Changsik Yoo:
Digital phase locked loop (DPLL) with offset dithered bang-bang phase detector (BBPD) for bandwidth control. 79-82 - Kun Ao, Yajuan He, Liang Li, Yuxin Wang, Qiang Li:
A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. 83-86 - Felix Lang, Markus Grozing
Design of a 4 GS/s radix-1.75 single channel pipeline ADC in 28 nm CMOS technology with foreground calibration. 87-90 - Qiang Li, Jing Wang, Yasuaki Inoue:
A high efficiency CMOS rectifier with ON-OFF response compensation for wireless power transfer in biomedical applications. 91-94 - Amir Zjajo, Nick van der Meijs, Rene van Leuken:
Statistical power optimization of deep-submicron digital CMOS circuits based on structured perceptron. 95-98 - Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria:
Vt-conscious repeater insertion in power-managed VLSI. 99-102 - Mengyang Li, Aijiao Cui, Tingting Yu:
An improved scan cell ordering method using the scan cells with complementary outputs. 103-106 - Hanjoo Cho, Young Hwan Kim:
Ray-casting algorithm and its considerations for parallel processing optimization techniques for parallel ray-casting algorithm. 107-110 - Aiwu Ruan, Wei Tian, Bo Ni, Ke Wu:
A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA. 111-114 - Xin Li, Ronald Shawn Blanton, Pulkit Grover
Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. 115-118 - Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu
SLIC: Statistical learning in chip. 119-123 - Hai Li
Neuromorphic hardware acceleration enabled by emerging technologies (Invited paper). 124-127 - Subhrajit Roy, Sougata Kumar Kar, Arindam Basu
Architectural exploration for on-chip, online learning in spiking neural networks. 128-131 - Yiqun Wei, Xinnan Lin:
An improved SPICE model of phase-change memory (PCM) for peripheral circuits simulation and design. 132-135 - Michael Pehl, Akshara Ranjit Punnakkal, Matthias Hiller
Advanced performance metrics for Physical Unclonable Functions. 136-139 - Stefan Gehrer
Reconfigurable PUFs for FPGA-based SoCs. 140-143 - Cesare Alippi, Andrey Bogdanov
Lightweight cryptography for constrained devices. 144-147 - Florian Wilde, Matthias Hiller
Statistic-based security analysis of ring oscillator PUFs. 148-151 - Jakub Breier
A survey of the state-of-the-art fault attacks. 152-155 - Jin He, Yong-Zhong Xiong, Jian Kang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue Ping Zhang:
A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applications. 156-159 - Taufiq Alif Kurniawan
A 2.5-GHz band low-voltage high efficiency class-E power amplifier IC with body effect. 160-163 - Ting Guo, Zhiqun Li, Qin Li, Zhigong Wang:
A 20.5GHz wide-band programmable divide-by-N frequency divider. 164-167 - Jongsuk Lee, Yong Moon, Taewon Ahn:
A dual-band VCO using inductor splitting for automotive radar system at W-band. 168-171 - Mario Garrido
Challenging the limits of FFT performance on FPGAs (Invited paper). 172-175 - Chiou-Yng Lee, Pramod Kumar Meher, Wen-Yo Lee:
Subquadratic space complexity digit-serial multiplier over binary extension fields using Toom-Cook algorithm. 176-179 - Shen-Jui Huang, Sau-Gee Chen:
A new memoryless and low-latency FFT rotator architecture. 180-183 - Ying-Liang Chen, Terng-Yin Hsu:
Cost-efficiency FFT using hardware-reduction and dynamic current scaling approaches. 184-187 - Tso-Bing Juang, Yu-Ming Chiu:
Fast binary to BCD converters for decimal communications using new recoding circuits. 188-191 - Dongying Liang, Yan Xiao, Yongqiang Feng, Yonghong Yan:
The role of auditory feedback in speech production: Implications for speech perception in the hearing impaired. 192-195 - Kostas Kokkinakis, Yi Hu, Dongying Liang:
An efficient spectral subtraction-based strategy for suppressing reverberation in cochlear implant devices. 196-199 - Qudsia Tahmina, Fei Chen
Perceptual contribution of vowels and consonants to sentence intelligibility by cochlear implant users. 200-203 - Ying-Hui Lai, Fei Chen
Effect of adaptive envelope compression in simulated electric hearing in reverberation. 204-207 - Wing Oi Siu, Terrence S. T. Mak:
Intra- and inter-chip voltage droop analysis using a power delivery grid model. 208-211 - Wangchen Dai
Time-efficient computation of digit serial Montgomery multiplication. 212-215 - Jun Wei Chuah:
The Internet of Things: An overview and new perspectives in systems design. 216-219 - Qiang Wu, Yajun Ha, Akash Kumar, Shaobo Luo, Ang Li, Shihab Mohamed:
A heterogeneous platform with GPU and FPGA for power efficient high performance computing. 220-223 - Yingnan Cui, Wei Zhang
Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme. 224-227 - Dong Wang
A low-distortion R-active-C lowpass filter for linear sensor applications. 228-231 - Uday Dasgupta, Geok Teng Ong, Junmin Cao, Soong Lin Chew:
A versatile three-stage operational amplifier with Second-stage Bypass Compensation. 232-235 - Zhelu Li
A primary side feedback control for flyback LED driver with no output voltage feedback resistors. 236-239 - Yejin Chen, Goh Wang Ling, Jun Yu, Muthukumaraswamy Annamalai Arasu:
An SOI-CMOS low noise chopper amplifier for high temperature applications. 240-243 - Chunfeng Bai, Jianhui Wu:
A 66dB continuous gain adjusting CMOS AGC amplifier with both feedforward and feedback loop. 244-247 - Philip Davis, Charles D. Creusere, Wei Tang:
ASIC implementation of the cross frequency coupling algorithm for EEG signal processing. 248-251 - Xiangyu Zhang, Shoushun Chen:
A second-generation noise-immune motion detection image sensor for moving object tracking application. 252-255 - Dan Yang, Guoyi Yu, Xuecheng Zou, Yelei Deng, Jianfu Zhong:
The design and verification of a novel LDPC decoder with high-efficiency. 256-259 - Tongqiang Gao, Xiaodong Xu, Hongfeng Zhang, Haigang Yang:
A highly-integrated wireless configuration circuit for FPGA chip. 260-263 - Lin Biao Wang, Kye Yak See
Power distribution network design for high-speed automotive graphical processing module. 264-267 - Tianqi Tang, Rong Luo, Boxun Li, Hai Li, Yu Wang
Energy efficient spiking neural network design with RRAM devices. 268-271 - Will X. Y. Li, Yao Xin, Dong Song
VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel. 272-275 - Junwen Luo, Graeme Coapes
A real-time silicon cerebellum spiking neural model based on FPGA. 276-279 - Peng Chen, Chao Wang, Xi Li, Xuehai Zhou, Aili Wang, Ray C. C. Cheung
Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner. 280-283 - Yangyang Ma, Shengqi Yang, Zhangqin Huang, Yibin Hou, Leqiang Cui, Dongfang Yang:
Hierarchical air quality monitoring system design. 284-287 - Yihu Li, Yong-Zhong Xiong, Goh Wang-Ling:
A 330 GHz frequency modulator using 0.13-μm SiGe HBTs. 288-291 - Shunli Ma, Junyan Ren, Hao Yu:
An overview of new design techniques for high performance CMOS millimeter-wave circuits. 292-295 - Jin He, Yong-Zhong Xiong, Jiankang Li, Debin Hou, Sanming Hu, Dan Lei Yan, Muthukumaraswamy Annamalai Arasu, Yue Ping Zhang:
A fully integrated 166-GHz frequency synthesizer in 0.13-μm SiGe BiCMOS for D-band applications. 296-299 - Xiaodong Deng, Yihu Li, Jiankang Li, Wen Wu, Yong-Zhong Xiong:
A 340 GHz fully integrated transmitter for high-speed communications. 300-303 - Chao Liu, Qiang Li, Yong-Zhong Xiong:
A compact Ka-band SPDT switch with high isolation. 304-307 - Jiang Luo, Jin He, Hao Wang, Sheng Chang, Qijun Huang, Yong-Zhong Xiong:
A 150-GHz push-push VCO in 0.13-μm SiGe BiCMOS. 308-311 - Shairfe Muhammad Salahuddin, Volkan Kursun
High-speed and low-leakage FinFET SRAM cell with enhanced read and write voltage margins. 312-315 - Shinobu Fujita, Hiroki Noguchi, Kazutaka Ikegami, Susumu Takeda, Kumiko Nomura, Keiko Abe:
Novel STT-MRAM-based last level caches for high performance processors using normally-off architectures. 316-319 - Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation. 320-323 - Yuejun Zhang
Design of threshold dominant delay Physical Unclonable Functions in 65nm CMOS. 324-327 - Chen-Bo Hsu, James B. Kuo:
MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits. 328-331 - Hitoshi Oi
Case study: Effectiveness of dynamic frequency scaling on server workload. 332-335 - Karthik Ganesan, Yao-Min Chen, Xiaochen Pan:
Scaling Java Virtual Machine on a many-core system. 336-339 - Joana Côrte-Real, Inês de Castro Dutra
A hybrid mapreduce model for prolog. 340-343 - Lijun Zhou, Zhiyi Yu, Jie Lin, Shikai Zhu, Weijing Shi, Haijie Zhou, Kunpeng Song, Xiaoyang Zeng:
Acceleration of Naive-Bayes algorithm on multicore processor for massive text classification. 344-347 - Ricardo Isidro Ramirez, Erika Hernandez Rubio
Differences of energetic consumption between Java and JNI Android apps. 348-351 - Daniel T. Grissom, Jeffrey McDaniel, Philip Brisk
Performance and cost analysis of NoC-inspired virtual topologies for digital microfluidic biochips. 352-355 - Mirela Alistar
Online synthesis for operation execution time variability on digital microfluidic biochips. 356-359 - Sudip Roy, Chi-Ruo Wu, Tsung-Yi Ho
Recent trends in chip-level design automation for digital microfluidic biochips. 360-363 - Juinn-Dar Huang
Sample preparation for droplet-based microfluidics. 364-367 - Nirmala Ramakrishnan, Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan:
Mask-based non-maximal suppression with iterative pruning for low-complexity corner detection. 368-371 - Meiqing Wu, Siew Kei Lam, Thambipillai Srikanthan, Tushar Shah:
Vision-based pedestrian tracking system using color and motion cue. 372-375 - Supriya Sathyanarayana, Ravi Kumar Satzoda, Suchitra Sathyanarayana, Thambipillai Srikanthan:
Reducing computational complexity for face detection. 376-379 - Philipp Wehner, Fynn Schwiegelshohn, Diana Göhringer, Michael Hübner:
Development of driver assistance systems using virtual hardware-in-the-loop. 380-383 - Natarajan Sudha, K. Sridharan, Dan Wilkinson:
A pipelined architecture for motion tracking on a multicore environment. 384-387 - Suyan Fan, Man-Kay Law, Pui-In Mak
A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout. 388-391 - Yuan Cao, Siarhei S. Zalivaka, Le Zhang, Chip-Hong Chang
CMOS image sensor based physical unclonable function for smart phone security applications. 392-395 - Leo John Chemmanda, Colin Chue Jianrong, Ravinder Pal Singh, Yalon Roterman:
ASIC front-end for sensing MEMS-mirror position. 396-399 - Di Zhu, Jiacheng Wang, Liter Siek
High accuracy time-mode duty-cycle-modulation-based temperature sensor for energy efficient system applications. 400-403 - Dipankar Nag, Kevin Tshun Chuan Chai:
High performance ΣΔ closed loop accelerometer. 404-407 - Seong-Jin Kim, Simon Sheung Yan Ng, David Wee, Yoon Hwee Leow, Fan-Yung Ma, Sie Boo Chiang:
High accuracy remote temperature sensor based on BJT devices in 0.13-μm CMOS. 408-411 - D. H. Lung, S. K. Hu, James B. Kuo, D. Chen, Y. J. Chen:
Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device. 412-415 - Benjamin Rebuffat, Pascal Masson, Jean-Luc Ogier, Marc Mantelli, Romain Laffont:
Effect of AC stress on oxide TDDB and trapped charge in interface states. 416-419 - Chana Leepattarapongpan, Toempong Phetchakul, Puttapon Pengpad, Arckom Srihapat, Wutthinan Jeamsaksiri
The increase sensitivity of PNP-magnetotransistor in CMOS technology. 420-423 - Yong Wang, Bo Chen, Supeng Liu, Liheng Lou, Kai Tang, Ying Zhang, Yuanjin Zheng:
Analysis and modelling on CMOS spiral inductor with impact of metal dummy fills. 424-427 - Bo Chen, Liheng Lou, Supeng Liu, Kai Tang, Yong Wang, Jianjun Gao, Yuanjin Zheng:
A semi-analytical extraction method for transformer model. 428-431 - Pedro Miguens Matutino
ROM-less RNS-to-binary converter moduli {22n - 1, 22n + 1, 2n - 3, 2n + 3}. 432-435 - Pietro Albicocco
Twenty years of research on RNS for DSP: Lessons learned and future perspectives. 436-439 - Jean-Claude Bajard
Babaï round-off CVP method in RNS: Application to lattice based cryptographic protocols. 440-443 - Amir Sabbagh Molahosseini
Rethinking reverse converter design: From algorithms to hardware components. 444-447 - Yinan Kong, Azadeh Safari, Cheeckottu Vayalil Niras:
A low-cost architecture for DWT filter banks in RNS applications. 448-451 - Shang Ma, Chenhao Wang, Jianhao Hu, Hongyan Chen:
ECRT: An extension of CRT based on weight pre-assignment. 452-455 - Peter Waszecki, Florian Sagstetter, Martin Lukasiewycz, Samarjit Chakraborty
Diagnosis-aware system design for automotive E/E architectures. 456-459 - Daniel Mueller-Gritschneder
System C-based multi-level error injection for the evaluation of fault-tolerant systems. 460-463 - Dip Goswami, Daniel Mueller-Gritschneder
Fault-tolerant embedded control systems for unreliable hardware. 464-467 - Martin Lukasiewycz, Shanker Shreejith
System simulation and optimization using reconfigurable hardware. 468-471 - Hou Zhao Qi Rex, Jong Ching Chuen, Andreas Herkersdorf:
Apps-usage driven energy management for multicore mobile computing systems. 472-475 - Quoc-Tai Duong, Atila Alvandpour:
Low noise linear and wideband transconductance amplifier design for current-mode frontend. 476-479 - Salma Nashit, Victor Adrian, Cui Keer, Quoc-An Mai, Bah-Hwee Gwee
A self-oscillating class D audio amplifier with dual voltage and current feedback. 480-483 - Jun Yu, Muthukumaraswamy Annamalai Arasu:
Transducer driver with active bootstrap switch. 484-487 - Tian-Shun Ng, Yin Sun, Victor Adrian, Bah-Hwee Gwee
Design of an output stage for high switching frequency DC-DC converters. 488-491 - Yajuan He, Song Wang, Qi Ling, Qiang Li:
A digital calibration technique for multi-bit-per-stage pipelined ADC. 492-495 - Jae-Yoon Bae, Hyeon-Cheon Seol, Young-Cheon Kwon, Seong-Kwan Hong, Oh-Kyong Kwon, Seong-Hwan Hwang, Seung-Tae Kim:
A small area 10-bit linear gamma DAC with voltage adder for large-sized active matrix flat panel displays. 496-499 - Hengzhou Yuan, Yang Guo, Zhuo Ma:
A 40nm/65nm process adaptive low jitter phase-locked loop. 500-503 - Seunghyun Im, Changho Seok, Hyunho Kim, Haryong Song, Hyoungho Ko
A versatile biopotential acquisition analog front end IC with effective DC offset and ripple rejection. 504-507 - Hillary Siewobr, Kazeem Alagbe Gbolagade
An efficient residue-to-binary converter for the new moduli set {2n/2 ± 1, 22n+1, 2n + 1}. 508-511 - Yee Hui Lee, Mohamed Khalil Hani, Muhammad N. Marsono
FPGA-based quantum circuit emulation: A case study on Quantum Fourier transform. 512-515 - Bin Zhao, Hongbao Zhang, LayKeng Lim, Xin Liu, M. Kumarasamy Raja:
Low-power multi-function multi-mode baseband design for low data rate applications. 516-519 - Xinyuan Qian, Hang Yu, Shoushun Chen, Kay Soon Low
Design and characterization of radiation-tolerant CMOS 4T Active Pixel Sensors. 520-523 - Fei Lyu
A more accurate circuit model for CMOS Hall cross with non-linear resistors and JFETs. 524-527 - Wen-Yaw Chung, Angelito A. Silverio
An amperometric sensor readout circuit for multiple electrochemical sensor cells. 528-531 - Wen-Yaw Chung, Angelito A. Silverio
A novel amperometric sensor readout based on charge measurement by current integration. 532-535 - Anak Agung Alit Apriyana, Yue-Ping Zhang:
DC - 15 GHz CMOS SP8T switches using defected ground structure low pass filter. 536-539 - Wei Yi Lim, M. Annamalai Arasu, M. Kumarasamy Raja:
Modeling of two port center-tapped to ground and three port scalable symmetrical inductor. 540-543 - Zhi-xiong Ren, Ke-feng Zhang, Lan-qi Liu, Cong Li, Xiaofei Chen, Dongsheng Liu, Zhenglin Liu, Xuecheng Zou:
A +33dBm 1.9 GHz linear CMOS power amplifier with MOS-level linearizers. 544-547 - Liheng Lou, Supeng Liu, Bo Chen, Kai Tang, Yong Wang, Yuanjin Zheng:
A broadband CMOS LC voltage-controlled oscillator for FMCW synthesizer. 548-551 - Dawei Li, Dongsheng Liu, Xuecheng Zou, Zilong Liu, Lun Li:
A low power injection-locked divider for body sensor network. 552-555 - Dan Lei Yan, Zhao Bin, Atshushi Tamura, M. Kumarasamy Raja:
A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOS. 556-559 - Subramanian Shiva Shankar, Pinxing Lin, Andreas Herkersdorf:
Deep packet inspection in residential gateways and routers: Issues and challenges. 560-563 - Angelina A. Silverio, Angelito A. Silverio, Joseph Demferlee Tatel:
Development of a variable frequency impedance measuring system. 564-567 - Kiat Seng Yeo
Internet of Things: Trends, challenges and applications. 568-571 - Felis Dwiyasa, Meng-Hiot Lim:
Zone classification for low-power active RFID tags. 572-575 - Zhou Jin, Xiao Wu, Yasuaki Inoue, Dan Niu:
A ramping method combined with the damped PTA algorithm to find the DC operating points for nonlinear circuits. 576-579 - Taha Mehrabi, Kaamran Raahemifar, Vadim Geurkov
Design of a 4-bit programmable delay with TDC-based BIST for use in serial data links. 580-583 - Kenichi Ohhata, Hiroki Nakahara, Takuya Inoue, Toru Yazaki, Norio Chujo, Takuma Nishimoto:
Automatic adjustment system for optical interconnection transmitter using improved particle swarm optimization. 584-587 - Xiao Wu, Zhou Jin, Dan Niu, Yasuaki Inoue:
The limitation for the growth of step of DPTA method. 588-591 - T. Du, Aiwu Ruan, P. Li, Bairui Jie:
A bitstream readback based FPGA test and diagnosis system. 592-595 - Wei Wei, Li Zhang, Chip-Hong Chang
A modular design of elliptic-curve point multiplication for resource constrained devices. 596-599 - Shugang Wei:
Conversions between RNS and mixed-radix numbers using signed-digit arithmetic. 600-603 - Junbeom Yoo, Eui-Sub Kim, Dong-Ah Lee, Jong-Gyun Choi, Young-Jun Lee, Jang-Soo Lee:
NuDE 2.0: A model-based software development environment for the PLC & FPGA based digital systems in nuclear power plants. 604-607 - Vladimir V. Sergeichik, Alexander A. Ivaniuk, Chip-Hong Chang
Obfuscation and watermarking of FPGA designs based on constant value generators. 608-611
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-15 19:44 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by: